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[/] [pipelined_fixed_point_elementary_functions/] [trunk/] [ibniz/] [ibniz_units.v] - Blame information for rev 5

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1 5 leshabiruk 
 
2 
`define MAX(a,b) ( (a)>(b)? (a):(b) )
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4 
module Ibniz_generator1 ( clk, rst, ena, T_in, X_in, Y_in, V_out );
5 
 
6 
input clk;
7 
input rst;
8 
input ena;
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input wire signed [31:0] T_in;
10 
input wire signed [31:0] X_in;
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input wire signed [31:0] Y_in;
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output reg [31:0] V_out;
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14 
wire [31:0] XxY= X_in^Y_in;
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always@(posedge clk or posedge rst)
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begin
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        if ( rst )
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        begin
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        end
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        else if ( ena )
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        begin
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        //      **
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//              XY <=((XX_in * YY_in)>>>16);
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//              V_out<= ( XY * (TT_in))>>>16;
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        //      ^x7r+Md8r& (xor exch ror(7) +   )
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                V_out= XxY+ (T_in>>7) + (T_in<<(32-7));
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        end
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end
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endmodule
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32 
module Ibniz_generator2 ( clk, rst, ena, T_in, X_in, Y_in, V_out, dbg_out );
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34 
input clk;
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input rst;
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input ena;
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input wire signed [31:0] T_in;
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input wire signed [31:0] X_in;
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input wire signed [31:0] Y_in;
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output reg [31:0] V_out;
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output reg [63:0] dbg_out;
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wire signed [47:0] XY= Y_in+X_in+(X_in>>>6);
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wire signed [31:0] d_out;
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wire done;
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48 
div_pipelined div1( clk, {T_in, 16'h0}, (/*XY[31]?-XY:*/XY), d_out );
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50 
//defparam div1.BITS= 48;
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52 
always@(posedge clk or posedge rst)
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begin
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        if ( rst )
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        begin
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        end
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        else if ( ena )
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        begin
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//              if (done)
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                begin
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                //      +/
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                        V_out<= d_out;
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                        dbg_out[31:0]<= X_in+Y_in;
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                        dbg_out[63:32]<= T_in>>>16;
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                end
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//              else
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//                      V_out<= V_out>>>1;
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        end
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end
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endmodule
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72 
////============================= PERLIN NOISE ===================================
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//module Ibniz_generator7d ( clk, rst, ena, T_in, X_in, Y_in, V_out, dbg_out );
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//
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//`define NSCALE 14
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//
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//input clk;
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//input rst;
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//input ena;
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//input wire signed [31:0] T_in;
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//input wire signed [31:0] X_in;
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//input wire signed [31:0] Y_in;
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//output reg [31:0] V_out;
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//output reg [63:0] dbg_out;
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//
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//wire signed [31:0] XX= (X_in>>>`NSCALE);
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//wire signed [31:0] YY= (Y_in>>>`NSCALE);
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//reg signed [31:0] GX00;
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//reg signed [31:0] GY00;
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//reg signed [31:0] GX01;
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//reg signed [31:0] GY01;
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//reg signed [31:0] GX10;
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//reg signed [31:0] GY10;
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//reg signed [31:0] GX11;
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//reg signed [31:0] GY11;
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//reg signed [31:0] rx00;
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//reg signed [31:0] ry00;
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//reg signed [31:0] rx01;
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//reg signed [31:0] ry01;
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//reg signed [31:0] rx10;
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//reg signed [31:0] ry10;
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//reg signed [31:0] rx11;
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//reg signed [31:0] ry11;
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//reg signed [31:0] r00;
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//reg signed [31:0] r10;
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//reg signed [31:0] r01;
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//reg signed [31:0] r11;
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//wire signed [31:0] _MX= (X_in - (XX<<<`NSCALE));//& (T_in[24]?(-1):((32'h1<<<`NSCALE) - 1));
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//wire signed [31:0] _MY= (Y_in - (YY<<<`NSCALE));//& (T_in[24]?(-1):((32'h1<<<`NSCALE) - 1));
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//reg signed [31:0] __MX;
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//reg signed [31:0] __MY;
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//reg signed [31:0] MX;
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//reg signed [31:0] MY;
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//reg signed [31:0] v1;
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//reg signed [31:0] v2;
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//reg signed [31:0] v3;
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//reg signed [31:0] v4;
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//wire signed [31:0] d_out;
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//
122 
//wire done;
123 
//
124 
////defparam div1.BITS= 48;
125 
//
126 
//always@(posedge clk or posedge rst)
127 
//begin
128 
//      if ( rst )
129 
//      begin
130 
//      end
131 
//      else if ( ena )
132 
//      begin
133 
////            if (done)
134 
//              begin
135 
//              //      +/
136 
//                GX00<= XX * 16'h7353 + YY * 16'hacd7 ;
137 
////              GY00<= XX * 16'ha689 + YY * 16'h7335;
138 
//                GX01<= XX * 16'h7353 + (YY+1) * 16'hacd7 ;
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////              GY01<= XX * 16'ha689 + (YY+1) * 16'h7335;
140 
//                GX10<= (XX+1) * 16'h7353 + YY * 16'hacd7 ;
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////              GY10<= (XX+1) * 16'ha689 + YY * 16'h7335;
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//                GX11<= (XX+1) * 16'h7353 + (YY+1) * 16'hacd7 ;
143 
////              GY11<= (XX+1) * 16'ha689 + (YY+1) * 16'h7335;
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//                      rx00 <=  GX00[15] ? 0 : GX00[14] ? 1 : -1;
145 
//                      ry00 <= ~GX00[15] ? 0 : GX00[14] ? 1 : -1;
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//                      r00 <= rx00*(_MX) + ry00*_MY;
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//                      rx01 <=  GX01[15] ? 0 : GX01[14] ? 1 : -1;
148 
//                      ry01 <= ~GX01[15] ? 0 : GX01[14] ? 1 : -1;
149 
//                      r01 <= rx01*_MX + ry01*(_MY - (32'sh1<<<(`NSCALE)) );
150 
//                      rx10 <=  GX10[15] ? 0 : GX10[14] ? 1 : -1;
151 
//                      ry10 <= ~GX10[15] ? 0 : GX10[14] ? 1 : -1;
152 
//                      r10 <= rx10*(_MX - (32'sh1<<<(`NSCALE)) ) + ry10*_MY;
153 
//                      rx11 <=  GX11[15] ? 0 : GX11[14] ? 1 : -1;
154 
//                      ry11 <= ~GX11[15] ? 0 : GX11[14] ? 1 : -1;
155 
//                      r11 <= rx11*(_MX - (32'sh1<<<(`NSCALE)) ) + ry11*(_MY - (32'sh1<<<(`NSCALE)) );
156 
//
157 
//         __MX<= (_MX*_MX);
158 
//         __MY<= (_MY*_MY);
159 
//         MX<= (3*__MX - 2*_MX*(__MX>>>`NSCALE))>>>`NSCALE;
160 
//         MY<= (3*__MY - 2*_MY*(__MY>>>`NSCALE))>>>`NSCALE;
161 
//
162 
//                      v1 <= (r10 * MX + r00 * ((32'sh1<<<(`NSCALE)) - MX))>>>`NSCALE;
163 
//                      v2 <= (r11 * MX + r01 * ((32'sh1<<<(`NSCALE)) - MX))>>>`NSCALE;
164 
////                    V_out <= (((32'sh1<<<(`NSCALE))+v1)<<<(15-`NSCALE) );
165 
//                      V_out <= (((32'sh1<<<(`NSCALE))+v2 * MY + v1 * ((32'sh1<<<(`NSCALE)) - MY))>>>`NSCALE)<<<(15-`NSCALE);
166 
//
167 
//                      //                      v1<= rx00 * MX + ry00 * MY;
168 
////                    v2<= rx01 * (16'h0040 - MX) + ry01 * MY;
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////                    v3<= rx10 * MX + ry10 * (16'h0040 - MY);
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////                    v4<= rx11 * (16'h0040 - MX) + ry11 * (16'h0040 - MY);
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////                    V_out<= (v1+v2+v3+v4);
172 
//              end
173 
//      end
174 
//end
175 
//endmodule
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177 
module Ibniz_generator3 ( clk, rst, ena, T_in, X_in, Y_in, V_out );
178 
 
179 
input clk;
180 
input rst;
181 
input ena;
182 
input wire signed [31:0] T_in;
183 
input wire signed [31:0] X_in;
184 
input wire signed [31:0] Y_in;
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output reg [31:0] V_out;
186 
 
187 
always@(posedge clk or posedge rst)
188 
begin
189 
        if ( rst )
190 
        begin
191 
        end
192 
        else if ( ena )
193 
        begin
194 
                //      **
195 
                V_out= ((((X_in>>>4) * (Y_in>>>4))>>>8) * (T_in>>>16));
196 
        end
197 
end
198 
endmodule
199 
 
200 
module Ibniz_generator4 ( clk, rst, ena, T_in, X_in, Y_in, V_out );
201 
 
202 
input clk;
203 
input rst;
204 
input ena;
205 
input wire signed [31:0] T_in;
206 
input wire signed [31:0] X_in;
207 
input wire signed [31:0] Y_in;
208 
output reg [31:0] V_out;
209 
 
210 
always@(posedge clk or posedge rst)
211 
begin
212 
        if ( rst )
213 
        begin
214 
        end
215 
        else if ( ena )
216 
        begin
217 
                //      &*
218 
                V_out= (X_in & Y_in) * (T_in>>>16);
219 
        end
220 
end
221 
endmodule
222 
 
223 
 
224 
 
225 
//
226 
 
227 
 
228 
//
229 
////============================= FLOOR+CEIL ===================================
230 
module Ibniz_generator7 ( clk, rst, ena, T_in, _X_in, Y_in, V_out, dbg_out );
231 
 
232 
input clk;
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input rst;
234 
input ena;
235 
input wire signed [31:0] T_in;
236 
input wire signed [31:0] _X_in;
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wire signed [31:0] X_in= _X_in/2;
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input wire signed [31:0] Y_in;
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output reg [31:0] V_out;
240 
output reg [63:0] dbg_out;
241 
 
242 
wire signed [31:0] d_out;
243 
wire signed [31:0] d_del;
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wire signed [31:0] Y_pos_del;
245 
wire signed [31:0] s_out;
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247 
wire done;
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249 
wire signed [47:0] XY= X_in+Y_in;
250 
//wire signed [47:0] X_pos= { {48{X_in[31]}}, X_in, 16'h0};
251 
//wire signed [48:0] Y_pos= Y_in;
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wire signed [47:0] X_pos= `ABS(X_in)>`ABS(Y_in) ? { {48{X_in[31]}}, X_in, 16'h0} : { {48{Y_in[31]}}, Y_in, 16'h0};
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wire signed [48:0] Y_pos= `ABS(X_in)>`ABS(Y_in) ? Y_in : X_in;
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255 
div_pipelined div1( clk, X_pos, Y_pos, d_out );
256 
//div_pipelined div1( clk, X_in+T_in, Y_in, d_out );
257 
defparam div1.BITS= 24;
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259 
id_pipelined   id2( clk, Y_pos, Y_pos_del );
260 
defparam id2.DELAY= 24;
261 
//defparam div2.BITS= 24;
262 
 
263 
//wire signed [31:0] ys_out;
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//sin_pipelined sin1( clk, Y_pos, ys_out, _, _ );
265 
//wire signed [31:0] ds_out;
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//sin_pipelined sin2( clk, d_out, ds_out, _, _ );
267 
 
268 
wire signed [31:0] hor= -((Y_pos_del>>>5)* (T_in>>>14));
269 
wire signed [31:0] _bright= `ABS(Y_pos_del)*2-32'hffff;
270 
wire signed [31:0] bright= (_bright>>>8)*(_bright>>>8);
271 
reg signed [31:0] bright2;
272 
 
273 
always@(posedge clk or posedge rst)
274 
begin
275 
        if ( rst )
276 
        begin
277 
        end
278 
        else if ( ena )
279 
        begin
280 
//              if (done)
281 
                begin
282 
                //      //
283 
                        bright2 <= (bright>>>8)*(bright>>>8);
284 
//                      V_out<=  d_out^(Y_pos+ ((X_in+Y_in<0) ? (T_in>>>10):-(T_in>>>10)));//(  (X_in<<<16 <0 != (Y_in<<<16 <0))        ) ? 0 : 32'haaaaaaaa;
285 
                        V_out<=  (bright*(d_out[15:0]^hor[18:3])>>16)
286 
                                                | (d_out[16]^hor[20] ? 32'h80000000:0)
287 
                                                | (d_out[17]^hor[21] ? 32'h00800000:0)
288 
                                                | (d_out[18]^hor[22] ? 32'h40000000:0)
289 
                                                | (Y_pos_del==Y_in ? 32'h00400000:0);//( (X_in<<<16 <0 != (Y_in<<<16 <0))        ) ? 0 : 32'haaaaaaaa;
290 
                        dbg_out[31:0]<= X_in+Y_in;
291 
                        dbg_out[63:32]<= T_in>>>16;
292 
                end
293 
//              else
294 
//                      V_out<= V_out>>>1;
295 
        end
296 
end
297 
endmodule
298 
 
299 
//============================= MATH TEST ===================================
300 
//module Ibniz_generator7h ( clk, rst, ena, T_in, X_in, Y_in, V_out, dbg_out );
301 
//
302 
//input clk;
303 
//input rst;
304 
//input ena;
305 
//input wire signed [31:0] T_in;
306 
//input wire signed [31:0] X_in;
307 
//input wire signed [31:0] Y_in;
308 
//output reg [31:0] V_out;
309 
//output reg [63:0] dbg_out;
310 
//
311 
//wire signed [31:0] d_out;
312 
//exp_pipelined exp1( clk, (X_in)<<<4, d_out );
313 
//
314 
//
315 
//always@(posedge clk or posedge rst)
316 
//begin
317 
//      if ( rst )
318 
//      begin
319 
//      end
320 
//      else if ( ena )
321 
//      begin
322 
//              begin
323 
//                      V_out<= (       (d_out > (Y_in<<<10))   ) ? 0 : 32'haaaaaaaa;
324 
//                      dbg_out[63:32]<= T_in>>>16;
325 
//              end
326 
//      end
327 
//end
328 
//endmodule

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