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[/] [pipelined_fixed_point_elementary_functions/] [trunk/] [ibniz/] [jupiter.v] - Blame information for rev 5

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1 5 leshabiruk 
 
2 
`define MAX(a,b) ( (a)>(b)? (a):(b) )
3 
`define ABS(a) ( (a)>0? (a):(-(a)) )
4 
 
5 
 
6 
//============================= ATAN2 ===================================
7 
module Ibniz_generator5 ( clk, rst, ena, T_in, _X_in, _Y_in, V_out, dbg_out );
8 
 
9 
input clk;
10 
input rst;
11 
input ena;
12 
input wire signed [31:0] T_in;
13 
input wire signed [31:0] _X_in;
14 
input wire signed [31:0] _Y_in;
15 
output reg [31:0] V_out;
16 
output reg signed [63:0] dbg_out;
17 
reg signed [31:0] V_out2;
18 
 
19 
 wire signed [31:0] X_in =_X_in;//+_Y_in)*3/4;
20 
 wire signed [31:0] Y_in =_Y_in;//-_Y_in)*3/4;
21 
 
22 
reg [31:0] R1;
23 
reg [31:0] R2;
24 
reg [31:0] R3;
25 
 
26 
always@(posedge clk or posedge rst)
27 
begin
28 
        if ( rst )
29 
        begin
30 
        end
31 
        else if ( ena )
32 
        begin
33 
                R1 <= (((X_in+T_in[31:12])>>>7)) * 11713 + ((Y_in>>>8)+(Y_in)) * 5422133;
34 
                R2 <= R1 * 7 + (R1>>8)*1817 ;
35 
                R3 <= { R2[7:0],R2[15:8],R2[23:16], R2[7:0] ^ R2[15:8] ^ R2[23:16] ^ R2[31:24] };
36 
                //      &*
37 
//              V_out2= ((d_out1*Z_D)>>>16 );//32'h00408000 +
38 
//              V_out= ( (V3<<16)+(V2<<8)+((V1*Z_D)>>>16));
39 
//              V_out= ( T_in[24] ? (a_T^(a_out1<<<2)) : ( a_out1<<<2 )+16'h8000 );
40 
                V_out= Z_D<5 ? (R3[7:0] ? 0 : R3[8] ? -1 : R3) :
41 
//                                      (((( d_out1&32'hff000000 )*Z_D)>>>16)&32'hff000000)|
42 
//                                      (((( d_out1&32'h00ff0000 )*Z_D)>>>16)&32'h00ff0000)|
43 
                                        (((( d_out1&32'hffff0000 ))))|
44 
                                        (((( d_out1&32'h0000ffff )*Z_D)>>>16)&32'h0000ffff);//(a_out2<<<3) ^(( a_out1<<<3 ) );//+16'h8000
45 
        end
46 
end
47 
 
48 
wire signed [47:0] XY= ((a_out1)<<<2)+(a_out2)-48'h00010000;
49 
wire signed [31:0] d_out1= (_d_out1)>>>8;
50 
wire signed [47:0] _d_out1;
51 
 
52 
div_pipelined div1( clk, {T_in, 22'h0}, (/*XY[31]?-XY:*/XY), _d_out1 );
53 
 
54 
 
55 
wire signed [31:0] X_D;
56 
wire signed [31:0] Y_D;
57 
wire signed [31:0] Z_D;
58 
wire signed [31:0] s_out1;
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wire signed [31:0] s_out2;
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wire signed [47:0] a_out2 =_a_out2>>>3;
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wire signed [47:0] a_out1 =`ABS(_a_out1);
62 
wire signed [17:0] _a_out2;
63 
wire signed [17:0] _a_out1;
64 
wire signed [31:0] d_out;
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wire signed [31:0] XX= ( (X_in>>>1)*(X_in>>>1) );                                        //      30
66 
wire signed [31:0] YY= ( (Y_in>>>1)*(Y_in>>>1) );                                        //      30
67 
wire signed [31:0] MXXYY1= 32'h40000000 - (XX+YY);                                       //      30
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wire signed [31:0] MXXYY= (MXXYY1[31]) ? 0:(MXXYY1<<1) ;                  //      31
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wire signed [31:0] MYY=  (MXXYY1[31]) ? 0:(-YY<<1) ;                              //      31
70 
//wire signed [31:0] MXXYY= 32'h00010000 - (XX+YY);
71 
//wire signed [31:0] MYY= 32'h00010000 - YY;
72 
 
73 
atan2_pipelined atan1( clk, s_out1[31:14], Y_in, _a_out1, dummy1 );
74 
atan2_pipelined atan2( clk, X_in, s_out2[28:13], _a_out2, dummy2 );
75 
//atan2_pipelined atan1( clk, s_out1, Y_D, a_out1, dummy1 );
76 
//atan2_pipelined atan2( clk, X_D, s_out2, a_out2, dummy2 );
77 
 
78 
defparam atan1.IS_IBNIZ= 1;
79 
defparam atan2.IS_IBNIZ= 1;
80 
//div_pipelined mydiv( clk, a_out<<12, pix2, d_out );
81 
//id_pipelined id1( clk, X_in, X_D );
82 
//defparam id1.DELAY= 32;
83 
//id_pipelined id2( clk, Y_in, Y_D );
84 
//defparam id2.DELAY= 32;
85 
id_pipelined id3( clk, s_out2[28:13], Z_D );
86 
defparam id3.DELAY= 64;
87 
 
88 
sqrt_pipelined sqrt1( clk, MYY[31:4], s_out1[31:0], _ );
89 
sqrt_pipelined sqrt2( clk, MXXYY[31:4], s_out2[31:0], _ );
90 
//sqrt_pipelined sqrt2( clk, MXXYY[16:1], s_out2[15:0], _ );
91 
//defparam sqrt2.BITS= 20;
92 
//defparam sqrt1.BITS= 20;
93 
 
94 
endmodule
95 
 
96 
 
97 
//============================= ATAN2 ===================================
98 
module PseudoSin ( clk, rst, ena, _X_in, S_out, R_out );
99 
 
100 
input clk;
101 
input rst;
102 
input ena;
103 
input wire signed [31:0] _X_in;
104 
output reg [31:0] S_out;
105 
output reg [15:0] R_out;
106 
 
107 
wire signed [31:0] XX_in= 32'h00007fff-{ {16{1'b0}}, {_X_in[15:0]} };
108 
wire signed [31:0] X_in=
109 
                                                                        `ABS(XX_in) < 32'h00000100 ? 32'h00000100 :
110 
                                                                                                                                                        XX_in;
111 
reg signed [31:0] X1;
112 
reg signed [31:0] X2;
113 
reg signed [31:0] X2d;
114 
reg signed [31:0] X3;
115 
reg sgn_x;
116 
reg _sgn_x;
117 
reg [15:0]rgn_x;
118 
reg [15:0]_rgn_x;
119 
 
120 
always@(posedge clk or posedge rst)
121 
begin
122 
        if ( rst )
123 
        begin
124 
        end
125 
        else if ( ena )
126 
        begin
127 
        // 1 ступень конвеера
128 
                X1<= `ABS(X_in);
129 
                X2<= ((X_in) * (X_in))>>>16;
130 
                _sgn_x<= _X_in[16];
131 
                _rgn_x<= _X_in[31:16];
132 
 
133 
        // 2 ступень конвеера
134 
                X2d<= X2;
135 
                X3<= (X1 * X2)>>>16;
136 
                sgn_x<= _sgn_x;
137 
                rgn_x<=_rgn_x;
138 
 
139 
        // 3 ступень конвеера
140 
                R_out<=rgn_x;
141 
                S_out<=  (((1<<15)-(3*X2d-2*X3)) ) * (sgn_x ? -2:2);//
142 
        end
143 
end
144 
 
145 
endmodule
146 
 
147 
 
148 
 
149 
 
150 
module Psin_Texture ( clk, rst, ena, T_in, _X_in, _Y_in, V_out );
151 
 
152 
input clk;
153 
input rst;
154 
input ena;
155 
input wire signed [31:0] T_in;
156 
input wire signed [31:0] _X_in;
157 
input wire signed [31:0] _Y_in;
158 
output reg [31:0] V_out;
159 
 
160 
reg signed [31:0] SXSY;
161 
wire signed [31:0] _SSS;
162 
wire signed [31:0] MSSS= -_SSS;
163 
wire signed [31:0] etalon;
164 
 
165 
wire signed [31:0] RX;
166 
wire signed [31:0] RY;
167 
 
168 
wire signed [15:0] NX;
169 
wire signed [15:0] NY;
170 
wire signed [15:0] NXd;
171 
wire signed [15:0] NYd;
172 
wire signed [15:0] PXY= NXd+NYd;
173 
wire signed [15:0] MXY= NXd-NYd;
174 
wire signed [31:0] NXY= _SSS>0 ? (PXY[3]?{ PXY[3:0], 4'b0, PXY[3:0]*PXY[7:4], 4'b0, (_SSS[15:0]) } :0) :
175 
                                                                                        (MXY[3]?{ MXY[4:1], 4'b0, MXY[3:0]*MXY[7:4], 4'b0, (MSSS[15:0]) } :0);
176 
 
177 
 
178 
always@(posedge clk or posedge rst)
179 
begin
180 
        if ( rst )
181 
        begin
182 
        end
183 
        else if ( ena )
184 
        begin
185 
                SXSY<= ( ((( RX>>>7)*( RY>>>7))) )/2;
186 
                V_out<=
187 
//                                      _X_in==0 && _Y_in[8]==0 ? 32'haaaaaaaa :
188 
        //                              _Y_in<32'h00008000 ? SXSY :
189 
                                        NXY;
190 
//              V_out= _Y_in==0 || _X_in==0  ? 32'haaaaaaaa : (((RX)>_Y_in ? -1:0) ^ ((etalon)>_Y_in ? 32'h33333333:0) );//+32'sh00008000;
191 
        end
192 
end
193 
 
194 
sin_pipelined sin1( clk, _X_in, etalon, _, _ );
195 
 
196 
PseudoSin psinX(  clk, rst, ena, _X_in*8, RX, NX );
197 
PseudoSin psinY(  clk, rst, ena, _Y_in*8, RY, NY );
198 
 
199 
PseudoSin psinV(  clk, rst, ena, SXSY*2, _SSS, _ );
200 
id_pipelined idnx( clk, NX, NXd );
201 
id_pipelined idny( clk, NY, NYd );
202 
defparam idnx.DELAY= 4;
203 
defparam idny.DELAY= 4;
204 
 
205 
endmodule
206 
 
207 
 
208 
//============================= rotate sphere ===================================
209 
module Ibniz_generator6 ( clk, rst, ena, T_in, _X_in, _Y_in, V_out, dbg_out );
210 
 
211 
input clk;
212 
input rst;
213 
input ena;
214 
input wire signed [31:0] T_in;
215 
input wire signed [31:0] _X_in;
216 
input wire signed [31:0] _Y_in;
217 
output reg [31:0] V_out;
218 
output reg signed [63:0] dbg_out;
219 
reg signed [31:0] V_out2;
220 
 
221 
 wire signed [31:0] __X_in= _X_in+(48<<7);
222 
 
223 
 reg signed [31:0] X_in;
224 
 wire signed [31:0] Y_in =_Y_in>0 ? (_Y_in - 32'h8008)*2 : (_Y_in + 32'h8008)*2;//-_Y_in)*3/4;
225 
 
226 
reg [31:0] R1;
227 
reg [31:0] R2;
228 
reg [31:0] R3;
229 
 
230 
always@(posedge clk or posedge rst)
231 
begin
232 
        if ( rst )
233 
        begin
234 
        end
235 
        else if ( ena )
236 
        begin
237 
                X_in =__X_in>(32'sd16<<<8) ? (__X_in - 32'h9000)*2 : (__X_in + 32'h8000)*2;//+_Y_in)*3/4;
238 
                //R1 <= (((X_in+T_in[31:12])>>>7)) * 11713 + ((Y_in>>>8)+(Y_in)) * 5422133;
239 
                //R2 <= R1 * 7 + (R1>>8)*1817 ;
240 
                //R3 <= { R2[7:0],R2[15:8],R2[23:16], R2[7:0] ^ R2[15:8] ^ R2[23:16] ^ R2[31:24] };
241 
                //      &*
242 
//              V_out2= ((d_out1*Z_D)>>>16 );//32'h00408000 +
243 
//              V_out= ( (V3<<16)+(V2<<8)+((V1*Z_D)>>>16));
244 
//              V_out= ( T_in[24] ? (a_out2^(a_out1<<<2)) : ( a_out1<<<2 )+16'h8000 );
245 
                V_out= Z_D<5 ? 0://(R3[7:0] ? 0 : R3[8] ? -1 : R3) :
246 
                                        d_out1;//(a_out2<<<3) ^(( a_out1<<<3 ) );//+16'h8000
247 
        end
248 
end
249 
 
250 
//wire signed [47:0] XY= ((a_out1)<<<3)+(a_out2)-48'h00010000;
251 
wire signed [31:0] d_out1= ((a_out1<<<4)+( _X_in>0 ? (T_in>>>10):0 ))^((a_out2<<<4)+( _Y_in>0 ? (T_in>>>10):0 ));
252 
//wire signed [47:0] _d_out1;
253 
 
254 
//div_pipelined div1( clk, {T_in, 22'h0}, (/*XY[31]?-XY:*/XY), _d_out1 );
255 
 
256 
 
257 
wire signed [31:0] X_D;
258 
wire signed [31:0] Y_D;
259 
wire signed [31:0] Z_D;
260 
wire signed [31:0] s_out1;
261 
wire signed [31:0] s_out2;
262 
wire signed [47:0] a_out2 =_a_out2>>>3;
263 
wire signed [47:0] a_out1 =`ABS(_a_out1>>>1);
264 
wire signed [31:0] _a_out2;
265 
wire signed [17:0] _a_out1;
266 
wire signed [31:0] d_out;
267 
wire signed [31:0] XX= ( (X_in>>>2)*(X_in>>>2) );                                        //      30
268 
wire signed [31:0] YY= ( (Y_in>>>2)*(Y_in>>>2) );                                        //      30
269 
wire signed [31:0] MXXYY1= 32'h10000000 - (XX+YY);                                       //      30
270 
wire signed [31:0] MXXYY= (MXXYY1[31]) ? 0:(MXXYY1<<3) ;                  //      31
271 
wire signed [31:0] MYY=  (MXXYY1[31]) ? 0:(-YY<<1) ;                              //      31
272 
//wire signed [31:0] MXXYY= 32'h00010000 - (XX+YY);
273 
//wire signed [31:0] MYY= 32'h00010000 - YY;
274 
 
275 
atan2_pipelined atan1( clk, s_out1[31:14], Y_in, _a_out1, dummy1 );     //16
276 
atan2_pipelined atan2( clk, X_in-(32'sd32<<<8), s_out2[31:13], _a_out2, dummy2 );
277 
//atan2_pipelined atan1( clk, s_out1, Y_D, a_out1, dummy1 );
278 
//atan2_pipelined atan2( clk, X_D, s_out2, a_out2, dummy2 );
279 
 
280 
defparam atan1.IS_IBNIZ= 1;
281 
defparam atan2.IS_IBNIZ= 1;
282 
//div_pipelined mydiv( clk, a_out<<12, pix2, d_out );
283 
//id_pipelined id1( clk, X_in, X_D );
284 
//defparam id1.DELAY= 32;
285 
//id_pipelined id2( clk, Y_in, Y_D );
286 
//defparam id2.DELAY= 32;
287 
id_pipelined id3( clk, s_out2[28:13], Z_D );
288 
defparam id3.DELAY= 16;
289 
 
290 
sqrt_pipelined sqrt1( clk, MYY[31:4], s_out1[31:0], _ ); //32
291 
sqrt_pipelined sqrt2( clk, MXXYY[31:4], s_out2[31:0], _ );
292 
//sqrt_pipelined sqrt2( clk, MXXYY[16:1], s_out2[15:0], _ );
293 
//defparam sqrt2.BITS= 20;
294 
//defparam sqrt1.BITS= 20;
295 
 
296 
endmodule
297 
 

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