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[/] [pipelined_fixed_point_elementary_functions/] [trunk/] [math_pipelined/] [math_pipelined.sv] - Blame information for rev 6

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1 6 leshabiruk 
 
2 
module mull_pipelined(
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        input clk,
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        input [7:0] x,
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        input [7:0] y,
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        output [15:0] z
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        );
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reg [7:0] cx [7:0];
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reg [7:0] cy [7:0];
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reg [15:0] cz [15:0];
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assign z= cz[7];
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always @( posedge clk )
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begin : multblk
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        integer ind;
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        cx[0]<= x;
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        cy[0]<= y;
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        cz[0]<= y[0]? x : 0;
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        for (ind=0; ind<6; ind=ind+1)
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        begin
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                cy[ind+1]<= cy[ind];
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                cx[ind+1]<= cx[ind];
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                cz[ind+1]<= cz[ind] + (cy[ind][ind+1]? (cx[ind]<<(ind+1)) : 0);
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        end
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        cz[7]<= cz[6] + (cy[6][7]? cx[6] : 0);
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end
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endmodule
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//module div_pipelined(
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//      input clk,
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//      input [15:0] x,
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//      input [7:0] y,
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//      output [7:0] z
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//      );
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//
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//parameter BITS= 8;
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//
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//reg [15:0] cx [15:0];
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//reg [7:0] cy [7:0];
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//reg [7:0] cz [7:0];
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//assign z= cz[7];
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//
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//wire [15:0] candidate [7:0];
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//
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//assign candidate[0]= x- (y<<7);
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//
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//`define MY_EXPR(ind) assign candidate[(ind+1)]= cx[(ind)]- (cy[(ind)]<<(6-ind))
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//
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//`MY_EXPR( 0 );
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//`MY_EXPR( 1 );
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//`MY_EXPR( 2 );
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//`MY_EXPR( 3 );
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//`MY_EXPR( 4 );
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//`MY_EXPR( 5 );
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//`MY_EXPR( 6 );
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//
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//always @( posedge clk )
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//begin : multblk
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//      integer ind;
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//      integer j;
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//      cx[0]<= candidate[0][15] ? x : candidate[0];
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//      cy[0]<= y;
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//      cz[0][7]<= candidate[0][15] ? 0 : 1;
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//      for (ind=0; ind<6; ind=ind+1)
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//      begin
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//              cy[ind+1]<= cy[ind];
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//              cx[ind+1]<= candidate[ind+1][15] ? cx[ind] : candidate[ind+1];
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//              cz[ind+1][6-ind]<= candidate[ind+1][15] ? 0 : 1;
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//              for (j=7; j>6-ind; j=j-1)
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//              begin
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//                      cz[ind+1][j]<= cz[ind][j];
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//              end
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//      end
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//      cz[7][0]<= candidate[7][15] ? 0 : 1;
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//      cz[7][7:1]<=cz[6][7:1];
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//end
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//endmodule
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module div_pipelined(
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        input clk,
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        input [D_UP:0] x,
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        input [UP:0] y,
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        output [UP:0] z
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        );
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parameter BITS= 48;
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//      ���������� ���������, �� ��������������.
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parameter UP= BITS-1;
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parameter D_UP= 2*BITS-1;
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reg [D_UP:0] cx [UP:0];
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reg [UP:0] cy [UP:0];
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reg [UP:0] cz [UP:0];
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reg csign [UP:0];
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assign z= (csign[UP] ? -cz[UP]:cz[UP]);
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wire [D_UP:0] candidate [UP:0];
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wire [D_UP:0] ux= ( (x[D_UP]) ? (-x):x );
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wire [UP:0] uy= ( (y[UP]) ? (-y):y );
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wire [D_UP:0] _uy= uy;
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wire [D_UP:0] _cy [UP:0];
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always @*
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begin
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        integer ind;
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        candidate[0]<= ux- (_uy<
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        for (ind=0; ind< BITS-2 ; ind=ind+1)
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        begin
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                _cy <= cy;
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                candidate[ind+1]<= cx[ind]- (_cy[ind]<<(BITS-2-ind));
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        end
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end
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always @( posedge clk )
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begin : multblk
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        integer ind;
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        integer j;
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        csign[0]= x[D_UP]^y[UP];
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        cx[0]<= candidate[0][D_UP] ? ux : candidate[0];
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        cy[0]<= uy;
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        cz[0][UP]<= ~candidate[0][D_UP];        //      !!! sign bit?
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        for (ind=0; ind< BITS-1 ; ind=ind+1)
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        begin
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                cy[ind+1]<= cy[ind];
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                cx[ind+1]<= candidate[ind+1][D_UP] ? cx[ind] : candidate[ind+1];
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                cz[ind+1][ BITS-2 -ind]<= ~candidate[ind+1][D_UP];
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                csign[ind+1]<= csign[ind];
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                for (j=UP; j> BITS-2 -ind; j=j-1)
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                begin
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                        cz[ind+1][j]<= cz[ind][j];
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                end
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        end
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//      cz[UP][0]<= ~candidate[UP][D_UP];
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//      cz[UP][UP:1]<=cz[ BITS-2 ][UP:1];
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//      csign[UP]<= csign[UP-1];
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end
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endmodule
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module id_pipelined(
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        input clk,
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        input [UP:0] i,
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        output [UP:0] o
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        );
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parameter BITS= 32;
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parameter DELAY= 32;
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//      ���������� ���������, �� ��������������.
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parameter UP= BITS-1;
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reg [UP:0] cx [DELAY];
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assign o= cx[DELAY-1];
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always @( posedge clk )
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begin : blk
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        integer ind;
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        cx[0]<= i;
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        for (ind=0; ind< DELAY-1 ; ind=ind+1)
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        begin
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                cx[ind+1]<= cx[ind];
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        end
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end
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endmodule
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