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[/] [powersupplysequencer/] [vhdl/] [msi/] [PowerSequencer/] [PowerSequencer_tb.vhd] - Blame information for rev 2

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-- Test bed for power sequencer slice
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-- (c) 2009.. Gerhard Hoffmann  opencores@hoffmann-hochfrequenz.de
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-- Published under BSD license
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-- V1.0   first published version
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--
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-- 3 sequencer slices and 3 simulated power supplies are connected together.
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--
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-- A power-up --> normal operation --> power-down is performed.
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--
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-- Then there is another power-up --> normal operation cycle that is
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-- aborted when the middle power supply decides to run too hot at t = 70 msec.
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.all;
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entity PowerSequencer_tb is end entity PowerSequencer_tb;
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architecture tb of PowerSequencer_tb is
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        constant ticks:             integer := 30; -- Power supplies must be up within 30 10KHz clock cycles
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        signal clk, rst:            std_logic;
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        signal ps1_defective:       boolean;
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        signal ps2_defective:       boolean;
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        signal ps3_defective:       boolean;
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        signal power_up:            std_logic;                        -- the mains switch
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        signal all_power_good:      std_logic;                        -- the green power lamp
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        signal ena_stage2, ena_stage3:                    std_logic;  -- mains switch for the slaves
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        signal fail_chain123, fail_chain23, fail_chain3:  std_logic;  -- fail outputs of the groups
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        signal pu_chain123, pu_chain23, pu_chain3:        std_logic;  -- power up status of the groups
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        signal vout1, vout2, vout3:                       real;       -- output voltages of the supplies
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        signal ena_supply1:                    std_logic;
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        signal supply1good:                          std_logic;
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        signal ena_supply2:                    std_logic;
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        signal supply2good:                          std_logic;
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        signal ena_supply3:                    std_logic;
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        signal supply3good:                          std_logic;
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begin
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uck: entity work.clk_rst    -- standard clock and reset source
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  generic map(
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    clock_frequency   => 10.0e3,   -- 10 KHz
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    min_resetwidth    => 5 ms,
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    verbose           => false
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  )
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  port map(
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    clk               => clk,
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    rst               => rst
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  );
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power_up            <= '0',
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                       '1' after 10 ms,
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                       '0' after 40 ms,
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                       '1' after 70 ms,
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                       '0' after 100 ms;
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ps1_defective       <= false;
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ps2_defective       <= false, true after 90 ms;
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ps3_defective       <= false;
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all_power_good      <= power_up and pu_chain123 and (not fail_chain123);
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uPS1: entity work.PowerSequencer
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generic map (
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        ticks             => ticks,
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        last_in_chain     => false
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)
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port map (
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  clk               => clk,
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  rst               => rst,
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  ena_chain_async   => power_up,
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  fail_chain_out    => fail_chain123,
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  pu_chain_out      => pu_chain123,
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  ena_next          => ena_stage2,
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  fail_chain_in     => fail_chain23,
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  pu_chain_ini      => pu_chain23,
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  supply_enai       => ena_supply1,
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  supply_good_async => supply1good
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);
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uPS2: entity work.PowerSequencer
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generic map (
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  ticks             => ticks,
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  last_in_chain     => false
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port map (
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  clk               => clk,
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  rst               => rst,
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  ena_chain_async   => ena_stage2,
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  fail_chain_out    => fail_chain23,
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  pu_chain_out      => pu_chain23,
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  ena_next          => ena_stage3,
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  fail_chain_in     => fail_chain3,
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  pu_chain_in       => pu_chain3,
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  supply_ena        => ena_supply2,
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  supply_good_async => supply2good
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);
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uPS3: entity work.PowerSequencer
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generic map (
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  ticks             => ticks,
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  last_in_chain     => true
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)
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port map (
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  clk               => clk,
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  rst               => rst,
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  ena_chain_async   => ena_stage3,
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  fail_chain_out    => fail_chain3,
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  pu_chain_out      => pu_chain3,
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  ena_next          => open,
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  fail_chain_in     => '0',
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  pu_chain_in       => '0',
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  supply_ena        => ena_supply3,
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  supply_good_async => supply3good
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);
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-------------------------------------------------------------------------
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usup1: entity work.powersupply
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generic map (
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  voltage           => 1.8,    -- volts
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  risetime          => 2.0e-3  -- seconds
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)
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port map (
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  defective         => ps1_defective,
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  ena               => ena_supply1,
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  pgood             => supply1good,
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  vout              => vout1
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);
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usup2: entity work.powersupply
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generic map (
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  voltage           => 3.3,
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  risetime          => 2.0e-3
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)
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port map(
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  defective         => ps2_defective,
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  ena               => ena_supply2,
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  pgood             => supply2good,
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  vout              => vout2
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);
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usup3:entity work.powersupply
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generic map(
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  voltage           => 1.1,
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  risetime          => 2.0e-3
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)
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port map(
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  defective         => ps3_defective,
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  ena               => ena_supply3,
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  pgood             => supply3good,
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  vout              => vout3
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);
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end architecture tb;
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