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[/] [powersupplysequencer/] [vhdl/] [msi/] [retrigg_timer/] [retrigg_timer.vhd] - Blame information for rev 2

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1 2 dk4xp
-- retriggerable timer
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-- (c) 2005..2010 Gerhard Hoffmann opencores@hoffmann-hochfrequenz.de
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.. V1.0 published under BSD license
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--
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-- delivers a done pulse TICKS clocks after a do command.
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.all;
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entity retrigg_timer is
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        generic (
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                ticks: integer  range 2 to integer'high  -- clock ticks between do and done
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        );
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        port (
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        clk:     in  std_logic;
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        rst:     in  std_logic;
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        do:      in  std_logic;
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        done:    out std_logic;
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        running: out std_logic
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);
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end retrigg_timer;
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architecture rtl of retrigg_timer is
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        signal tctr:                             integer range 0 to ticks;
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        signal irunning: std_logic;
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        signal idone:                    std_logic;
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        function bool2sl (b: boolean) return std_logic is
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        begin
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                if b  then return '1'; else return '0';  end if;
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        end function bool2sl;
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begin
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u_timer: process(clk) is
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begin
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        if rising_edge(clk)
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        then
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                if rst = '1'
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                then
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                        tctr     <= 0;
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                        irunning <= '0';
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                elsif (do = '1')
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                then
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                        tctr     <= ticks -1;
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                        irunning <= '1';
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                elsif ((irunning = '1') and (idone = '0'))
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                then
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                        tctr <= tctr - 1;
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                elsif (idone = '1')
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                then
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                        irunning <= '0';
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                end if; -- rst
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        -- we are not done when a retrigger comes
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        -- just before the timeout
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                idone <= bool2sl((tctr = 1) and (do /= '1'));
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        end if; -- rising_edge()
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end process u_timer;
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done    <= idone;
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running <= irunning;
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end architecture rtl;
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