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[/] [powersupplysequencer/] [vhdl/] [msi/] [retrigg_timer/] [retrigg_timer_tb.vhd] - Blame information for rev 2

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1 2 dk4xp
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-- (c) 2005..2010 Gerhard Hoffmann opencores@hoffmann-hochfrequenz.de
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.. V1.0 published under BSD license
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----------------------------------------------------------------------------------------------------
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-- Tool versions:   Modelsim, ISE 6 .. 10
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-- Description:     testbed for retriggerable timer
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-- calls lib:       ieee standard
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-- calls entities:  clk_rst, retrigg_timer
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----------------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.all;
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entity retrigg_timer_tb is begin end retrigg_timer_tb;
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architecture tb of retrigg_timer_tb is
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  signal rst, clk: std_logic;
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  signal do, done, running: std_logic;
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begin
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u_clk_rst: entity work.clk_rst
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  generic  map(
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    verbose           => false,
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    clock_frequency   => 100.0e6,
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    min_resetwidth    => 46 ns
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  )
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  port map(
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    clk               => clk,
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    rst               => rst
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  );
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do <= '0',
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      '1' after  95 ns, '0' after 105 ns,  -- trigger first time
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      '1' after 205 ns, '0' after 215 ns,  -- trigger second time
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      '1' after 245 ns, '0' after 255 ns;  -- and once more to test retrigger
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uut: entity work.retrigg_timer
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  generic map (
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    ticks     => 5
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  )
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  port map (
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    clk       => clk,
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    rst       => rst,
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    do        => do,
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    done      => done,
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    running   => running
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  );
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end tb;
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