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[/] [powersupplysequencer/] [vhdl/] [tb/] [clk_rst/] [clk_rst.vhd] - Blame information for rev 2

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1 2 dk4xp
--! @file
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--! @brief clock for simulation with selectable frequency and reset with selectable width.
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-- (c) jul 2007... Gerhard Hoffmann  opencores@hoffmann-hochfrequenz.de
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-- Published under BSD license
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-- V1.0  first published version
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--
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--! @details Solution to an everyday problem.
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--! This module produces a clock for a simulation with selectable frequency
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--! and a reset signal with selectable width. The duty cycle is 1:1.
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--! The reset is active from the beginning and removed synchronously shortly
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--! after a rising clock edge.
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--! setting verbose to true gives some diagnostics.
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--
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-- Make sure that your simulator has a time resolution of at least 1 ps.
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-- For modelsim, this is set up by the various modelsim.ini files
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-- and/or the project file (foobar.mpf)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity clk_rst is
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  generic (
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    verbose:         boolean := false;
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    clock_frequency: real    := 100.0e6;  -- 100 MHz
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    min_resetwidth:  time    := 12 ns     -- minimum resetwidth, is synchronized to clk  
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        );
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  port (
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    clk: out std_logic;
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    rst: out std_logic
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  );
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end entity clk_rst;
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architecture rtl of clk_rst is
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-- The clock frequency is given in Hz in floating point format.
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-- compute the equivalent half cycle time.
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function frequency2halfcycle(f: real; verbose: boolean) return time is
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  variable picoseconds: real;
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  variable retval:      time;
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begin
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  assert f > 1.0e-10
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    report "clk_and_rst.vhd: requested clock frequency is unreasonably low or even negative - danger of 1/0.0"
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    severity error;
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  picoseconds := (0.5 / f ) / 1.0e-12;
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  retval := integer(picoseconds) * 1 ps;
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  if verbose then
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    report "function frequency2halfcycle() in clk_rst.vhd: picoseconds = " & real'image(picoseconds);
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    report "halfcycle = " & time'image(retval);
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  end if;
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  assert retval > 0 ps
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    report "frequency2halfcycle(): length of halfcycle truncated to 0 ps. "
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         & "Set simulator resolution to 1 ps or smaller in modelsim.ini, foobar.mpf or whatever your simulator uses"
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    severity error;
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  return retval;
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end;
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signal iclk:      std_logic := '0';  -- entity-internal clk and rst
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signal irst:      std_logic := '1';
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constant halfcycle: time    := frequency2halfcycle(clock_frequency, verbose);
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----------------------------------------------------------------------------------------------------   
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begin
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--
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-- generate the internal system clock
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u_sysclock: process is
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begin
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   wait for halfcycle;
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   iclk <= '1';
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   wait for halfcycle;
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   iclk <= '0';
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end process u_sysclock;
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--
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-- generate internal reset
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u_rst: process is
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begin
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   irst <= '1';
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   wait for min_resetwidth;
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   wait until rising_edge(iclk);
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   irst <= '0';
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   wait;    -- forever
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end process u_rst;
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-- make the local signals public
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clk <= iclk;
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rst <= irst;
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end architecture rtl;
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