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[/] [qaz_libs/] [trunk/] [BFM/] [src/] [8b10b/] [deserializer_8b10b_bfm_if.sv] - Blame information for rev 46

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1 46 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2018 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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// Chuck Benz, Hollis, NH   Copyright (c)2002
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//
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// The information and description contained herein is the
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// property of Chuck Benz.
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//
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// Permission is granted for any reuse of this information
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// and description as long as this copyright notice is
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// preserved.  Modifications may be made as long as this
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// notice is preserved.
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// per Widmer and Franaszek
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interface
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  deserializer_8b10b_bfm_if
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  ( input clk
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  , input serial_in
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  );
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// module decode_8b10b (datain, dispin, dataout, dispout, code_err, disp_err) ;
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  // input [9:0]   datain ;
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  // input              dispin ;
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  // output [8:0]       dataout ;
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  // output     dispout ;
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  // output     code_err ;
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  // output     disp_err ;
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  wire [9:0] datain;
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  wire dispin;
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  wire [8:0]    dataout ;
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  wire  code_err ;
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  wire  disp_err ;
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  wire ai = datain[0] ;
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  wire bi = datain[1] ;
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  wire ci = datain[2] ;
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  wire di = datain[3] ;
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  wire ei = datain[4] ;
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  wire ii = datain[5] ;
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  wire fi = datain[6] ;
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  wire gi = datain[7] ;
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  wire hi = datain[8] ;
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  wire ji = datain[9] ;
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  wire aeqb = (ai & bi) | (!ai & !bi) ;
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  wire ceqd = (ci & di) | (!ci & !di) ;
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  wire p22 = (ai & bi & !ci & !di) |
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             (ci & di & !ai & !bi) |
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             ( !aeqb & !ceqd) ;
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  wire p13 = ( !aeqb & !ci & !di) |
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             ( !ceqd & !ai & !bi) ;
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  wire p31 = ( !aeqb & ci & di) |
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             ( !ceqd & ai & bi) ;
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  wire p40 = ai & bi & ci & di ;
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  wire p04 = !ai & !bi & !ci & !di ;
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  wire disp6a = p31 | (p22 & dispin) ; // pos disp if p22 and was pos, or p31.
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   wire disp6a2 = p31 & dispin ;  // disp is ++ after 4 bits
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   wire disp6a0 = p13 & ! dispin ; // -- disp after 4 bits
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  wire disp6b = (((ei & ii & ! disp6a0) | (disp6a & (ei | ii)) | disp6a2 |
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                  (ei & ii & di)) & (ei | ii | di)) ;
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  // The 5B/6B decoding special cases where ABCDE != abcde
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  wire p22bceeqi = p22 & bi & ci & (ei == ii) ;
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  wire p22bncneeqi = p22 & !bi & !ci & (ei == ii) ;
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  wire p13in = p13 & !ii ;
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  wire p31i = p31 & ii ;
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  wire p13dei = p13 & di & ei & ii ;
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  wire p22aceeqi = p22 & ai & ci & (ei == ii) ;
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  wire p22ancneeqi = p22 & !ai & !ci & (ei == ii) ;
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  wire p13en = p13 & !ei ;
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  wire anbnenin = !ai & !bi & !ei & !ii ;
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  wire abei = ai & bi & ei & ii ;
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  wire cdei = ci & di & ei & ii ;
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  wire cndnenin = !ci & !di & !ei & !ii ;
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  // non-zero disparity cases:
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  wire p22enin = p22 & !ei & !ii ;
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  wire p22ei = p22 & ei & ii ;
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  //wire p13in = p12 & !ii ;
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  //wire p31i = p31 & ii ;
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  wire p31dnenin = p31 & !di & !ei & !ii ;
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  //wire p13dei = p13 & di & ei & ii ;
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  wire p31e = p31 & ei ;
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  wire compa = p22bncneeqi | p31i | p13dei | p22ancneeqi |
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                p13en | abei | cndnenin ;
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  wire compb = p22bceeqi | p31i | p13dei | p22aceeqi |
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                p13en | abei | cndnenin ;
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  wire compc = p22bceeqi | p31i | p13dei | p22ancneeqi |
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                p13en | anbnenin | cndnenin ;
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  wire compd = p22bncneeqi | p31i | p13dei | p22aceeqi |
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                p13en | abei | cndnenin ;
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  wire compe = p22bncneeqi | p13in | p13dei | p22ancneeqi |
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                p13en | anbnenin | cndnenin ;
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  wire ao = ai ^ compa ;
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  wire bo = bi ^ compb ;
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  wire co = ci ^ compc ;
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  wire _do = di ^ compd ;
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  wire eo = ei ^ compe ;
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  wire feqg = (fi & gi) | (!fi & !gi) ;
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  wire heqj = (hi & ji) | (!hi & !ji) ;
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  wire fghj22 = (fi & gi & !hi & !ji) |
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                (!fi & !gi & hi & ji) |
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                ( !feqg & !heqj) ;
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  wire fghjp13 = ( !feqg & !hi & !ji) |
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                 ( !heqj & !fi & !gi) ;
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  wire fghjp31 = ( (!feqg) & hi & ji) |
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                 ( !heqj & fi & gi) ;
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  wire dispout = (fghjp31 | (disp6b & fghj22) | (hi & ji)) & (hi | ji) ;
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  wire ko = ( (ci & di & ei & ii) | ( !ci & !di & !ei & !ii) |
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                (p13 & !ei & ii & gi & hi & ji) |
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                (p31 & ei & !ii & !gi & !hi & !ji)) ;
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  wire alt7 =   (fi & !gi & !hi & // 1000 cases, where disp6b is 1
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                 ((dispin & ci & di & !ei & !ii) | ko |
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                  (dispin & !ci & di & !ei & !ii))) |
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                (!fi & gi & hi & // 0111 cases, where disp6b is 0
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                 (( !dispin & !ci & !di & ei & ii) | ko |
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                  ( !dispin & ci & !di & ei & ii))) ;
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  wire k28 = (ci & di & ei & ii) | ! (ci | di | ei | ii) ;
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  // k28 with positive disp into fghi - .1, .2, .5, and .6 special cases
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  wire k28p = ! (ci | di | ei | ii) ;
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  wire fo = (ji & !fi & (hi | !gi | k28p)) |
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            (fi & !ji & (!hi | gi | !k28p)) |
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            (k28p & gi & hi) |
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            (!k28p & !gi & !hi) ;
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  wire go = (ji & !fi & (hi | !gi | !k28p)) |
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            (fi & !ji & (!hi | gi |k28p)) |
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            (!k28p & gi & hi) |
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            (k28p & !gi & !hi) ;
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  wire ho = ((ji ^ hi) & ! ((!fi & gi & !hi & ji & !k28p) | (!fi & gi & hi & !ji & k28p) |
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                            (fi & !gi & !hi & ji & !k28p) | (fi & !gi & hi & !ji & k28p))) |
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            (!fi & gi & hi & ji) | (fi & !gi & !hi & !ji) ;
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  wire disp6p = (p31 & (ei | ii)) | (p22 & ei & ii) ;
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  wire disp6n = (p13 & ! (ei & ii)) | (p22 & !ei & !ii) ;
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  wire disp4p = fghjp31 ;
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  wire disp4n = fghjp13 ;
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  assign code_err = p40 | p04 | (fi & gi & hi & ji) | (!fi & !gi & !hi & !ji) |
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                    (p13 & !ei & !ii) | (p31 & ei & ii) |
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                    (ei & ii & fi & gi & hi) | (!ei & !ii & !fi & !gi & !hi) |
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                    (ei & !ii & gi & hi & ji) | (!ei & ii & !gi & !hi & !ji) |
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                    (!p31 & ei & !ii & !gi & !hi & !ji) |
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                    (!p13 & !ei & ii & gi & hi & ji) |
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                    (((ei & ii & !gi & !hi & !ji) |
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                      (!ei & !ii & gi & hi & ji)) &
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                     ! ((ci & di & ei) | (!ci & !di & !ei))) |
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                    (disp6p & disp4p) | (disp6n & disp4n) |
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                    (ai & bi & ci & !ei & !ii & ((!fi & !gi) | fghjp13)) |
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                    (!ai & !bi & !ci & ei & ii & ((fi & gi) | fghjp31)) |
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                    (fi & gi & !hi & !ji & disp6p) |
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                    (!fi & !gi & hi & ji & disp6n) |
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                    (ci & di & ei & ii & !fi & !gi & !hi) |
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                    (!ci & !di & !ei & !ii & fi & gi & hi) ;
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  assign dataout = {ko, ho, go, fo, eo, _do, co, bo, ao} ;
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  // my disp err fires for any legal codes that violate disparity, may fire for illegal codes
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   assign disp_err = ((dispin & disp6p) | (disp6n & !dispin) |
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                      (dispin & !disp6n & fi & gi) |
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                      (dispin & ai & bi & ci) |
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                      (dispin & !disp6n & disp4p) |
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                      (!dispin & !disp6p & !fi & !gi) |
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                      (!dispin & !ai & !bi & !ci) |
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                      (!dispin & !disp6p & disp4n) |
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                      (disp6p & disp4p) | (disp6n & disp4n)) ;
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// endmodule
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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  // --------------------------------------------------------------------
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  localparam COMMAS_TO_LOCK = 5;
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  localparam K28_5 = 10'b1010000011;
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  // --------------------------------------------------------------------
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  logic [9:0] parallel_data = 0;
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  logic [9:0] comma_char = K28_5;
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  int cycle;
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  bit dataout_valid;
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  // --------------------------------------------------------------------
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  default clocking cb @(posedge clk);
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    input serial_in;
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    inout parallel_data;
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    inout cycle;
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    inout dataout_valid;
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  endclocking
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  // --------------------------------------------------------------------
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  task zero_cycle_delay;
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    ##0;
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  endtask: zero_cycle_delay
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  // --------------------------------------------------------------------
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  wire comma_sync = (parallel_data == comma_char);
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  always @(cb)
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    cb.parallel_data <= {cb.serial_in, cb.parallel_data[9:1]};
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  // --------------------------------------------------------------------
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  always @(cb)
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    if(comma_sync)
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      cb.cycle <= 1;
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    else if(cb.cycle == 9)
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      cb.cycle <= 0;
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    else
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      cb.cycle <= cb.cycle + 1;
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  // --------------------------------------------------------------------
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  int locked_count = 0;
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  wire locked = locked_count >= COMMAS_TO_LOCK;
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  always @(cb iff comma_sync)
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    if(cb.cycle == 0)
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    begin
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      if(locked_count < COMMAS_TO_LOCK)
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        locked_count++;
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    end
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    else
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      locked_count = 0;
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  // --------------------------------------------------------------------
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  reg [9:0] parallel_data_r;
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  wire [9:0] parallel_data_msb = {<<{parallel_data_r}};
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  wire [5:0] data_6b = parallel_data_msb[9:4];
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  wire [3:0] data_4b = parallel_data_msb[3:0];
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  always @(cb)
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    if(cb.cycle == 0)
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      parallel_data_r <= cb.parallel_data;
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  // --------------------------------------------------------------------
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  int disparity;
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  int running_disparity;
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  always @(cb)
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    if(~locked)
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      if(dispout)
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        running_disparity = 1;
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      else
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        running_disparity = -1;
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    else if(cb.cycle == 0)
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    begin
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      disparity = 0;
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      for(int i = 0; i < 10; i++)
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        if(cb.parallel_data[i] == 1'b1)
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          disparity++;
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        else
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          disparity--;
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      running_disparity = running_disparity - disparity;
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    end
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  // --------------------------------------------------------------------
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  assign datain = parallel_data_r;
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  logic dispin_r;
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  assign dispin = dispin_r;
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295
  always @(cb)
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    if(cb.cycle == 0)
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      dispin_r <= dispout;
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  // --------------------------------------------------------------------
300
  always @(cb)
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    if(cb.cycle == 5)
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      cb.dataout_valid <= 1;
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    else
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      cb.dataout_valid <= 0;
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  // --------------------------------------------------------------------
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  wire [7:0] dataout_msb = {<<{dataout[7:0]}};
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  wire [4:0] data_5b = dataout[4:0];
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  wire [2:0] data_3b = dataout[7:5];
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  wire data_k = dataout[8];
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// --------------------------------------------------------------------
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endinterface

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