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qaztronic |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module tb_top;
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import uvm_pkg::*;
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import tb_top_pkg::*;
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import riffa_pkg::*;
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`include "uvm_macros.svh"
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// --------------------------------------------------------------------
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wire clk_100mhz;
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wire tb_clk = clk_100mhz;
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wire tb_rst;
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wire clk_1000mhz;
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tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
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// --------------------------------------------------------------------
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wire clk = clk_100mhz;
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wire reset;
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sync_reset sync_reset_i(tb_clk, tb_rst, reset);
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// --------------------------------------------------------------------
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riffa_chnl_if #(N) chnl_bus(.*);
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riffa_register_if #(.N(N), .B(B)) r_if(.*); // dword sized (32 bit) registers
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riffa_register_file #(.N(N), .B(B))
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dut(.*);
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// --------------------------------------------------------------------
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for(genvar j = 0; j < r_if.RC; j++)
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assign r_if.register_in[j] = r_if.register_out[j];
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// --------------------------------------------------------------------
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riffa_config #(N) cfg_h = new(chnl_bus);
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initial
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begin
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uvm_config_db #(riffa_config #(N))::set(null, "*", "riffa_config", cfg_h);
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run_test("t_debug");
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end
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// --------------------------------------------------------------------
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endmodule
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