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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////

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//////////////////////////////////////////////////////////////////////

module

  riffa_chn_tx

  #(

    N, // data bus width in bytes

    D = 2 // TX data fifo depth

  )

  (

    riffa_chnl_if chnl_in,

    input tx_ready,

    input tx_done,

    output reg [31:0] tx_index,

    input tx_last,

    input [31:0] tx_len,

    input [30:0] tx_off,

    input clk,

    input reset

  );

  // --------------------------------------------------------------------

  //

  localparam RW = (N/4); // width of the bus in 32 bit words

  // --------------------------------------------------------------------

  //

  riffa_chnl_tx_fsm

    riffa_chnl_tx_fsm_i

    (

      .tx(chnl_in.tx),

      .tx_ack(chnl_in.tx_ack),

      .*

    );

  // --------------------------------------------------------------------

  //

  always_ff @(posedge clk)

    if(reset | ~chnl_in.tx)

      tx_index = 0;

    else if(chnl_in.tx_data_valid & chnl_in.tx_data_ren)

      tx_index <= tx_index + RW;

// --------------------------------------------------------------------

//

endmodule