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[/] [qaz_libs/] [trunk/] [axi4_lib/] [sim/] [src/] [axi4_bfm/] [axi4_master_bfm_if.sv] - Blame information for rev 29

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1 29 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
27
 
28
 
29
interface
30
  axi4_master_bfm_if
31
  #(
32
    A = 32, // address bus width
33
    N = 8,  // data bus width in bytes
34
    I = 1   // ID width
35
  )
36
  (
37
    axi4_if axi4_s,
38
    input   aresetn,
39
    input   aclk
40
  );
41
 
42
  logic [(A-1):0]    araddr;
43
  logic [1:0]        arburst;
44
  logic [3:0]        arcache;
45
  logic [(I-1):0]    arid;
46
  logic [7:0]        arlen;
47
  logic              arlock;
48
  logic [2:0]        arprot;
49
  logic [3:0]        arqos;
50
  logic              arready;
51
  logic [3:0]        arregion;
52
  logic [2:0]        arsize;
53
  logic              arvalid;
54
  logic [(A-1):0]    awaddr;
55
  logic [1:0]        awburst;
56
  logic [3:0]        awcache;
57
  logic [(I-1):0]    awid;
58
  logic [7:0]        awlen;
59
  logic              awlock;
60
  logic [2:0]        awprot;
61
  logic [3:0]        awqos;
62
  logic              awready;
63
  logic [3:0]        awregion;
64
  logic [2:0]        awsize;
65
  logic              awvalid;
66
  logic [(I-1):0]    bid;
67
  logic              bready;
68
  logic [1:0]        bresp;
69
  logic              bvalid;
70
  logic [(8*N)-1:0]  rdata;
71
  logic [(I-1):0]    rid;
72
  logic              rlast;
73
  logic              rready;
74
  logic [1:0]        rresp;
75
  logic              rvalid;
76
  logic [(8*N)-1:0]  wdata;
77
  logic [(I-1):0]    wid;
78
  logic              wlast;
79
  logic              wready;
80
  logic [N-1:0]      wstrb;
81
  logic              wvalid;
82
 
83
 
84
  // --------------------------------------------------------------------
85
  //
86
  default clocking cb @(posedge aclk);
87
    output  arid;
88
    output  araddr;
89
    output  arburst;
90
    output  arcache;
91
    output  awid;
92
    output  arlen;
93
    output  arlock;
94
    output  arprot;
95
    output  arqos;
96
    input   arready;
97
    output  arregion;
98
    output  arsize;
99
    output  arvalid;
100
    output  awaddr;
101
    output  awburst;
102
    output  awcache;
103
    output  awlen;
104
    output  awlock;
105
    output  awprot;
106
    output  awqos;
107
    input   awready;
108
    output  awregion;
109
    output  awsize;
110
    output  awvalid;
111
    output  bready;
112
    input   bid;
113
    input   bresp;
114
    input   bvalid;
115
    input   rdata;
116
    input   rid;
117
    input   rlast;
118
    output  rready;
119
    input   rresp;
120
    input   rvalid;
121
    output  wdata;
122
    output  wlast;
123
    input   wready;
124
    output  wstrb;
125
    output  wvalid;
126
    input   aresetn;
127
    input   aclk;
128
  endclocking
129
 
130
 
131
  // --------------------------------------------------------------------
132
  //
133
  assign axi4_s.arid     = arid;
134
  assign axi4_s.araddr   = araddr;
135
  assign axi4_s.arburst  = arburst;
136
  assign axi4_s.arcache  = arcache;
137
  assign axi4_s.awid     = awid;
138
  assign axi4_s.arlen    = arlen;
139
  assign axi4_s.arlock   = arlock;
140
  assign axi4_s.arprot   = arprot;
141
  assign axi4_s.arqos    = arqos;
142
  assign arready         = axi4_s.arready;
143
  assign axi4_s.arregion = arregion;
144
  assign axi4_s.arsize   = arsize;
145
  assign axi4_s.arvalid  = arvalid;
146
  assign axi4_s.awaddr   = awaddr;
147
  assign axi4_s.awburst  = awburst;
148
  assign axi4_s.awcache  = awcache;
149
  assign axi4_s.awlen    = awlen;
150
  assign axi4_s.awlock   = awlock;
151
  assign axi4_s.awprot   = awprot;
152
  assign axi4_s.awqos    = awqos;
153
  assign awready         = axi4_s.awready;
154
  assign axi4_s.awregion = awregion;
155
  assign axi4_s.awsize   = awsize;
156
  assign axi4_s.awvalid  = awvalid;
157
  assign axi4_s.bready   = bready;
158
  assign bid             = axi4_s.bid;
159
  assign bresp           = axi4_s.bresp;
160
  assign bvalid          = axi4_s.bvalid;
161
  assign rdata           = axi4_s.rdata;
162
  assign rid             = axi4_s.rid;
163
  assign rlast           = axi4_s.rlast;
164
  assign axi4_s.rready   = rready;
165
  assign rresp           = axi4_s.rresp;
166
  assign rvalid          = axi4_s.rvalid;
167
  assign axi4_s.wdata    = wdata;
168
  assign axi4_s.wlast    = wlast;
169
  assign wready          = axi4_s.wready;
170
  assign axi4_s.wstrb    = wstrb;
171
  assign axi4_s.wvalid   = wvalid;
172
 
173
 
174
  // --------------------------------------------------------------------
175
  //
176
  function void
177
    ar_default;
178
 
179
    cb.araddr   <= 'bx;
180
    cb.arburst  <= 'bx;
181
    cb.arcache  <= 'bx;
182
    cb.arid     <= 'bx;
183
    cb.arlen    <= 'bx;
184
    cb.arlock   <= 'bx;
185
    cb.arprot   <= 'bx;
186
    cb.arqos    <= 'bx;
187
    cb.arregion <= 'bx;
188
    cb.arsize   <= 'bx;
189
    cb.arvalid  <= 0;
190
 
191
  endfunction: ar_default
192
 
193
 
194
  // --------------------------------------------------------------------
195
  //
196
  function void
197
    aw_default;
198
 
199
    cb.awaddr   <= 'bx;
200
    cb.awburst  <= 'bx;
201
    cb.awcache  <= 'bx;
202
    cb.awid     <= 'bx;
203
    cb.awlen    <= 'bx;
204
    cb.awlock   <= 'bx;
205
    cb.awprot   <= 'bx;
206
    cb.awqos    <= 'bx;
207
    cb.awregion <= 'bx;
208
    cb.awsize   <= 'bx;
209
    cb.awvalid  <= 0;
210
 
211
  endfunction: aw_default
212
 
213
 
214
  // --------------------------------------------------------------------
215
  //
216
  function void
217
    r_default;
218
 
219
    cb.rready <= 0;
220
 
221
  endfunction: r_default
222
 
223
 
224
  // --------------------------------------------------------------------
225
  //
226
  function void
227
    w_default;
228
 
229
    cb.wdata    <= 'bx;
230
    cb.wlast    <= 'bx;
231
    cb.wstrb    <= {N{1'b1}};
232
    cb.wvalid   <= 0;
233
 
234
  endfunction: w_default
235
 
236
 
237
  // --------------------------------------------------------------------
238
  //
239
  function void
240
    b_default;
241
 
242
    cb.bready   <= 0;
243
 
244
  endfunction: b_default
245
 
246
 
247
  // --------------------------------------------------------------------
248
  //
249
  function void
250
    init;
251
 
252
    ar_default();
253
    r_default();
254
    aw_default();
255
    w_default();
256
    b_default();
257
 
258
  endfunction: init
259
 
260
 
261
  // --------------------------------------------------------------------
262
  //
263
  task
264
    zero_cycle_delay;
265
 
266
    ##0;
267
 
268
  endtask: zero_cycle_delay
269
 
270
 
271
  // --------------------------------------------------------------------
272
  //
273
  import tb_bfm_pkg::*;
274
  import axi4_transaction_pkg::*;
275
 
276
 
277
  // --------------------------------------------------------------------
278
  //
279
  class ar_master_transaction_class #(A = 32, N = 8, I = 1)
280
    extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
281
 
282
    // --------------------------------------------------------------------
283
    //
284
    task automatic
285
      transaction
286
      (
287
        ref T tr_h
288
      );
289
 
290
      ->this.start;
291
 
292
      ##(tr_h.delay_h.next());
293
 
294
      cb.araddr   <= tr_h.addr;
295
      cb.arid     <= tr_h.id;
296
      cb.arlen    <= tr_h.len;
297
      cb.arsize   <= tr_h.size;
298
 
299
      cb.arburst  <= tr_h.burst;
300
      cb.arcache  <= tr_h.cache;
301
      cb.arlock   <= tr_h.lock;
302
      cb.arprot   <= tr_h.prot;
303
      cb.arqos    <= tr_h.qos;
304
      cb.arregion <= tr_h.region;
305
      cb.arvalid  <= 1;
306
 
307
      $display("^^^ %16.t | %m | master AR transaction @ 0x%08x |", $time, tr_h.addr);
308
 
309
      ##1;
310
      wait(cb.arready);
311
 
312
      ##0;
313
      ar_default();
314
 
315
      ->this.done;
316
 
317
    endtask: transaction
318
 
319
 
320
  // --------------------------------------------------------------------
321
  //
322
  endclass: ar_master_transaction_class
323
 
324
 
325
  // --------------------------------------------------------------------
326
  //
327
  class r_master_transaction_class #(A = 32, N = 8, I = 1)
328
    extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
329
 
330
    // --------------------------------------------------------------------
331
    //
332
    task automatic
333
      transaction
334
      (
335
        ref T tr_h
336
      );
337
 
338
      ->this.start;
339
 
340
      tr_h.data_h = new(tr_h.len);
341
 
342
      foreach(tr_h.payload_h.w[i])
343
      begin
344
        ##(tr_h.delay_h.next());
345
        cb.rready <= 1;
346
        ##1;
347
 
348
        wait(cb.rvalid);
349
        ##0;
350
 
351
        tr_h.data_h.w[i] = cb.rdata;
352
 
353
        $display("^^^ %16.t | %m | master R transaction | %d | 0x%016x |", $time, i, tr_h.data_h.w[i]);
354
        r_default();
355
      end
356
 
357
      ->this.done;
358
 
359
    endtask: transaction
360
 
361
 
362
  // --------------------------------------------------------------------
363
  //
364
  endclass: r_master_transaction_class
365
 
366
 
367
  // --------------------------------------------------------------------
368
  //
369
  class aw_master_transaction_class #(A = 32, N = 8, I = 1)
370
    extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
371
 
372
    // --------------------------------------------------------------------
373
    //
374
    task automatic
375
      transaction
376
      (
377
        ref T tr_h
378
      );
379
 
380
      ->this.start;
381
 
382
      ##(tr_h.delay_h.next());
383
 
384
      cb.awaddr   <= tr_h.addr;
385
      cb.awid     <= tr_h.id;
386
      cb.awlen    <= tr_h.len;
387
      cb.awsize   <= tr_h.size;
388
 
389
      cb.awburst  <= tr_h.burst;
390
      cb.awcache  <= tr_h.cache;
391
      cb.awlock   <= tr_h.lock;
392
      cb.awprot   <= tr_h.prot;
393
      cb.awqos    <= tr_h.qos;
394
      cb.awregion <= tr_h.region;
395
      cb.awvalid  <= 1;
396
 
397
      $display("^^^ %16.t | %m | master AW transaction @ 0x%08x |", $time, tr_h.addr);
398
 
399
      ##1;
400
      wait(cb.awready);
401
 
402
      ##0;
403
      aw_default();
404
 
405
      ->this.done;
406
 
407
    endtask: transaction
408
 
409
 
410
  // --------------------------------------------------------------------
411
  //
412
  endclass: aw_master_transaction_class
413
 
414
 
415
  // --------------------------------------------------------------------
416
  //
417
  class w_master_transaction_class #(A = 32, N = 8, I = 1)
418
    extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
419
 
420
    // --------------------------------------------------------------------
421
    //
422
    task automatic
423
      transaction
424
      (
425
        ref T tr_h
426
      );
427
 
428
      ->this.start;
429
 
430
      foreach(tr_h.payload_h.w[i])
431
      begin
432
        ##(tr_h.delay_h.next());
433
 
434
        cb.wdata  <= tr_h.payload_h.w[i];
435
        // cb.wstrb  <= tr_h.strb;    // need to fix
436
 
437
        if(i < tr_h.payload_h.w.size - 1)
438
          cb.wlast   <= 0;
439
        else
440
          cb.wlast   <= 1;
441
 
442
        cb.wvalid <= 1;
443
 
444
        ##1;
445
        wait(cb.wready);
446
 
447
        ##0;
448
        $display("^^^ %16.t | %m | master W transaction | %d | 0x%016x |", $time, i, tr_h.payload_h.w[i]);
449
        w_default();
450
      end
451
 
452
      ->this.done;
453
 
454
    endtask: transaction
455
 
456
 
457
  // --------------------------------------------------------------------
458
  //
459
  endclass: w_master_transaction_class
460
 
461
 
462
  // --------------------------------------------------------------------
463
  //
464
  class b_master_transaction_class #(A = 32, N = 8, I = 1)
465
    extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
466
 
467
    // --------------------------------------------------------------------
468
    //
469
    task automatic
470
      transaction
471
      (
472
        ref T tr_h
473
      );
474
 
475
      ->this.start;
476
 
477
      ##(tr_h.delay_h.next());
478
      cb.bready <= 1;
479
      ##1;
480
 
481
      wait(cb.bvalid);
482
      ##0;
483
 
484
      $display("^^^ %16.t | %m | master B transaction | 0x%x |", $time, cb.bresp);
485
      b_default();
486
 
487
      ->this.done;
488
 
489
    endtask: transaction
490
 
491
 
492
  // --------------------------------------------------------------------
493
  //
494
  endclass: b_master_transaction_class
495
 
496
 
497
  // --------------------------------------------------------------------
498
  //
499
  ar_master_transaction_class #(.A(A), .N(N), .I(I))  ar_h;
500
  r_master_transaction_class  #(.A(A), .N(N), .I(I))  r_h;
501
  aw_master_transaction_class #(.A(A), .N(N), .I(I))  aw_h;
502
  w_master_transaction_class #(.A(A), .N(N), .I(I))   w_h;
503
  b_master_transaction_class  #(.A(A), .N(N), .I(I))  b_h;
504
 
505
  initial
506
  begin
507
    init();
508
    ar_h = new;
509
    ar_h.init();
510
    r_h = new;
511
    r_h.init();
512
    aw_h = new;
513
    aw_h.init();
514
    w_h = new;
515
    w_h.init();
516
    b_h = new;
517
    b_h.init();
518
  end
519
 
520
 
521
// --------------------------------------------------------------------
522
//
523
 
524
endinterface
525
 
526
 

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