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[/] [qaz_libs/] [trunk/] [axi4_lib/] [sim/] [src/] [legacy/] [axi4_bfm/] [axi4_master_bfm_if.sv] - Blame information for rev 50

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
interface
  axi4_master_bfm_if
  #(
    A = 32, // address bus width
    N = 8,  // data bus width in bytes
    I = 1   // ID width
  )
  (
    axi4_if axi4_s,
    input   aresetn,
    input   aclk
  );
 
  logic [(A-1):0]    araddr;
  logic [1:0]        arburst;
  logic [3:0]        arcache;
  logic [(I-1):0]    arid;
  logic [7:0]        arlen;
  logic              arlock;
  logic [2:0]        arprot;
  logic [3:0]        arqos;
  logic              arready;
  logic [3:0]        arregion;
  logic [2:0]        arsize;
  logic              arvalid;
  logic [(A-1):0]    awaddr;
  logic [1:0]        awburst;
  logic [3:0]        awcache;
  logic [(I-1):0]    awid;
  logic [7:0]        awlen;
  logic              awlock;
  logic [2:0]        awprot;
  logic [3:0]        awqos;
  logic              awready;
  logic [3:0]        awregion;
  logic [2:0]        awsize;
  logic              awvalid;
  logic [(I-1):0]    bid;
  logic              bready;
  logic [1:0]        bresp;
  logic              bvalid;
  logic [(8*N)-1:0]  rdata;
  logic [(I-1):0]    rid;
  logic              rlast;
  logic              rready;
  logic [1:0]        rresp;
  logic              rvalid;
  logic [(8*N)-1:0]  wdata;
  logic [(I-1):0]    wid;
  logic              wlast;
  logic              wready;
  logic [N-1:0]      wstrb;
  logic              wvalid;
 
 
  // --------------------------------------------------------------------
  //
  default clocking cb @(posedge aclk);
    output  arid;
    output  araddr;
    output  arburst;
    output  arcache;
    output  awid;
    output  arlen;
    output  arlock;
    output  arprot;
    output  arqos;
    input   arready;
    output  arregion;
    output  arsize;
    output  arvalid;
    output  awaddr;
    output  awburst;
    output  awcache;
    output  awlen;
    output  awlock;
    output  awprot;
    output  awqos;
    input   awready;
    output  awregion;
    output  awsize;
    output  awvalid;
    output  bready;
    input   bid;
    input   bresp;
    input   bvalid;
    input   rdata;
    input   rid;
    input   rlast;
    output  rready;
    input   rresp;
    input   rvalid;
    output  wdata;
    output  wlast;
    input   wready;
    output  wstrb;
    output  wvalid;
    input   aresetn;
    input   aclk;
  endclocking
 
 
  // --------------------------------------------------------------------
  //
  assign axi4_s.arid     = arid;
  assign axi4_s.araddr   = araddr;
  assign axi4_s.arburst  = arburst;
  assign axi4_s.arcache  = arcache;
  assign axi4_s.awid     = awid;
  assign axi4_s.arlen    = arlen;
  assign axi4_s.arlock   = arlock;
  assign axi4_s.arprot   = arprot;
  assign axi4_s.arqos    = arqos;
  assign arready         = axi4_s.arready;
  assign axi4_s.arregion = arregion;
  assign axi4_s.arsize   = arsize;
  assign axi4_s.arvalid  = arvalid;
  assign axi4_s.awaddr   = awaddr;
  assign axi4_s.awburst  = awburst;
  assign axi4_s.awcache  = awcache;
  assign axi4_s.awlen    = awlen;
  assign axi4_s.awlock   = awlock;
  assign axi4_s.awprot   = awprot;
  assign axi4_s.awqos    = awqos;
  assign awready         = axi4_s.awready;
  assign axi4_s.awregion = awregion;
  assign axi4_s.awsize   = awsize;
  assign axi4_s.awvalid  = awvalid;
  assign axi4_s.bready   = bready;
  assign bid             = axi4_s.bid;
  assign bresp           = axi4_s.bresp;
  assign bvalid          = axi4_s.bvalid;
  assign rdata           = axi4_s.rdata;
  assign rid             = axi4_s.rid;
  assign rlast           = axi4_s.rlast;
  assign axi4_s.rready   = rready;
  assign rresp           = axi4_s.rresp;
  assign rvalid          = axi4_s.rvalid;
  assign axi4_s.wdata    = wdata;
  assign axi4_s.wlast    = wlast;
  assign wready          = axi4_s.wready;
  assign axi4_s.wstrb    = wstrb;
  assign axi4_s.wvalid   = wvalid;
 
 
  // --------------------------------------------------------------------
  //
  function void
    ar_default;
 
    cb.araddr   <= 'bx;
    cb.arburst  <= 'bx;
    cb.arcache  <= 'bx;
    cb.arid     <= 'bx;
    cb.arlen    <= 'bx;
    cb.arlock   <= 'bx;
    cb.arprot   <= 'bx;
    cb.arqos    <= 'bx;
    cb.arregion <= 'bx;
    cb.arsize   <= 'bx;
    cb.arvalid  <= 0;
 
  endfunction: ar_default
 
 
  // --------------------------------------------------------------------
  //
  function void
    aw_default;
 
    cb.awaddr   <= 'bx;
    cb.awburst  <= 'bx;
    cb.awcache  <= 'bx;
    cb.awid     <= 'bx;
    cb.awlen    <= 'bx;
    cb.awlock   <= 'bx;
    cb.awprot   <= 'bx;
    cb.awqos    <= 'bx;
    cb.awregion <= 'bx;
    cb.awsize   <= 'bx;
    cb.awvalid  <= 0;
 
  endfunction: aw_default
 
 
  // --------------------------------------------------------------------
  //
  function void
    r_default;
 
    cb.rready <= 0;
 
  endfunction: r_default
 
 
  // --------------------------------------------------------------------
  //
  function void
    w_default;
 
    cb.wdata    <= 'bx;
    cb.wlast    <= 'bx;
    cb.wstrb    <= {N{1'b1}};
    cb.wvalid   <= 0;
 
  endfunction: w_default
 
 
  // --------------------------------------------------------------------
  //
  function void
    b_default;
 
    cb.bready   <= 0;
 
  endfunction: b_default
 
 
  // --------------------------------------------------------------------
  //
  function void
    init;
 
    ar_default();
    r_default();
    aw_default();
    w_default();
    b_default();
 
  endfunction: init
 
 
  // --------------------------------------------------------------------
  //
  task
    zero_cycle_delay;
 
    ##0;
 
  endtask: zero_cycle_delay
 
 
  // --------------------------------------------------------------------
  //
  import tb_bfm_pkg::*;
  import axi4_transaction_pkg::*;
 
 
  // --------------------------------------------------------------------
  //
  class ar_master_transaction_class #(A = 32, N = 8, I = 1)
    extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
    // --------------------------------------------------------------------
    //
    task automatic
      transaction
      (
        ref T tr_h
      );
 
      ->this.start;
 
      ##(tr_h.delay_h.next());
 
      cb.araddr   <= tr_h.addr;
      cb.arid     <= tr_h.id;
      cb.arlen    <= tr_h.len;
      cb.arsize   <= tr_h.size;
 
      cb.arburst  <= tr_h.burst;
      cb.arcache  <= tr_h.cache;
      cb.arlock   <= tr_h.lock;
      cb.arprot   <= tr_h.prot;
      cb.arqos    <= tr_h.qos;
      cb.arregion <= tr_h.region;
      cb.arvalid  <= 1;
 
      $display("^^^ %16.t | %m | master AR transaction @ 0x%08x |", $time, tr_h.addr);
 
      ##1;
      wait(cb.arready);
 
      ##0;
      ar_default();
 
      ->this.done;
 
    endtask: transaction
 
 
  // --------------------------------------------------------------------
  //
  endclass: ar_master_transaction_class
 
 
  // --------------------------------------------------------------------
  //
  class r_master_transaction_class #(A = 32, N = 8, I = 1)
    extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
    // --------------------------------------------------------------------
    //
    task automatic
      transaction
      (
        ref T tr_h
      );
 
      ->this.start;
 
      tr_h.data_h = new(tr_h.len);
 
      foreach(tr_h.payload_h.w[i])
      begin
        ##(tr_h.delay_h.next());
        cb.rready <= 1;
        ##1;
 
        wait(cb.rvalid);
        ##0;
 
        tr_h.data_h.w[i] = cb.rdata;
 
        $display("^^^ %16.t | %m | master R transaction | %d | 0x%016x |", $time, i, tr_h.data_h.w[i]);
        r_default();
      end
 
      ->this.done;
 
    endtask: transaction
 
 
  // --------------------------------------------------------------------
  //
  endclass: r_master_transaction_class
 
 
  // --------------------------------------------------------------------
  //
  class aw_master_transaction_class #(A = 32, N = 8, I = 1)
    extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
    // --------------------------------------------------------------------
    //
    task automatic
      transaction
      (
        ref T tr_h
      );
 
      ->this.start;
 
      ##(tr_h.delay_h.next());
 
      cb.awaddr   <= tr_h.addr;
      cb.awid     <= tr_h.id;
      cb.awlen    <= tr_h.len;
      cb.awsize   <= tr_h.size;
 
      cb.awburst  <= tr_h.burst;
      cb.awcache  <= tr_h.cache;
      cb.awlock   <= tr_h.lock;
      cb.awprot   <= tr_h.prot;
      cb.awqos    <= tr_h.qos;
      cb.awregion <= tr_h.region;
      cb.awvalid  <= 1;
 
      $display("^^^ %16.t | %m | master AW transaction @ 0x%08x |", $time, tr_h.addr);
 
      ##1;
      wait(cb.awready);
 
      ##0;
      aw_default();
 
      ->this.done;
 
    endtask: transaction
 
 
  // --------------------------------------------------------------------
  //
  endclass: aw_master_transaction_class
 
 
  // --------------------------------------------------------------------
  //
  class w_master_transaction_class #(A = 32, N = 8, I = 1)
    extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
    // --------------------------------------------------------------------
    //
    task automatic
      transaction
      (
        ref T tr_h
      );
 
      ->this.start;
 
      foreach(tr_h.payload_h.w[i])
      begin
        ##(tr_h.delay_h.next());
 
        cb.wdata  <= tr_h.payload_h.w[i];
        // cb.wstrb  <= tr_h.strb;    // need to fix
 
        if(i < tr_h.payload_h.w.size - 1)
          cb.wlast   <= 0;
        else
          cb.wlast   <= 1;
 
        cb.wvalid <= 1;
 
        ##1;
        wait(cb.wready);
 
        ##0;
        $display("^^^ %16.t | %m | master W transaction | %d | 0x%016x |", $time, i, tr_h.payload_h.w[i]);
        w_default();
      end
 
      ->this.done;
 
    endtask: transaction
 
 
  // --------------------------------------------------------------------
  //
  endclass: w_master_transaction_class
 
 
  // --------------------------------------------------------------------
  //
  class b_master_transaction_class #(A = 32, N = 8, I = 1)
    extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
 
    // --------------------------------------------------------------------
    //
    task automatic
      transaction
      (
        ref T tr_h
      );
 
      ->this.start;
 
      ##(tr_h.delay_h.next());
      cb.bready <= 1;
      ##1;
 
      wait(cb.bvalid);
      ##0;
 
      $display("^^^ %16.t | %m | master B transaction | 0x%x |", $time, cb.bresp);
      b_default();
 
      ->this.done;
 
    endtask: transaction
 
 
  // --------------------------------------------------------------------
  //
  endclass: b_master_transaction_class
 
 
  // --------------------------------------------------------------------
  //
  ar_master_transaction_class #(.A(A), .N(N), .I(I))  ar_h;
  r_master_transaction_class  #(.A(A), .N(N), .I(I))  r_h;
  aw_master_transaction_class #(.A(A), .N(N), .I(I))  aw_h;
  w_master_transaction_class #(.A(A), .N(N), .I(I))   w_h;
  b_master_transaction_class  #(.A(A), .N(N), .I(I))  b_h;
 
  initial
  begin
    init();
    ar_h = new;
    ar_h.init();
    r_h = new;
    r_h.init();
    aw_h = new;
    aw_h.init();
    w_h = new;
    w_h.init();
    b_h = new;
    b_h.init();
  end
 
 
// --------------------------------------------------------------------
//
 
endinterface
 
 

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Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [axi4_lib/] [sim/] [src/] [legacy/] [axi4_bfm/] [axi4_master_bfm_if.sv] - Blame information for rev 50

Line No.	Rev	Author	Line
1	45	qaztronic	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Copyright (C) 2015 Authors and OPENCORES.ORG ////`
4			`//// ////`
5			`//// This source file may be used and distributed without ////`
6			`//// restriction provided that this copyright statement is not ////`
7			`//// removed from the file and that any derivative work contains ////`
8			`//// the original copyright notice and the associated disclaimer. ////`
9			`//// ////`
10			`//// This source file is free software; you can redistribute it ////`
11			`//// and/or modify it under the terms of the GNU Lesser General ////`
12			`//// Public License as published by the Free Software Foundation; ////`
13			`//// either version 2.1 of the License, or (at your option) any ////`
14			`//// later version. ////`
15			`//// ////`
16			`//// This source is distributed in the hope that it will be ////`
17			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
18			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
19			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
20			`//// details. ////`
21			`//// ////`
22			`//// You should have received a copy of the GNU Lesser General ////`
23			`//// Public License along with this source; if not, download it ////`
24			`//// from http://www.opencores.org/lgpl.shtml ////`
25			`//// ////`
26			`//////////////////////////////////////////////////////////////////////`
27
28
29			`interface`
30			`axi4_master_bfm_if`
31			`#(`
32			`A = 32, // address bus width`
33			`N = 8, // data bus width in bytes`
34			`I = 1 // ID width`
35			`)`
36			`(`
37			`axi4_if axi4_s,`
38			`input aresetn,`
39			`input aclk`
40			`);`
41
42			`logic [(A-1):0] araddr;`
43			`logic [1:0] arburst;`
44			`logic [3:0] arcache;`
45			`logic [(I-1):0] arid;`
46			`logic [7:0] arlen;`
47			`logic arlock;`
48			`logic [2:0] arprot;`
49			`logic [3:0] arqos;`
50			`logic arready;`
51			`logic [3:0] arregion;`
52			`logic [2:0] arsize;`
53			`logic arvalid;`
54			`logic [(A-1):0] awaddr;`
55			`logic [1:0] awburst;`
56			`logic [3:0] awcache;`
57			`logic [(I-1):0] awid;`
58			`logic [7:0] awlen;`
59			`logic awlock;`
60			`logic [2:0] awprot;`
61			`logic [3:0] awqos;`
62			`logic awready;`
63			`logic [3:0] awregion;`
64			`logic [2:0] awsize;`
65			`logic awvalid;`
66			`logic [(I-1):0] bid;`
67			`logic bready;`
68			`logic [1:0] bresp;`
69			`logic bvalid;`
70			`logic [(8*N)-1:0] rdata;`
71			`logic [(I-1):0] rid;`
72			`logic rlast;`
73			`logic rready;`
74			`logic [1:0] rresp;`
75			`logic rvalid;`
76			`logic [(8*N)-1:0] wdata;`
77			`logic [(I-1):0] wid;`
78			`logic wlast;`
79			`logic wready;`
80			`logic [N-1:0] wstrb;`
81			`logic wvalid;`
82
83
84			`// --------------------------------------------------------------------`
85			`//`
86			`default clocking cb @(posedge aclk);`
87			`output arid;`
88			`output araddr;`
89			`output arburst;`
90			`output arcache;`
91			`output awid;`
92			`output arlen;`
93			`output arlock;`
94			`output arprot;`
95			`output arqos;`
96			`input arready;`
97			`output arregion;`
98			`output arsize;`
99			`output arvalid;`
100			`output awaddr;`
101			`output awburst;`
102			`output awcache;`
103			`output awlen;`
104			`output awlock;`
105			`output awprot;`
106			`output awqos;`
107			`input awready;`
108			`output awregion;`
109			`output awsize;`
110			`output awvalid;`
111			`output bready;`
112			`input bid;`
113			`input bresp;`
114			`input bvalid;`
115			`input rdata;`
116			`input rid;`
117			`input rlast;`
118			`output rready;`
119			`input rresp;`
120			`input rvalid;`
121			`output wdata;`
122			`output wlast;`
123			`input wready;`
124			`output wstrb;`
125			`output wvalid;`
126			`input aresetn;`
127			`input aclk;`
128			`endclocking`
129
130
131			`// --------------------------------------------------------------------`
132			`//`
133			`assign axi4_s.arid = arid;`
134			`assign axi4_s.araddr = araddr;`
135			`assign axi4_s.arburst = arburst;`
136			`assign axi4_s.arcache = arcache;`
137			`assign axi4_s.awid = awid;`
138			`assign axi4_s.arlen = arlen;`
139			`assign axi4_s.arlock = arlock;`
140			`assign axi4_s.arprot = arprot;`
141			`assign axi4_s.arqos = arqos;`
142			`assign arready = axi4_s.arready;`
143			`assign axi4_s.arregion = arregion;`
144			`assign axi4_s.arsize = arsize;`
145			`assign axi4_s.arvalid = arvalid;`
146			`assign axi4_s.awaddr = awaddr;`
147			`assign axi4_s.awburst = awburst;`
148			`assign axi4_s.awcache = awcache;`
149			`assign axi4_s.awlen = awlen;`
150			`assign axi4_s.awlock = awlock;`
151			`assign axi4_s.awprot = awprot;`
152			`assign axi4_s.awqos = awqos;`
153			`assign awready = axi4_s.awready;`
154			`assign axi4_s.awregion = awregion;`
155			`assign axi4_s.awsize = awsize;`
156			`assign axi4_s.awvalid = awvalid;`
157			`assign axi4_s.bready = bready;`
158			`assign bid = axi4_s.bid;`
159			`assign bresp = axi4_s.bresp;`
160			`assign bvalid = axi4_s.bvalid;`
161			`assign rdata = axi4_s.rdata;`
162			`assign rid = axi4_s.rid;`
163			`assign rlast = axi4_s.rlast;`
164			`assign axi4_s.rready = rready;`
165			`assign rresp = axi4_s.rresp;`
166			`assign rvalid = axi4_s.rvalid;`
167			`assign axi4_s.wdata = wdata;`
168			`assign axi4_s.wlast = wlast;`
169			`assign wready = axi4_s.wready;`
170			`assign axi4_s.wstrb = wstrb;`
171			`assign axi4_s.wvalid = wvalid;`
172
173
174			`// --------------------------------------------------------------------`
175			`//`
176			`function void`
177			`ar_default;`
178
179			`cb.araddr <= 'bx;`
180			`cb.arburst <= 'bx;`
181			`cb.arcache <= 'bx;`
182			`cb.arid <= 'bx;`
183			`cb.arlen <= 'bx;`
184			`cb.arlock <= 'bx;`
185			`cb.arprot <= 'bx;`
186			`cb.arqos <= 'bx;`
187			`cb.arregion <= 'bx;`
188			`cb.arsize <= 'bx;`
189			`cb.arvalid <= 0;`
190
191			`endfunction: ar_default`
192
193
194			`// --------------------------------------------------------------------`
195			`//`
196			`function void`
197			`aw_default;`
198
199			`cb.awaddr <= 'bx;`
200			`cb.awburst <= 'bx;`
201			`cb.awcache <= 'bx;`
202			`cb.awid <= 'bx;`
203			`cb.awlen <= 'bx;`
204			`cb.awlock <= 'bx;`
205			`cb.awprot <= 'bx;`
206			`cb.awqos <= 'bx;`
207			`cb.awregion <= 'bx;`
208			`cb.awsize <= 'bx;`
209			`cb.awvalid <= 0;`
210
211			`endfunction: aw_default`
212
213
214			`// --------------------------------------------------------------------`
215			`//`
216			`function void`
217			`r_default;`
218
219			`cb.rready <= 0;`
220
221			`endfunction: r_default`
222
223
224			`// --------------------------------------------------------------------`
225			`//`
226			`function void`
227			`w_default;`
228
229			`cb.wdata <= 'bx;`
230			`cb.wlast <= 'bx;`
231			`cb.wstrb <= {N{1'b1}};`
232			`cb.wvalid <= 0;`
233
234			`endfunction: w_default`
235
236
237			`// --------------------------------------------------------------------`
238			`//`
239			`function void`
240			`b_default;`
241
242			`cb.bready <= 0;`
243
244			`endfunction: b_default`
245
246
247			`// --------------------------------------------------------------------`
248			`//`
249			`function void`
250			`init;`
251
252			`ar_default();`
253			`r_default();`
254			`aw_default();`
255			`w_default();`
256			`b_default();`
257
258			`endfunction: init`
259
260
261			`// --------------------------------------------------------------------`
262			`//`
263			`task`
264			`zero_cycle_delay;`
265
266			`##0;`
267
268			`endtask: zero_cycle_delay`
269
270
271			`// --------------------------------------------------------------------`
272			`//`
273			`import tb_bfm_pkg::*;`
274			`import axi4_transaction_pkg::*;`
275
276
277			`// --------------------------------------------------------------------`
278			`//`
279			`class ar_master_transaction_class #(A = 32, N = 8, I = 1)`
280			`extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));`
281
282			`// --------------------------------------------------------------------`
283			`//`
284			`task automatic`
285			`transaction`
286			`(`
287			`ref T tr_h`
288			`);`
289
290			`->this.start;`
291
292			`##(tr_h.delay_h.next());`
293
294			`cb.araddr <= tr_h.addr;`
295			`cb.arid <= tr_h.id;`
296			`cb.arlen <= tr_h.len;`
297			`cb.arsize <= tr_h.size;`
298
299			`cb.arburst <= tr_h.burst;`
300			`cb.arcache <= tr_h.cache;`
301			`cb.arlock <= tr_h.lock;`
302			`cb.arprot <= tr_h.prot;`
303			`cb.arqos <= tr_h.qos;`
304			`cb.arregion <= tr_h.region;`
305			`cb.arvalid <= 1;`
306
307			`$display("^^^ %16.t \| %m \| master AR transaction @ 0x%08x \|", $time, tr_h.addr);`
308
309			`##1;`
310			`wait(cb.arready);`
311
312			`##0;`
313			`ar_default();`
314
315			`->this.done;`
316
317			`endtask: transaction`
318
319
320			`// --------------------------------------------------------------------`
321			`//`
322			`endclass: ar_master_transaction_class`
323
324
325			`// --------------------------------------------------------------------`
326			`//`
327			`class r_master_transaction_class #(A = 32, N = 8, I = 1)`
328			`extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));`
329
330			`// --------------------------------------------------------------------`
331			`//`
332			`task automatic`
333			`transaction`
334			`(`
335			`ref T tr_h`
336			`);`
337
338			`->this.start;`
339
340			`tr_h.data_h = new(tr_h.len);`
341
342			`foreach(tr_h.payload_h.w[i])`
343			`begin`
344			`##(tr_h.delay_h.next());`
345			`cb.rready <= 1;`
346			`##1;`
347
348			`wait(cb.rvalid);`
349			`##0;`
350
351			`tr_h.data_h.w[i] = cb.rdata;`
352
353			`$display("^^^ %16.t \| %m \| master R transaction \| %d \| 0x%016x \|", $time, i, tr_h.data_h.w[i]);`
354			`r_default();`
355			`end`
356
357			`->this.done;`
358
359			`endtask: transaction`
360
361
362			`// --------------------------------------------------------------------`
363			`//`
364			`endclass: r_master_transaction_class`
365
366
367			`// --------------------------------------------------------------------`
368			`//`
369			`class aw_master_transaction_class #(A = 32, N = 8, I = 1)`
370			`extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));`
371
372			`// --------------------------------------------------------------------`
373			`//`
374			`task automatic`
375			`transaction`
376			`(`
377			`ref T tr_h`
378			`);`
379
380			`->this.start;`
381
382			`##(tr_h.delay_h.next());`
383
384			`cb.awaddr <= tr_h.addr;`
385			`cb.awid <= tr_h.id;`
386			`cb.awlen <= tr_h.len;`
387			`cb.awsize <= tr_h.size;`
388
389			`cb.awburst <= tr_h.burst;`
390			`cb.awcache <= tr_h.cache;`
391			`cb.awlock <= tr_h.lock;`
392			`cb.awprot <= tr_h.prot;`
393			`cb.awqos <= tr_h.qos;`
394			`cb.awregion <= tr_h.region;`
395			`cb.awvalid <= 1;`
396
397			`$display("^^^ %16.t \| %m \| master AW transaction @ 0x%08x \|", $time, tr_h.addr);`
398
399			`##1;`
400			`wait(cb.awready);`
401
402			`##0;`
403			`aw_default();`
404
405			`->this.done;`
406
407			`endtask: transaction`
408
409
410			`// --------------------------------------------------------------------`
411			`//`
412			`endclass: aw_master_transaction_class`
413
414
415			`// --------------------------------------------------------------------`
416			`//`
417			`class w_master_transaction_class #(A = 32, N = 8, I = 1)`
418			`extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));`
419
420			`// --------------------------------------------------------------------`
421			`//`
422			`task automatic`
423			`transaction`
424			`(`
425			`ref T tr_h`
426			`);`
427
428			`->this.start;`
429
430			`foreach(tr_h.payload_h.w[i])`
431			`begin`
432			`##(tr_h.delay_h.next());`
433
434			`cb.wdata <= tr_h.payload_h.w[i];`
435			`// cb.wstrb <= tr_h.strb; // need to fix`
436
437			`if(i < tr_h.payload_h.w.size - 1)`
438			`cb.wlast <= 0;`
439			`else`
440			`cb.wlast <= 1;`
441
442			`cb.wvalid <= 1;`
443
444			`##1;`
445			`wait(cb.wready);`
446
447			`##0;`
448			`$display("^^^ %16.t \| %m \| master W transaction \| %d \| 0x%016x \|", $time, i, tr_h.payload_h.w[i]);`
449			`w_default();`
450			`end`
451
452			`->this.done;`
453
454			`endtask: transaction`
455
456
457			`// --------------------------------------------------------------------`
458			`//`
459			`endclass: w_master_transaction_class`
460
461
462			`// --------------------------------------------------------------------`
463			`//`
464			`class b_master_transaction_class #(A = 32, N = 8, I = 1)`
465			`extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));`
466
467			`// --------------------------------------------------------------------`
468			`//`
469			`task automatic`
470			`transaction`
471			`(`
472			`ref T tr_h`
473			`);`
474
475			`->this.start;`
476
477			`##(tr_h.delay_h.next());`
478			`cb.bready <= 1;`
479			`##1;`
480
481			`wait(cb.bvalid);`
482			`##0;`
483
484			`$display("^^^ %16.t \| %m \| master B transaction \| 0x%x \|", $time, cb.bresp);`
485			`b_default();`
486
487			`->this.done;`
488
489			`endtask: transaction`
490
491
492			`// --------------------------------------------------------------------`
493			`//`
494			`endclass: b_master_transaction_class`
495
496
497			`// --------------------------------------------------------------------`
498			`//`
499			`ar_master_transaction_class #(.A(A), .N(N), .I(I)) ar_h;`
500			`r_master_transaction_class #(.A(A), .N(N), .I(I)) r_h;`
501			`aw_master_transaction_class #(.A(A), .N(N), .I(I)) aw_h;`
502			`w_master_transaction_class #(.A(A), .N(N), .I(I)) w_h;`
503			`b_master_transaction_class #(.A(A), .N(N), .I(I)) b_h;`
504
505			`initial`
506			`begin`
507			`init();`
508			`ar_h = new;`
509			`ar_h.init();`
510			`r_h = new;`
511			`r_h.init();`
512			`aw_h = new;`
513			`aw_h.init();`
514			`w_h = new;`
515			`w_h.init();`
516			`b_h = new;`
517			`b_h.init();`
518			`end`
519
520
521			`// --------------------------------------------------------------------`
522			`//`
523
524			`endinterface`
525
526