OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [axi4_lib/] [sim/] [src/] [legacy/] [axi4_bfm/] [axi4_simple_agent_pkg.sv] - Blame information for rev 50

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 45 qaztronic
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
4
////                                                              ////
5
//// This source file may be used and distributed without         ////
6
//// restriction provided that this copyright statement is not    ////
7
//// removed from the file and that any derivative work contains  ////
8
//// the original copyright notice and the associated disclaimer. ////
9
////                                                              ////
10
//// This source file is free software; you can redistribute it   ////
11
//// and/or modify it under the terms of the GNU Lesser General   ////
12
//// Public License as published by the Free Software Foundation; ////
13
//// either version 2.1 of the License, or (at your option) any   ////
14
//// later version.                                               ////
15
////                                                              ////
16
//// This source is distributed in the hope that it will be       ////
17
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
18
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
19
//// PURPOSE.  See the GNU Lesser General Public License for more ////
20
//// details.                                                     ////
21
////                                                              ////
22
//// You should have received a copy of the GNU Lesser General    ////
23
//// Public License along with this source; if not, download it   ////
24
//// from http://www.opencores.org/lgpl.shtml                     ////
25
////                                                              ////
26
//////////////////////////////////////////////////////////////////////
27
 
28
 
29
package axi4_simple_agent_pkg;
30
 
31
  // --------------------------------------------------------------------
32
  //
33
  import axi4_transaction_pkg::*;
34
 
35
 
36
  // --------------------------------------------------------------------
37
  //
38
  class axi4_simple_agent_class #(A = 32, N = 8, I = 1);
39
 
40
    axi4_transaction_class tr_h;
41
    virtual axi4_master_bfm_if  #(.A(A), .N(N), .I(I)) axi4_m;
42
    virtual axi4_slave_bfm_if   #(.A(A), .N(N), .I(I)) axi4_s;
43
 
44
 
45
    //--------------------------------------------------------------------
46
    function new
47
      (
48
        virtual axi4_master_bfm_if  #(.A(A), .N(N), .I(I)) axi4_m,
49
        virtual axi4_slave_bfm_if   #(.A(A), .N(N), .I(I)) axi4_s
50
      );
51
 
52
      this.axi4_m = axi4_m;
53
      this.axi4_s = axi4_s;
54
 
55
    endfunction: new
56
 
57
 
58
    // --------------------------------------------------------------------
59
    //
60
    task
61
      basic_read
62
      (
63
        input   logic [(A-1):0]   araddr,
64
        input   logic [7:0]       arlen,
65
        output  logic [(8*N)-1:0] data[],
66
        output  logic [1:0]       rresp
67
      );
68
 
69
      this.tr_h = new;
70
      this.tr_h.basic_read(araddr, arlen);
71
 
72
      axi4_m.ar_h.put(tr_h);
73
      axi4_s.ar_h.put(tr_h);
74
      axi4_m.r_h.put(tr_h);
75
 
76
      @(axi4_m.r_h.done);
77
      data = tr_h.data_h.w;
78
      rresp = tr_h.resp;
79
 
80
    endtask: basic_read
81
 
82
 
83
    // --------------------------------------------------------------------
84
    //
85
    task
86
      basic_write
87
      (
88
        input   logic [(A-1):0]   awaddr,
89
        input   logic [7:0]       awlen,
90
        input   logic [(8*N)-1:0] data[],
91
        output  logic [1:0]       bresp
92
      );
93
 
94
      this.tr_h = new;
95
      this.tr_h.basic_write(awaddr, awlen);
96
 
97
      foreach(this.tr_h.payload_h.w[i])
98
        this.tr_h.payload_h.w[i] = data[i];
99
 
100
      axi4_m.aw_h.put(tr_h);
101
      axi4_s.aw_h.put(tr_h);
102
      axi4_m.w_h.put(tr_h);
103
      axi4_s.w_h.put(tr_h);
104
      axi4_m.b_h.put(tr_h);
105
 
106
      @(axi4_s.b_h.done);
107
      bresp = tr_h.resp;
108
 
109
    endtask: basic_write
110
 
111
 
112
    // --------------------------------------------------------------------
113
    //
114
    task
115
      basic_random_write
116
      (
117
        input   logic [(A-1):0]   awaddr,
118
        input   logic [7:0]       awlen,
119
        output  logic [1:0]       bresp
120
      );
121
 
122
      this.tr_h = new;
123
      this.tr_h.basic_write(awaddr, awlen);
124
 
125
      axi4_m.aw_h.put(tr_h);
126
      axi4_s.aw_h.put(tr_h);
127
      axi4_m.w_h.put(tr_h);
128
      axi4_s.w_h.put(tr_h);
129
      axi4_m.b_h.put(tr_h);
130
 
131
      @(axi4_s.b_h.done);
132
      bresp = tr_h.resp;
133
 
134
    endtask: basic_random_write
135
 
136
 
137
    // --------------------------------------------------------------------
138
    //
139
    function void
140
      init;
141
 
142
    endfunction: init
143
 
144
 
145
  // --------------------------------------------------------------------
146
  //
147
  endclass: axi4_simple_agent_class
148
 
149
 
150
// --------------------------------------------------------------------
151
//
152
endpackage: axi4_simple_agent_pkg
153
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.