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[/] [qaz_libs/] [trunk/] [axi4_lib/] [src/] [axi4_if.sv] - Blame information for rev 23

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1 23 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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interface
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  axi4_if
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  #(
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    DATA_WIDTH = 64
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  )
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  (
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    input                   aresetn,
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    input                   aclk
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  );
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    wire                    arready;
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    wire                    arregion;
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    wire                    awready;
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    wire                    awregion;
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    wire                    bvalid;
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    wire                    rlast;
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    wire                    rvalid;
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    wire                    wready;
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    wire [1:0]              bresp;
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    wire [1:0]              rresp;
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    wire [5:0]              bid;
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    wire [5:0]              rid;
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    wire [DATA_WIDTH-1:0]   rdata;
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    wire [7:0]              rcount;
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    wire [7:0]              wcount;
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    wire [2:0]              racount;
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    wire [5:0]              wacount;
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    wire                    arvalid;
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    wire                    awvalid;
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    wire                    bready;
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    wire                    rready;
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    wire                    wlast;
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    wire                    wvalid;
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    wire [1:0]              arburst;
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    wire [1:0]              arlock;
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    wire [2:0]              arsize;
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    wire [1:0]              awburst;
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    wire [1:0]              awlock;
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    wire [2:0]              awsize;
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    wire [2:0]              arprot;
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    wire [2:0]              awprot;
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    wire [31:0]             araddr;
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    wire [31:0]             awaddr;
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    wire [3:0]              arcache;
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    wire [7:0]              arlen;
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    wire [3:0]              arqos;
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    wire [3:0]              awcache;
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    wire [3:0]              awlen;
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    wire [3:0]              awqos;
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    wire [5:0]              arid;
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    wire [5:0]              awid;
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    wire [5:0]              wid;
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    wire [DATA_WIDTH-1:0]   wdata;
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    wire [DATA_WIDTH/8-1:0] wstrb;
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  // --------------------------------------------------------------------
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  //
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  modport
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    master
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    (
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      output  arid,
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      output  araddr,
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      output  arburst,
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      output  arcache,
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      output  arlen,
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      output  arlock,
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      output  arprot,
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      output  arqos,
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      input   arready,
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      output  arregion,
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      output  arsize,
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      output  arvalid,
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      output  awaddr,
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      output  awburst,
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      output  awcache,
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      output  awlen,
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      output  awlock,
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      output  awprot,
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      output  awqos,
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      input   awready,
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      output  awregion,
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      output  awsize,
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      output  awvalid,
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      output  bready,
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      input   bresp,
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      input   bvalid,
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      input   rdata,
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      input   rlast,
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      output  rready,
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      input   rresp,
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      input   rvalid,
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      output  wdata,
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      output  wlast,
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      input   wready,
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      output  wstrb,
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      output  wvalid,
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      input   aresetn,
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      input   aclk
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    );
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  modport
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    slave
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    (
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      input   arid,
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      input   araddr,
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      input   arburst,
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      input   arcache,
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      input   arlen,
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      input   arlock,
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      input   arprot,
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      input   arqos,
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      output  arready,
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      input   arregion,
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      input   arsize,
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      input   arvalid,
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      input   awaddr,
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      input   awburst,
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      input   awcache,
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      input   awlen,
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      input   awlock,
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      input   awprot,
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      input   awqos,
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      output  awready,
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      input   awregion,
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      input   awsize,
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      input   awvalid,
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      input   bready,
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      output  bresp,
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      output  bvalid,
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      output  rdata,
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      output  rlast,
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      input   rready,
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      output  rresp,
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      output  rvalid,
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      input   wdata,
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      input   wlast,
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      output  wready,
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      input   wstrb,
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      input   wvalid,
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      input   aresetn,
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      input   aclk
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    );
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endinterface: axi4_if
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