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[/] [qaz_libs/] [trunk/] [axi4_lib/] [src/] [axi4_m_to_read_fifos.sv] - Blame information for rev 31

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1 31 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  axi4_m_to_read_fifos
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  #(
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    A     = 32, // address bus width
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    N     = 8,  // data bus width in bytes
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    I     = 1,  // ID width
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    R_D   = 32,
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    AR_D  = 2,
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    WATERMARK = 0,
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    USE_ADVANCED_PROTOCOL = 0
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  )
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  (
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    axi4_if     axi4_m,
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    axi4_if     axi4_read_fifo,
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    output      ar_wr_full,
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    input       ar_wr_en,
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    output      r_rd_empty,
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    input       r_rd_en,
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    output      r_topped_off,
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    output      r_watermark,
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    input       aclk,
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    input       aresetn
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  );
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  // --------------------------------------------------------------------
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  //
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  localparam UB = $clog2(R_D);
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  // --------------------------------------------------------------------
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  //
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  localparam R_W =
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    8*N + //  logic [(8*N)-1:0]  rdata;
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    I +   //  logic [(I-1):0]    rid;
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    1 +   //  logic              rlast;
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    2;    //  logic [1:0]        rresp;
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  localparam AX_BASIC_W =
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    A +  // logic [(A-1):0]    axaddr;
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    2 +  // logic [1:0]        axburst;
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    I +  // logic [(I-1):0]    axid;
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    8 +  // logic [7:0]        axlen;
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    3;   // logic [2:0]        axsize;
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  localparam AX_ADVANCED_W =
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    4 +   // logic [3:0]        axcache;
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    1 +   // logic              axlock;
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    3 +   // logic [2:0]        axprot;
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    4 +   // logic [3:0]        axqos;
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    4;    // logic [3:0]        axregion;
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  localparam AR_W = USE_ADVANCED_PROTOCOL ? AX_BASIC_W + AX_ADVANCED_W : AX_BASIC_W;
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  // --------------------------------------------------------------------
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  //
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  wire [AR_W-1:0] ar_rd_data;
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  wire [AR_W-1:0] ar_wr_data;
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  generate
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    begin: ar_data_gen
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      if(USE_ADVANCED_PROTOCOL)
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      begin
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        assign ar_wr_data =
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          {
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            axi4_read_fifo.araddr,
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            axi4_read_fifo.arburst,
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            axi4_read_fifo.arid,
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            axi4_read_fifo.arlen,
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            axi4_read_fifo.arsize,
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            axi4_read_fifo.arcache,
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            axi4_read_fifo.arlock,
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            axi4_read_fifo.arprot,
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            axi4_read_fifo.arqos,
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            axi4_read_fifo.arregion
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          };
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        assign
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          {
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            axi4_m.araddr,
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            axi4_m.arburst,
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            axi4_m.arid,
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            axi4_m.arlen,
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            axi4_m.arsize,
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            axi4_m.arcache,
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            axi4_m.arlock,
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            axi4_m.arprot,
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            axi4_m.arqos,
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            axi4_m.arregion
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          } = ar_rd_data;
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      end
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      else
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      begin
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        assign ar_wr_data =
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          {
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            axi4_read_fifo.araddr,
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            axi4_read_fifo.arburst,
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            axi4_read_fifo.arid,
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            axi4_read_fifo.arlen,
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            axi4_read_fifo.arsize
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          };
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        assign axi4_read_fifo.arcache  = 0;
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        assign axi4_read_fifo.arlock   = 0;
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        assign axi4_read_fifo.arprot   = 0;
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        assign axi4_read_fifo.arqos    = 0;
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        assign axi4_read_fifo.arregion = 0;
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        assign
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          {
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            axi4_m.araddr,
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            axi4_m.arburst,
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            axi4_m.arid,
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            axi4_m.arlen,
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            axi4_m.arsize
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          } = ar_rd_data;
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        assign axi4_m.arcache  = 0;
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        assign axi4_m.arlock   = 0;
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        assign axi4_m.arprot   = 0;
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        assign axi4_m.arqos    = 0;
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        assign axi4_m.arregion = 0;
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      end
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    end
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  endgenerate
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  // --------------------------------------------------------------------
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  //
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  wire ar_rd_empty;
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  wire ar_rd_en = axi4_m.arready & axi4_m.arvalid;
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  assign axi4_m.arvalid = ~ar_rd_empty;
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  sync_fifo #(.W(AR_W), .D(AR_D))
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    ar_fifo
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    (
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      .wr_full(ar_wr_full),
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      .wr_data(ar_wr_data),
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      .wr_en(ar_wr_en),
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      .rd_empty(ar_rd_empty),
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      .rd_data(ar_rd_data),
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      .rd_en(ar_rd_en),
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      .count(),
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      .clk(aclk),
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      .reset(~aresetn)
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    );
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  // --------------------------------------------------------------------
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  //
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  wire [R_W-1:0] r_rd_data;
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  wire [R_W-1:0] r_wr_data;
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  assign r_wr_data =
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    {
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      axi4_m.rdata,
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      axi4_m.rid,
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      axi4_m.rlast,
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      axi4_m.rresp
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    };
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  assign
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    {
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      axi4_read_fifo.rdata,
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      axi4_read_fifo.rid,
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      axi4_read_fifo.rlast,
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      axi4_read_fifo.rresp
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    } = r_rd_data;
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  // --------------------------------------------------------------------
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  //
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  wire [UB:0] r_count;
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  generate
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    begin: r_watermark_gen
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      if(WATERMARK == 0)
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      begin
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        assign r_topped_off = 1;
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        assign r_watermark = 0;
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      end
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      else
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      begin
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        reg r_topped_off_r;
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        assign r_topped_off = r_topped_off_r;
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        assign r_watermark = r_count > WATERMARK - 1;
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        always_ff @(posedge aclk)
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          if(~aresetn | r_rd_empty)
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            r_topped_off_r <= 0;
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          else if(r_watermark)
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            r_topped_off_r <= 1;
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      end
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    end
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  endgenerate
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  // --------------------------------------------------------------------
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  //
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  wire r_wr_full;
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  wire r_wr_en = axi4_m.rready & axi4_m.rvalid;
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  assign axi4_m.rready = ~r_wr_full;
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  sync_fifo #(.W(R_W), .D(R_D))
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    r_fifo
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    (
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      .wr_full(r_wr_full),
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      .wr_data(r_wr_data),
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      .wr_en(r_wr_en),
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      .rd_empty(r_rd_empty),
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      .rd_data(r_rd_data),
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      .rd_en(r_rd_en),
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      .count(r_count),
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      .clk(aclk),
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      .reset(~aresetn)
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    );
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// --------------------------------------------------------------------
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//
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endmodule
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