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[/] [qaz_libs/] [trunk/] [axi4_lib/] [src/] [axi4_register_slice.sv] - Blame information for rev 29

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1 29 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  axi4_register_slice
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  #(
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    A = 32, // address bus width
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    N = 8,  // data bus width in bytes
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    I = 1,  // ID width
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    USE_ADVANCED_PROTOCOL = 0
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  )
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  (
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    axi4_if axi4_s,
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    axi4_if axi4_m,
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    input   aclk,
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    input   aresetn
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  );
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  // --------------------------------------------------------------------
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  //
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  wire ar_rd_empty;
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  wire ar_rd_en = axi4_m.arvalid & axi4_m.arready;
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  wire r_wr_full;
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  wire r_wr_en = axi4_m.rvalid & axi4_m.rready;
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  axi4_if #(.A(A), .N(N), .I(I))
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    axi4_read_fifo(.*);
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  // --------------------------------------------------------------------
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  //
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  axi4_to_read_fifos
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    #(
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      .A(A),
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      .N(N),
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      .I(I),
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      .USE_ADVANCED_PROTOCOL(USE_ADVANCED_PROTOCOL)
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    )
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    axi4_to_read_fifos_i(.*);
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  // --------------------------------------------------------------------
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  //
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  assign axi4_m.arid    = axi4_read_fifo.arid;
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  assign axi4_m.araddr  = axi4_read_fifo.araddr;
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  assign axi4_m.arburst = axi4_read_fifo.arburst;
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  assign axi4_m.arlen   = axi4_read_fifo.arlen;
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  assign axi4_m.arsize  = axi4_read_fifo.arsize;
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  assign axi4_m.arvalid = ~ar_rd_empty;
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  generate
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    begin: ar_assign_gen
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      if(USE_ADVANCED_PROTOCOL)
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      begin
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        assign axi4_m.arcache   = axi4_read_fifo.arcache;
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        assign axi4_m.arlock    = axi4_read_fifo.arlock;
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        assign axi4_m.arprot    = axi4_read_fifo.arprot;
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        assign axi4_m.arqos     = axi4_read_fifo.arqos;
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        assign axi4_m.arregion  = axi4_read_fifo.arregion;
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      end
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      else
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      begin
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        assign axi4_m.arcache   = 0;
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        assign axi4_m.arlock    = 0;
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        assign axi4_m.arprot    = 0;
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        assign axi4_m.arqos     = 0;
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        assign axi4_m.arregion  = 0;
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      end
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    end
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  endgenerate
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  // --------------------------------------------------------------------
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  //
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  assign axi4_m.rready        = ~r_wr_full;
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  assign axi4_read_fifo.rdata = axi4_m.rdata;
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  assign axi4_read_fifo.rid   = axi4_m.rid;
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  assign axi4_read_fifo.rlast = axi4_m.rlast;
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  assign axi4_read_fifo.rresp = axi4_m.rresp;
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  // --------------------------------------------------------------------
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  //
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  wire aw_rd_empty;
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  wire aw_rd_en = axi4_m.awvalid & axi4_m.awready;
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  wire w_rd_empty;
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  wire w_rd_en = axi4_m.wvalid & axi4_m.wready;
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  wire b_wr_full;
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  wire b_wr_en = axi4_m.bvalid & axi4_m.bready;
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  axi4_if #(.A(A), .N(N), .I(I))
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    axi4_write_fifo(.*);
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  // --------------------------------------------------------------------
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  //
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  axi4_to_write_fifos
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    #(
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      .A(A),
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      .N(N),
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      .I(I),
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      .USE_ADVANCED_PROTOCOL(USE_ADVANCED_PROTOCOL)
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    )
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    axi4_to_write_fifos_i(.*);
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  // --------------------------------------------------------------------
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  //
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  assign axi4_m.awid    = axi4_write_fifo.awid;
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  assign axi4_m.awaddr  = axi4_write_fifo.awaddr;
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  assign axi4_m.awburst = axi4_write_fifo.awburst;
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  assign axi4_m.awlen   = axi4_write_fifo.awlen;
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  assign axi4_m.awsize  = axi4_write_fifo.awsize;
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  assign axi4_m.awvalid = ~aw_rd_empty;
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  generate
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    begin: aw_assign_gen
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      if(USE_ADVANCED_PROTOCOL)
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      begin
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        assign axi4_m.awcache   = axi4_write_fifo.awcache;
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        assign axi4_m.awlock    = axi4_write_fifo.awlock;
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        assign axi4_m.awprot    = axi4_write_fifo.awprot;
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        assign axi4_m.awqos     = axi4_write_fifo.awqos;
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        assign axi4_m.awregion  = axi4_write_fifo.awregion;
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      end
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      else
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      begin
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        assign axi4_m.awcache   = 0;
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        assign axi4_m.awlock    = 0;
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        assign axi4_m.awprot    = 0;
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        assign axi4_m.awqos     = 0;
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        assign axi4_m.awregion  = 0;
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      end
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    end
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  endgenerate
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  // --------------------------------------------------------------------
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  //
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  assign axi4_m.wvalid  = ~w_rd_empty;
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  assign axi4_m.wdata   = axi4_write_fifo.wdata;
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  assign axi4_m.wid     = axi4_write_fifo.wid;
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  assign axi4_m.wlast   = axi4_write_fifo.wlast;
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  assign axi4_m.wstrb   = axi4_write_fifo.wstrb;
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  // --------------------------------------------------------------------
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  //
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  assign axi4_m.bready        = ~b_wr_full;
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  assign axi4_write_fifo.bid   = axi4_m.bid;
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  assign axi4_write_fifo.bresp = axi4_m.bresp;
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// --------------------------------------------------------------------
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//
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endmodule
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