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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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interface
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axi4_lite_register_if
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#(
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N = 8, // data bus width in bytes, must be 4 or 8 for axi lite
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MW = 3, // mux select width
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MI = 2 ** MW // mux inputs
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);
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wire [(N*8)-1:0] register_in [MI-1:0];
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reg [(N*8)-1:0] register_out [MI-1:0];
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qaztronic |
wire wr_en [MI-1:0];
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qaztronic |
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// --------------------------------------------------------------------
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// synthesis translate_off
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initial
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a_data_bus_width: assert((N == 8) | (N == 4)) else $fatal;
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// synthesis translate_on
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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endinterface
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