OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_if.sv] - Blame information for rev 29

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 23 qaztronic
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
4
////                                                              ////
5
//// This source file may be used and distributed without         ////
6
//// restriction provided that this copyright statement is not    ////
7
//// removed from the file and that any derivative work contains  ////
8
//// the original copyright notice and the associated disclaimer. ////
9
////                                                              ////
10
//// This source file is free software; you can redistribute it   ////
11
//// and/or modify it under the terms of the GNU Lesser General   ////
12
//// Public License as published by the Free Software Foundation; ////
13
//// either version 2.1 of the License, or (at your option) any   ////
14
//// later version.                                               ////
15
////                                                              ////
16
//// This source is distributed in the hope that it will be       ////
17
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
18
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
19
//// PURPOSE.  See the GNU Lesser General Public License for more ////
20
//// details.                                                     ////
21
////                                                              ////
22
//// You should have received a copy of the GNU Lesser General    ////
23
//// Public License along with this source; if not, download it   ////
24
//// from http://www.opencores.org/lgpl.shtml                     ////
25
////                                                              ////
26
//////////////////////////////////////////////////////////////////////
27
 
28
 
29
interface
30
  axis_if
31
  #(
32
    N = 8,  // data bus width in bytes
33
    I = 1,  // TID width
34
    D = 1,  // TDEST width
35
    U = 1   // TUSER width
36
  )
37
  (
38
    input             aclk,
39
    input             aresetn
40
  );
41
    wire              tvalid;
42
    wire              tready;
43
    wire  [(8*N)-1:0] tdata;
44
    wire  [N-1:0]     tstrb;
45
    wire  [N-1:0]     tkeep;
46
    wire              tlast;
47
    wire  [I-1:0]     tid;
48
    wire  [D-1:0]     tdest;
49
    wire  [U-1:0]     tuser;
50
 
51
 
52
    // --------------------------------------------------------------------
53
    //
54
    default clocking cb_m @(posedge aclk iff aresetn);
55
      input   aresetn;
56
      input   aclk;
57
      output  tvalid;
58
      input   tready;
59
      output  tdata;
60
      output  tstrb;
61
      output  tkeep;
62
      output  tlast;
63
      output  tid;
64
      output  tdest;
65
      output  tuser;
66
    endclocking
67
 
68
 
69
    // --------------------------------------------------------------------
70
    //
71
    clocking cb_s @(posedge aclk iff aresetn);
72
      input   aresetn;
73
      input   aclk;
74
      input   tvalid;
75
      output  tready;
76
      input   tdata;
77
      input   tstrb;
78
      input   tkeep;
79
      input   tlast;
80
      input   tid;
81
      input   tdest;
82
      input   tuser;
83
    endclocking
84
 
85
 
86
    // --------------------------------------------------------------------
87
    //
88
    modport
89
      master
90
      (
91
        input     aresetn,
92
        input     aclk,
93
        output    tvalid,
94
        input     tready,
95
        output    tdata,
96
        output    tstrb,
97
        output    tkeep,
98
        output    tlast,
99
        output    tid,
100
        output    tdest,
101
        output    tuser,
102
        clocking  cb_m
103
      );
104
 
105
 
106
    // --------------------------------------------------------------------
107
    //
108
    modport
109
      slave
110
      (
111
        input     aresetn,
112
        input     aclk,
113
        input     tvalid,
114
        output    tready,
115
        input     tdata,
116
        input     tstrb,
117
        input     tkeep,
118
        input     tlast,
119
        input     tid,
120
        input     tdest,
121
        input     tuser,
122
        clocking  cb_s
123
      );
124
 
125
 
126
endinterface: axis_if
127
 
128
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.