OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_map_fifo.sv] - Blame information for rev 31

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 31 qaztronic
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
4
////                                                              ////
5
//// This source file may be used and distributed without         ////
6
//// restriction provided that this copyright statement is not    ////
7
//// removed from the file and that any derivative work contains  ////
8
//// the original copyright notice and the associated disclaimer. ////
9
////                                                              ////
10
//// This source file is free software; you can redistribute it   ////
11
//// and/or modify it under the terms of the GNU Lesser General   ////
12
//// Public License as published by the Free Software Foundation; ////
13
//// either version 2.1 of the License, or (at your option) any   ////
14
//// later version.                                               ////
15
////                                                              ////
16
//// This source is distributed in the hope that it will be       ////
17
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
18
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
19
//// PURPOSE.  See the GNU Lesser General Public License for more ////
20
//// details.                                                     ////
21
////                                                              ////
22
//// You should have received a copy of the GNU Lesser General    ////
23
//// Public License along with this source; if not, download it   ////
24
//// from http://www.opencores.org/lgpl.shtml                     ////
25
////                                                              ////
26
//////////////////////////////////////////////////////////////////////
27
 
28
module
29
  axis_map_fifo
30
  #(
31
    N = 8,          // data bus width in bytes
32
    I = 0,          // TID width
33
    D = 0,          // TDEST width
34
    U = 1,          // TUSER width
35
    USE_TSTRB = 0,  //  set to 1 to enable, 0 to disable
36
    USE_TKEEP = 0,  //  set to 1 to enable, 0 to disable
37
    USE_XID = 0,    //  set to 1 to enable, 0 to disable
38
    W = 0
39
  )
40
  (
41
    axis_if         axis_in,
42
    axis_if         axis_out,
43
    output  [W-1:0] wr_data,
44
    input   [W-1:0] rd_data,
45
    input           aclk,
46
    input           aresetn
47
  );
48
 
49
// --------------------------------------------------------------------
50
// synthesis translate_off
51
  initial
52
  begin
53
    a_tid_unsuported:   assert(I == 0) else $fatal;
54
    a_tdest_unsuported: assert(D == 0) else $fatal;
55
    a_xid_unsuported: assert(USE_XID == 0) else $fatal;
56
    a_w: assert(W == (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1) else $fatal;
57
  end
58
// synthesis translate_on
59
// --------------------------------------------------------------------
60
 
61
 
62
  // --------------------------------------------------------------------
63
  //
64
  generate
65
    begin: assign_gen
66
      if(USE_TSTRB & USE_TKEEP)
67
      begin
68
        assign wr_data =
69
          {
70
            axis_in.tdata,
71
            axis_in.tlast,
72
            axis_in.tuser,
73
            axis_in.tstrb,
74
            axis_in.tkeep
75
          };
76
        assign
77
          {
78
            axis_out.tdata,
79
            axis_out.tlast,
80
            axis_out.tuser,
81
            axis_out.tstrb,
82
            axis_out.tkeep
83
          } = rd_data;
84
      end
85
      else if(USE_TSTRB)
86
      begin
87
        assign wr_data =
88
          {
89
            axis_in.tdata,
90
            axis_in.tlast,
91
            axis_in.tuser,
92
            axis_in.tstrb
93
          };
94
        assign
95
          {
96
            axis_out.tdata,
97
            axis_out.tlast,
98
            axis_out.tuser,
99
            axis_out.tstrb
100
          } = rd_data;
101
      end
102
      else if(USE_TKEEP)
103
      begin
104
        assign wr_data =
105
          {
106
            axis_in.tdata,
107
            axis_in.tlast,
108
            axis_in.tuser,
109
            axis_in.tkeep
110
          };
111
        assign
112
          {
113
            axis_out.tdata,
114
            axis_out.tlast,
115
            axis_out.tuser,
116
            axis_out.tkeep
117
          } = rd_data;
118
      end
119
      else
120
      begin
121
        assign wr_data =
122
          {
123
            axis_in.tdata,
124
            axis_in.tlast,
125
            axis_in.tuser
126
          };
127
        assign
128
          {
129
            axis_out.tdata,
130
            axis_out.tlast,
131
            axis_out.tuser
132
          } = rd_data;
133
      end
134
    end
135
  endgenerate
136
 
137
 
138
// --------------------------------------------------------------------
139
//
140
endmodule
141
 

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.