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//////////////////////////////////////////////////////////////////////

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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////

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//////////////////////////////////////////////////////////////////////

module

  axis_mux

  #(

    N = 8,          // data bus width in bytes

    I = 1,          // TID width

    D = 1,          // TDEST width

    U = 1,          // TUSER width

    USE_TSTRB = 0,  //  set to 1 to enable, 0 to disable

    USE_TKEEP = 0   //  set to 1 to enable, 0 to disable

  )

  (

    input           mux_select,

    axis_if.slave   axis_0_in,

    axis_if.slave   axis_1_in,

    axis_if.master  axis_out,

    input           axis_en,

    input           aclk,

    input           aresetn

  );

  // --------------------------------------------------------------------

  //

  axis_if #(.N(N), .I(I), .D(D), .U(U))

    axis_mux_out(.*);

  assign axis_0_in.tready = mux_select ? 0                    : axis_mux_out.tready;

  assign axis_1_in.tready = mux_select ? axis_mux_out.tready  : 0;

  assign axis_mux_out.tvalid = mux_select ? axis_1_in.tvalid : axis_0_in.tvalid;

  assign axis_mux_out.tdata  = mux_select ? axis_1_in.tdata  : axis_0_in.tdata;

  assign axis_mux_out.tstrb  = mux_select ? axis_1_in.tstrb  : axis_0_in.tstrb;

  assign axis_mux_out.tkeep  = mux_select ? axis_1_in.tkeep  : axis_0_in.tkeep;

  assign axis_mux_out.tlast  = mux_select ? axis_1_in.tlast  : axis_0_in.tlast;

  assign axis_mux_out.tid    = mux_select ? axis_1_in.tid    : axis_0_in.tid;

  assign axis_mux_out.tdest  = mux_select ? axis_1_in.tdest  : axis_0_in.tdest;

  assign axis_mux_out.tuser  = mux_select ? axis_1_in.tuser  : axis_0_in.tuser;

  // --------------------------------------------------------------------

  //

  axis_register_slice

    #(

      .N(N),

      .I(I),

      .D(D),

      .U(U),

      .USE_TSTRB(USE_TSTRB),

      .USE_TKEEP(USE_TKEEP)

    )

    axis_register_slice_i

    (

      .axis_in(axis_mux_out), //  .slave

      .axis_out(axis_out),    //  .master

      .*

    );

  // --------------------------------------------------------------------

  //

endmodule