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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_upsizer.sv] - Blame information for rev 31

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1 31 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  axis_upsizer
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  #(
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    N,              // data bus width in bytes
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    I = 1,          // TID width
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    D = 1,          // TDEST width
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    U,              // TUSER width
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    S,              // tdata size multiplier
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    USE_TSTRB = 0,  //  set to 1 to enable, 0 to disable
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    USE_TKEEP = 0,  //  set to 1 to enable, 0 to disable
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    BYTES_PER_TUSER //  bytes per tuser bit. Set to 0 for transfer based.
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  )
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  (
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    axis_if axis_in,
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    axis_if axis_out,
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    input   aclk,
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    input   aresetn
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  );
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// --------------------------------------------------------------------
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// synthesis translate_off
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  initial
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  begin
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    a_multiplier: assert((S > 1) & (S % 2 == 0))else $fatal;
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    a_tstrb_unsuported: assert(USE_TSTRB == 0) else $fatal;
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    a_tkeep_unsuported: assert(USE_TKEEP == 0) else $fatal;
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    a_bytes_per_tuser: assert((BYTES_PER_TUSER == 0) | (N % BYTES_PER_TUSER == 0)) else $fatal;
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    a_tuser: assert((BYTES_PER_TUSER == 0) | (U % S == 0)) else $fatal;
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  end
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// synthesis translate_on
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// --------------------------------------------------------------------
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  // --------------------------------------------------------------------
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  //
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  localparam A = $clog2(S);
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  localparam ED = 2 ** A;
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  // --------------------------------------------------------------------
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  //
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  axis_if #(.N(N*S), .U(U*S)) axis_upsizer_bus(.*);
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  wire last_word;
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  //---------------------------------------------------
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  //  state machine binary definitions
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  enum reg [1:0]
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    {
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      GET_WORDS_IN  = 2'b01,
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      WORD_OUT      = 2'b10
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    } state, next_state;
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  //---------------------------------------------------
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  //  state machine flop
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  always_ff @(posedge aclk)
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    if(~aresetn)
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      state <= GET_WORDS_IN;
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    else
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      state <= next_state;
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  //---------------------------------------------------
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  //  state machine
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  always_comb
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    case(state)
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      GET_WORDS_IN:         if(axis_in.tvalid & last_word)
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                              next_state <= WORD_OUT;
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                            else
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                              next_state <= GET_WORDS_IN;
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      WORD_OUT:             if(axis_upsizer_bus.tready)
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                              next_state <= GET_WORDS_IN;
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                            else
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                              next_state <= WORD_OUT;
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      default:              next_state <= GET_WORDS_IN;
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    endcase
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  // --------------------------------------------------------------------
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  //
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  reg [A-1:0] index;
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  wire roll_over = ~(index < S - 1) & axis_in.tready & axis_in.tvalid;
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  always_ff @(posedge aclk)
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    if(~aresetn | roll_over)
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      index <= 0;
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    else if(axis_in.tready & axis_in.tvalid)
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      index <= index + 1;
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  // --------------------------------------------------------------------
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  //
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  wire [ED-1:0] encoded;
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  assign last_word = encoded[S-1];
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  one_hot_encoder #(A)
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    one_hot_encoder_i(index, encoded);
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  // --------------------------------------------------------------------
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  //
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  reg tlast_in[S];
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  reg [U-1:0] tuser_in[S];
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  reg [(8*N)-1:0] tdata_in[S];
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  wire [S-1:0] tlast_out_w;
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  wire [(U*S)-1:0] tuser_out_w;
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  wire [(8*N*S)-1:0] tdata_out_w;
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  genvar j;
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  generate
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    for(j = 0; j < S; j++)
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    begin: tdata_gen
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      always_ff @(posedge aclk)
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        if(encoded[j] & axis_in.tready & axis_in.tvalid)
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        begin
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          tdata_in[j] <= axis_in.tdata;
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          tuser_in[j] <= axis_in.tuser;
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          tlast_in[j] <= axis_in.tlast;
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        end
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      assign tlast_out_w[j]             = tlast_in[j];
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      assign tuser_out_w[j*U +: U]      = tuser_in[j];
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      assign tdata_out_w[j*N*8 +: N*8]  = tdata_in[j];
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    end
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  endgenerate
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  // --------------------------------------------------------------------
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  //
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  assign axis_in.tready = (state == GET_WORDS_IN) | (next_state == GET_WORDS_IN);
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  assign axis_upsizer_bus.tvalid  = (state == WORD_OUT);
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  assign axis_upsizer_bus.tdata = tdata_out_w;
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  assign axis_upsizer_bus.tuser = tuser_out_w;
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  assign axis_upsizer_bus.tlast = tlast_out_w[S-1];
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  // --------------------------------------------------------------------
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  //
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  axis_register_slice #(.N(N*S), .U(U*S))
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    axis_register_slice_i(.axis_in(axis_upsizer_bus), .*);
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// --------------------------------------------------------------------
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//
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endmodule
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