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[/] [qaz_libs/] [trunk/] [basal/] [sim/] [tests/] [tb_fifo/] [fifo_if.sv] - Blame information for rev 44

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1 44 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2018 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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interface
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  fifo_if
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  #(
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    W,
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    D,
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    UB = $clog2(D)
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  )
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  (
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    input reset,
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    input clk
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  );
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  import uvm_pkg::*;
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  `include "uvm_macros.svh"
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  import tb_fifo_pkg::*;
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  // --------------------------------------------------------------------
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  wire          wr_full;
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  wire  [W-1:0] wr_data;
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  wire          wr_en;
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  wire          rd_empty;
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  wire  [W-1:0] rd_data;
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  wire          rd_en;
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  wire  [UB:0]  count;
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  // --------------------------------------------------------------------
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  default clocking cb @(posedge clk);
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    input reset;
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    input wr_full;
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    input rd_empty;
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    input rd_data;
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    input count;
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    inout rd_en;
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    inout wr_en;
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    inout wr_data;
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  endclocking
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  // --------------------------------------------------------------------
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  task zero_cycle_delay;
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    ##0;
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  endtask: zero_cycle_delay
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// --------------------------------------------------------------------
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endinterface

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