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1 34 qaztronic
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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// 
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// All rights reserved.
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// 
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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//     - Redistributions of source code must retain the above copyright
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//       notice, this list of conditions and the following disclaimer.
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//     - Redistributions in binary form must reproduce the above copyright
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//       notice, this list of conditions and the following disclaimer in
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//       the documentation and/or other materials provided with the
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//       distribution.
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//     - Neither the name of Analog Devices, Inc. nor the names of its
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//       contributors may be used to endorse or promote products derived
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//       from this software without specific prior written permission.
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//     - The use of this software may or may not infringe the patent rights
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//       of one or more patent holders.  This license does not release you
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//       from the requirement that you obtain separate licenses from these
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//       patent holders to use this software.
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//     - Use of the software either in source or binary form, must be run
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//       on or directly connected to an Analog Devices Inc. component.
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//    
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// PN monitors
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`timescale 1ns/100ps
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module cf_pnmon (
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  // adc interface
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  adc_clk,
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  adc_data,
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  // pn out of sync and error
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  adc_pn_oos,
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  adc_pn_err,
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  // processor interface PN9 (0x0), PN23 (0x1)
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  up_pn_type);
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  // adc interface
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  input           adc_clk;
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  input   [13:0]  adc_data;
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  // pn out of sync and error
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  output          adc_pn_oos;
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  output          adc_pn_err;
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  // processor interface PN9 (0x0), PN23 (0x1)
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  input           up_pn_type;
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  reg             adc_pn_type_m1 = 'd0;
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  reg             adc_pn_type_m2 = 'd0;
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  reg             adc_pn_type = 'd0;
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  reg             adc_pn_en = 'd0;
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  reg     [13:0]  adc_data_d = 'd0;
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  reg     [27:0]  adc_pn_data = 'd0;
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  reg             adc_pn_en_d = 'd0;
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  reg             adc_pn_match = 'd0;
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  reg     [ 6:0]  adc_pn_oos_count = 'd0;
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  reg             adc_pn_oos = 'd0;
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  reg     [ 4:0]  adc_pn_err_count = 'd0;
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  reg             adc_pn_err = 'd0;
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  wire    [27:0]  adc_pn_data_in_s;
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  wire            adc_pn_match0_s;
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  wire            adc_pn_match1_s;
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  wire            adc_pn_match2_s;
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  wire            adc_pn_match_s;
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  wire    [27:0]  adc_pn_data_s;
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  wire            adc_pn_err_s;
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  // PN23 function
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  function [27:0] pn23;
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    input [27:0] din;
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    reg   [27:0] dout;
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    begin
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      dout[27] = din[22] ^ din[17];
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      dout[26] = din[21] ^ din[16];
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      dout[25] = din[20] ^ din[15];
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      dout[24] = din[19] ^ din[14];
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      dout[23] = din[18] ^ din[13];
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      dout[22] = din[17] ^ din[12];
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      dout[21] = din[16] ^ din[11];
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      dout[20] = din[15] ^ din[10];
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      dout[19] = din[14] ^ din[ 9];
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      dout[18] = din[13] ^ din[ 8];
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      dout[17] = din[12] ^ din[ 7];
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      dout[16] = din[11] ^ din[ 6];
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      dout[15] = din[10] ^ din[ 5];
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      dout[14] = din[ 9] ^ din[ 4];
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      dout[13] = din[ 8] ^ din[ 3];
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      dout[12] = din[ 7] ^ din[ 2];
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      dout[11] = din[ 6] ^ din[ 1];
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      dout[10] = din[ 5] ^ din[ 0];
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      dout[ 9] = din[ 4] ^ din[22] ^ din[17];
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      dout[ 8] = din[ 3] ^ din[21] ^ din[16];
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      dout[ 7] = din[ 2] ^ din[20] ^ din[15];
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      dout[ 6] = din[ 1] ^ din[19] ^ din[14];
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      dout[ 5] = din[ 0] ^ din[18] ^ din[13];
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      dout[ 4] = din[22] ^ din[12];
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      dout[ 3] = din[21] ^ din[11];
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      dout[ 2] = din[20] ^ din[10];
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      dout[ 1] = din[19] ^ din[ 9];
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      dout[ 0] = din[18] ^ din[ 8];
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      pn23 = dout;
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    end
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  endfunction
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  // PN9 function
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  function [27:0] pn9;
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    input [27:0] din;
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    reg   [27:0] dout;
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    begin
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      dout[27] = din[ 8] ^ din[ 4];
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      dout[26] = din[ 7] ^ din[ 3];
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      dout[25] = din[ 6] ^ din[ 2];
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      dout[24] = din[ 5] ^ din[ 1];
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      dout[23] = din[ 4] ^ din[ 0];
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      dout[22] = din[ 3] ^ din[ 8] ^ din[ 4];
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      dout[21] = din[ 2] ^ din[ 7] ^ din[ 3];
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      dout[20] = din[ 1] ^ din[ 6] ^ din[ 2];
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      dout[19] = din[ 0] ^ din[ 5] ^ din[ 1];
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      dout[18] = din[ 8] ^ din[ 0];
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      dout[17] = din[ 7] ^ din[ 8] ^ din[ 4];
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      dout[16] = din[ 6] ^ din[ 7] ^ din[ 3];
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      dout[15] = din[ 5] ^ din[ 6] ^ din[ 2];
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      dout[14] = din[ 4] ^ din[ 5] ^ din[ 1];
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      dout[13] = din[ 3] ^ din[ 4] ^ din[ 0];
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      dout[12] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
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      dout[11] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
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      dout[10] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
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      dout[ 9] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
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      dout[ 8] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
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      dout[ 7] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
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      dout[ 6] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
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      dout[ 5] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
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      dout[ 4] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
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      dout[ 3] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
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      dout[ 2] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
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      dout[ 1] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
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      dout[ 0] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
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      pn9 = dout;
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    end
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  endfunction
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  // This PN sequence checking algorithm is commonly used is most applications.
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  // It is a simple function generated based on the OOS status.
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  // If OOS is asserted (PN is OUT of sync):
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  //    The next sequence is generated from the incoming data.
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  //    If 16 sequences match CONSECUTIVELY, OOS is cleared (de-asserted).
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  // If OOS is de-asserted (PN is IN sync)
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  //    The next sequence is generated from the current sequence.
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  //    If 64 sequences mismatch CONSECUTIVELY, OOS is set (asserted).
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  // If OOS is de-asserted, any spurious mismatches sets the ERROR register.
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  // Ideally, processor should make sure both OOS == 0x0 AND ERR == 0x0.
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  assign adc_pn_data_in_s[27:14] = {adc_data_d[13], adc_data_d[12:0]};
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  assign adc_pn_data_in_s[13: 0] = {adc_data[13], adc_data[12:0]};
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  assign adc_pn_match0_s = (adc_pn_data_in_s[27:14] == adc_pn_data[27:14]) ? 1'b1 : 1'b0;
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  assign adc_pn_match1_s = (adc_pn_data_in_s[13:0] == adc_pn_data[13:0]) ? 1'b1 : 1'b0;
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  assign adc_pn_match2_s = ((adc_data == 14'd0) && (adc_data_d == 14'd0)) ? 1'b0 : 1'b1;
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  assign adc_pn_match_s = adc_pn_match0_s & adc_pn_match1_s & adc_pn_match2_s;
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  assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in_s : adc_pn_data;
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  assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match);
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  // PN running sequence
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  always @(posedge adc_clk) begin
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    adc_pn_type_m1 <= up_pn_type;
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    adc_pn_type_m2 <= adc_pn_type_m1;
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    adc_pn_type <= adc_pn_type_m2;
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    adc_pn_en <= ~adc_pn_en;
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    adc_data_d <= adc_data;
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    if (adc_pn_en == 1'b1) begin
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      if (adc_pn_type == 1'b0) begin
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        adc_pn_data <= pn9(adc_pn_data_s);
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      end else begin
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        adc_pn_data <= pn23(adc_pn_data_s);
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      end
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    end
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  end
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  // PN OOS and counters (16 to clear, 64 to set). These numbers are actually determined
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  // based on BER parameters set by the system (usually in network applications).
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  always @(posedge adc_clk) begin
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    adc_pn_en_d <= adc_pn_en;
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    adc_pn_match <= adc_pn_match_s;
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    if (adc_pn_en_d == 1'b1) begin
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      if (adc_pn_oos == 1'b1) begin
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        if (adc_pn_match == 1'b1) begin
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          if (adc_pn_oos_count >= 16) begin
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            adc_pn_oos_count <= 'd0;
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            adc_pn_oos <= 'd0;
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          end else begin
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            adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
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            adc_pn_oos <= 'd1;
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          end
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        end else begin
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          adc_pn_oos_count <= 'd0;
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          adc_pn_oos <= 'd1;
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        end
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      end else begin
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        if (adc_pn_match == 1'b0) begin
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          if (adc_pn_oos_count >= 64) begin
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            adc_pn_oos_count <= 'd0;
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            adc_pn_oos <= 'd1;
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          end else begin
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            adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
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            adc_pn_oos <= 'd0;
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          end
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        end else begin
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          adc_pn_oos_count <= 'd0;
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          adc_pn_oos <= 'd0;
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        end
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      end
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    end
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  end
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  // The error state is streched to multiple adc clocks such that processor
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  // has enough time to sample the error condition.
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  always @(posedge adc_clk) begin
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    if (adc_pn_en_d == 1'b1) begin
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      if (adc_pn_err_s == 1'b1) begin
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        adc_pn_err_count <= 5'h10;
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      end else if (adc_pn_err_count[4] == 1'b1) begin
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        adc_pn_err_count <= adc_pn_err_count + 1'b1;
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      end
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    end
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    adc_pn_err <= adc_pn_err_count[4];
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  end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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