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[/] [qaz_libs/] [trunk/] [basal/] [src/] [synchronize/] [sync_reset.v] - Blame information for rev 34

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1 34 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  sync_reset
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  #(
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    parameter ASSERT_LENGTH = 8
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  )
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  (
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    input clk_in,
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    input async_reset_in,
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    output sync_reset_out
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  );
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  // --------------------------------------------------------------------
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  reg [(ASSERT_LENGTH-1):0] sync_reset_out_r;
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  assign    sync_reset_out = sync_reset_out_r[ASSERT_LENGTH-1];
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  always @(posedge clk_in or posedge async_reset_in)
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    if(async_reset_in)
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      sync_reset_out_r <= {ASSERT_LENGTH{1'b1}};
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    else
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      sync_reset_out_r <= {sync_reset_out_r[(ASSERT_LENGTH-2):0], 1'b0};
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endmodule
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