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qaztronic |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module
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avf_line_buffer_row #(N, W, AW, EOL_TO_PASS)
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(
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axis_if axis_in,
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axis_if axis_out,
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input enable,
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output zero_pad,
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output initialized,
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input aclk,
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input aresetn
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);
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// --------------------------------------------------------------------
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wire in_eol = axis_in.tlast & axis_in.tready & axis_in.tvalid;
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wire in_eof = axis_in.tuser[2] & axis_in.tready & axis_in.tvalid;
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wire primed;
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// --------------------------------------------------------------------
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generate
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begin: counter_gen
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if(EOL_TO_PASS == 0)
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begin: first_line_gen // don't let any EOL pass through.
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// ---------------- // The trailing FIFO is primed by the first line.
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assign primed = in_eol;
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end
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else
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begin: remainder_lines_gen
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// --------------------------------------------------------------------
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reg [$clog2(EOL_TO_PASS)-1:0] eol_count;
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assign primed = (eol_count == EOL_TO_PASS) & in_eol;
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always_ff @(posedge aclk)
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if(~aresetn | primed)
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eol_count <= 0;
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else if(in_eol)
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eol_count <= eol_count + 1;
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end
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end
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endgenerate
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// --------------------------------------------------------------------
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localparam UB = $clog2(AW*2);
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localparam D = 2**UB;
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// --------------------------------------------------------------------
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wire [UB:0] count;
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wire wr_full;
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wire rd_empty;
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wire [W-1:0] wr_data = {axis_in.tlast, axis_in.tuser, axis_in.tdata};
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wire wr_en = axis_in.tready & axis_in.tvalid;
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wire rd_en = axis_out.tready & axis_out.tvalid;
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wire [W-1:0] rd_data;
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assign {axis_out.tlast, axis_out.tuser, axis_out.tdata} = rd_data;
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sync_fifo #(W, D) fifo_i(.clk(aclk), .reset(~aresetn), .*);
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// --------------------------------------------------------------------
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enum reg [3:0]
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{
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PRIME = 4'b0001,
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INITIALIZED = 4'b0010,
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READY = 4'b0100,
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FLUSH = 4'b1000
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} state, next_state;
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// --------------------------------------------------------------------
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always_ff @(posedge aclk)
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if(~aresetn)
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state <= PRIME;
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else
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state <= next_state;
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// --------------------------------------------------------------------
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always_comb
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case(state)
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PRIME: if(primed)
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next_state = INITIALIZED;
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else
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next_state = PRIME;
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INITIALIZED: if(enable)
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next_state = READY;
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else
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next_state = INITIALIZED;
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READY: if(in_eof)
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next_state = FLUSH;
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else
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next_state = READY;
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FLUSH: if(rd_empty)
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next_state = PRIME;
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else
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next_state = FLUSH;
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default: next_state = PRIME;
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endcase
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// --------------------------------------------------------------------
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generate
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if(EOL_TO_PASS == 0) // no pass through for trailing FIFO
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begin: first_line_gen
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assign axis_out.tvalid = ~rd_empty & ((state == READY) | (state == FLUSH));
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end
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else
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begin: remainder_lines_gen
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assign axis_out.tvalid = ~rd_empty & ((state == PRIME) | (state == READY) | (state == FLUSH));
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end
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endgenerate
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// --------------------------------------------------------------------
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assign axis_in.tready = ~wr_full & ((state == PRIME) | (state == READY));
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assign zero_pad = (state == PRIME) | (state == INITIALIZED);
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assign initialized = (state == INITIALIZED);
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// --------------------------------------------------------------------
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endmodule
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