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[/] [qaz_libs/] [trunk/] [zed_board/] [block_diagrams/] [zync_bd_14_4.tcl] - Blame information for rev 27

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1 27 qaztronic
 
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################################################################
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# This is a generated script based on design: zync
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#
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# Though there are limitations about the generated script,
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# the main purpose of this utility is to make learning
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# IP Integrator Tcl commands easier.
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################################################################
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2014.4
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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   puts ""
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   puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."
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   return 1
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}
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################################################################
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# START
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################################################################
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# To test this script, run the following commands from Vivado Tcl console:
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# source zync_script.tcl
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# If you do not already have a project created,
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# you can create a project using the following command:
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#    create_project project_1 myproj -part xc7z020clg484-1
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#    set_property BOARD_PART em.avnet.com:zed:part0:1.2 [current_project]
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# CHANGE DESIGN NAME HERE
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set design_name zync
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# If you do not already have an existing IP Integrator design open,
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# you can create a design using the following command:
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#    create_bd_design $design_name
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# CHECKING IF PROJECT EXISTS
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if { [get_projects -quiet] eq "" } {
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   puts "ERROR: Please open or create a project!"
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   return 1
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}
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# Creating design if needed
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set errMsg ""
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set nRet 0
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set cur_design [current_bd_design -quiet]
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set list_cells [get_bd_cells -quiet]
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if { ${design_name} eq "" } {
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   # USE CASES:
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   #    1) Design_name not set
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   set errMsg "ERROR: Please set the variable <design_name> to a non-empty value."
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   set nRet 1
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} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
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   # USE CASES:
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   #    2): Current design opened AND is empty AND names same.
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   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
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   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
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   if { $cur_design ne $design_name } {
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      puts "INFO: Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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      set design_name [get_property NAME $cur_design]
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   }
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   puts "INFO: Constructing design in IPI design <$cur_design>..."
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} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
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   # USE CASES:
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   #    5) Current design opened AND has components AND same names.
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   set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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   set nRet 1
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} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
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   # USE CASES: 
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   #    6) Current opened design, has components, but diff names, design_name exists in project.
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   #    7) No opened design, design_name exists in project.
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   set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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   set nRet 2
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} else {
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   # USE CASES:
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   #    8) No opened design, design_name not in project.
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   #    9) Current opened design, has components, but diff names, design_name not in project.
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   puts "INFO: Currently there is no design <$design_name> in project, so creating one..."
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   create_bd_design $design_name
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   puts "INFO: Making design <$design_name> as current_bd_design."
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   current_bd_design $design_name
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}
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puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"."
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if { $nRet != 0 } {
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   puts $errMsg
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   return $nRet
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}
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##################################################################
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# DESIGN PROCs
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##################################################################
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# Procedure to create entire design; Provide argument to make
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# procedure reusable. If parentCell is "", will use root.
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proc create_root_design { parentCell } {
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  if { $parentCell eq "" } {
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     set parentCell [get_bd_cells /]
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  }
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  # Get object for parentCell
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  set parentObj [get_bd_cells $parentCell]
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  if { $parentObj == "" } {
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     puts "ERROR: Unable to find parent cell <$parentCell>!"
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     return
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  }
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  # Make sure parentObj is hier blk
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  set parentType [get_property TYPE $parentObj]
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  if { $parentType ne "hier" } {
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     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
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     return
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  }
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  # Save current instance; Restore later
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  set oldCurInst [current_bd_instance .]
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  # Set parent object as current
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  current_bd_instance $parentObj
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  # Create interface ports
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  set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
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  set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
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  set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ]
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  set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.NUM_READ_OUTSTANDING {8} CONFIG.NUM_WRITE_OUTSTANDING {8} CONFIG.PROTOCOL {AXI4LITE}  ] $M00_AXI
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  # Create ports
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  set FCLK_CLK0 [ create_bd_port -dir O -type clk FCLK_CLK0 ]
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  set_property -dict [ list CONFIG.ASSOCIATED_BUSIF {M00_AXI}  ] $FCLK_CLK0
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  set peripheral_aresetn [ create_bd_port -dir O -from 0 -to 0 -type rst peripheral_aresetn ]
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  # Create instance: axi_interconnect_0, and set properties
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  set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
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  set_property -dict [ list CONFIG.NUM_MI {1}  ] $axi_interconnect_0
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  # Create instance: proc_sys_reset_0, and set properties
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  set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
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  # Create instance: processing_system7_0, and set properties
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  set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
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  set_property -dict [ list CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {0} CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} CONFIG.preset {ZedBoard*}  ] $processing_system7_0
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  # Create interface connections
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  connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
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  connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
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  connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
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  connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
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  # Create port connections
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  connect_bd_net -net ARESETN_1 [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins proc_sys_reset_0/interconnect_aresetn]
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  connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_ports peripheral_aresetn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
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  connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FCLK_CLK0] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK]
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  connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N]
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  # Create address segments
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  create_bd_addr_seg -range 0x10000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M00_AXI/Reg] SEG_M00_AXI_Reg
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  # Restore current instance
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  current_bd_instance $oldCurInst
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  save_bd_design
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}
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# End of create_root_design()
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##################################################################
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# MAIN FLOW
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##################################################################
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create_root_design ""
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