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1 15 qaztronic
 
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`timescale 1 ns / 1 ps
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        module reg_file_v1_0_S00_AXI #
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        (
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                // Users to add parameters here
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                // User parameters ends
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                // Do not modify the parameters beyond this line
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                // Width of S_AXI data bus
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                parameter integer C_S_AXI_DATA_WIDTH    = 32,
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                // Width of S_AXI address bus
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                parameter integer C_S_AXI_ADDR_WIDTH    = 4
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        )
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        (
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                // Users to add ports here
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                // User ports ends
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                // Do not modify the ports beyond this line
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                // Global Clock Signal
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                input wire  S_AXI_ACLK,
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                // Global Reset Signal. This Signal is Active LOW
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                input wire  S_AXI_ARESETN,
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                // Write address (issued by master, acceped by Slave)
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                input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
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                // Write channel Protection type. This signal indicates the
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                // privilege and security level of the transaction, and whether
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                // the transaction is a data access or an instruction access.
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                input wire [2 : 0] S_AXI_AWPROT,
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                // Write address valid. This signal indicates that the master signaling
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                // valid write address and control information.
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                input wire  S_AXI_AWVALID,
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                // Write address ready. This signal indicates that the slave is ready
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                // to accept an address and associated control signals.
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                output wire  S_AXI_AWREADY,
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                // Write data (issued by master, acceped by Slave) 
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                input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
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                // Write strobes. This signal indicates which byte lanes hold
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                // valid data. There is one write strobe bit for each eight
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                // bits of the write data bus.    
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                input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
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                // Write valid. This signal indicates that valid write
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                // data and strobes are available.
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                input wire  S_AXI_WVALID,
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                // Write ready. This signal indicates that the slave
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                // can accept the write data.
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                output wire  S_AXI_WREADY,
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                // Write response. This signal indicates the status
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                // of the write transaction.
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                output wire [1 : 0] S_AXI_BRESP,
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                // Write response valid. This signal indicates that the channel
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                // is signaling a valid write response.
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                output wire  S_AXI_BVALID,
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                // Response ready. This signal indicates that the master
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                // can accept a write response.
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                input wire  S_AXI_BREADY,
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                // Read address (issued by master, acceped by Slave)
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                input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
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                // Protection type. This signal indicates the privilege
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                // and security level of the transaction, and whether the
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                // transaction is a data access or an instruction access.
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                input wire [2 : 0] S_AXI_ARPROT,
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                // Read address valid. This signal indicates that the channel
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                // is signaling valid read address and control information.
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                input wire  S_AXI_ARVALID,
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                // Read address ready. This signal indicates that the slave is
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                // ready to accept an address and associated control signals.
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                output wire  S_AXI_ARREADY,
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                // Read data (issued by slave)
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                output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
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                // Read response. This signal indicates the status of the
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                // read transfer.
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                output wire [1 : 0] S_AXI_RRESP,
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                // Read valid. This signal indicates that the channel is
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                // signaling the required read data.
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                output wire  S_AXI_RVALID,
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                // Read ready. This signal indicates that the master can
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                // accept the read data and response information.
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                input wire  S_AXI_RREADY,
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    output reg [C_S_AXI_DATA_WIDTH-1:0]  slv_reg0,
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    output reg [C_S_AXI_DATA_WIDTH-1:0]  slv_reg1,
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    output reg [C_S_AXI_DATA_WIDTH-1:0]  slv_reg2,
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    output reg [C_S_AXI_DATA_WIDTH-1:0]  slv_reg3
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        );
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        // AXI4LITE signals
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        reg [C_S_AXI_ADDR_WIDTH-1 : 0]   axi_awaddr;
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        reg     axi_awready;
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        reg     axi_wready;
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        reg [1 : 0]      axi_bresp;
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        reg     axi_bvalid;
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        reg [C_S_AXI_ADDR_WIDTH-1 : 0]   axi_araddr;
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        reg     axi_arready;
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        reg [C_S_AXI_DATA_WIDTH-1 : 0]   axi_rdata;
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        reg [1 : 0]      axi_rresp;
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        reg     axi_rvalid;
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        // Example-specific design signals
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        // local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
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        // ADDR_LSB is used for addressing 32/64 bit registers/memories
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        // ADDR_LSB = 2 for 32 bits (n downto 2)
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        // ADDR_LSB = 3 for 64 bits (n downto 3)
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        localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
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        localparam integer OPT_MEM_ADDR_BITS = 1;
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        //----------------------------------------------
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        //-- Signals for user logic register space example
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        //------------------------------------------------
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        //-- Number of Slave Registers 4
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        // reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
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        // reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
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        // reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
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        // reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
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        wire     slv_reg_rden;
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        wire     slv_reg_wren;
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        reg [C_S_AXI_DATA_WIDTH-1:0]      reg_data_out;
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        integer  byte_index;
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122
        // I/O Connections assignments
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124
        assign S_AXI_AWREADY    = axi_awready;
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        assign S_AXI_WREADY     = axi_wready;
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        assign S_AXI_BRESP      = axi_bresp;
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        assign S_AXI_BVALID     = axi_bvalid;
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        assign S_AXI_ARREADY    = axi_arready;
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        assign S_AXI_RDATA      = axi_rdata;
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        assign S_AXI_RRESP      = axi_rresp;
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        assign S_AXI_RVALID     = axi_rvalid;
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        // Implement axi_awready generation
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        // axi_awready is asserted for one S_AXI_ACLK clock cycle when both
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        // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
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        // de-asserted when reset is low.
136
 
137
        always @( posedge S_AXI_ACLK )
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        begin
139
          if ( S_AXI_ARESETN == 1'b0 )
140
            begin
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              axi_awready <= 1'b0;
142
            end
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          else
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            begin
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              if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
146
                begin
147
                  // slave is ready to accept write address when 
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                  // there is a valid write address and write data
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                  // on the write address and data bus. This design 
150
                  // expects no outstanding transactions. 
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                  axi_awready <= 1'b1;
152
                end
153
              else
154
                begin
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                  axi_awready <= 1'b0;
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                end
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            end
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        end
159
 
160
        // Implement axi_awaddr latching
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        // This process is used to latch the address when both 
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        // S_AXI_AWVALID and S_AXI_WVALID are valid. 
163
 
164
        always @( posedge S_AXI_ACLK )
165
        begin
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          if ( S_AXI_ARESETN == 1'b0 )
167
            begin
168
              axi_awaddr <= 0;
169
            end
170
          else
171
            begin
172
              if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
173
                begin
174
                  // Write Address latching 
175
                  axi_awaddr <= S_AXI_AWADDR;
176
                end
177
            end
178
        end
179
 
180
        // Implement axi_wready generation
181
        // axi_wready is asserted for one S_AXI_ACLK clock cycle when both
182
        // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is 
183
        // de-asserted when reset is low. 
184
 
185
        always @( posedge S_AXI_ACLK )
186
        begin
187
          if ( S_AXI_ARESETN == 1'b0 )
188
            begin
189
              axi_wready <= 1'b0;
190
            end
191
          else
192
            begin
193
              if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
194
                begin
195
                  // slave is ready to accept write data when 
196
                  // there is a valid write address and write data
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                  // on the write address and data bus. This design 
198
                  // expects no outstanding transactions. 
199
                  axi_wready <= 1'b1;
200
                end
201
              else
202
                begin
203
                  axi_wready <= 1'b0;
204
                end
205
            end
206
        end
207
 
208
        // Implement memory mapped register select and write logic generation
209
        // The write data is accepted and written to memory mapped registers when
210
        // axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
211
        // select byte enables of slave registers while writing.
212
        // These registers are cleared when reset (active low) is applied.
213
        // Slave register write enable is asserted when valid address and data are available
214
        // and the slave is ready to accept the write address and write data.
215
        assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
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217
        always @( posedge S_AXI_ACLK )
218
        begin
219
          if ( S_AXI_ARESETN == 1'b0 )
220
            begin
221
              slv_reg0 <= 0;
222
              slv_reg1 <= 0;
223
              slv_reg2 <= 0;
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              slv_reg3 <= 0;
225
            end
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          else begin
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            if (slv_reg_wren)
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              begin
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                case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
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                  2'h0:
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                    for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
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                      if ( S_AXI_WSTRB[byte_index] == 1 ) begin
233
                        // Respective byte enables are asserted as per write strobes 
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                        // Slave register 0
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                        slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
236
                      end
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                  2'h1:
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                    for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
239
                      if ( S_AXI_WSTRB[byte_index] == 1 ) begin
240
                        // Respective byte enables are asserted as per write strobes 
241
                        // Slave register 1
242
                        slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
243
                      end
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                  2'h2:
245
                    for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
246
                      if ( S_AXI_WSTRB[byte_index] == 1 ) begin
247
                        // Respective byte enables are asserted as per write strobes 
248
                        // Slave register 2
249
                        slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
250
                      end
251
                  2'h3:
252
                    for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
253
                      if ( S_AXI_WSTRB[byte_index] == 1 ) begin
254
                        // Respective byte enables are asserted as per write strobes 
255
                        // Slave register 3
256
                        slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
257
                      end
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                  default : begin
259
                              slv_reg0 <= slv_reg0;
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                              slv_reg1 <= slv_reg1;
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                              slv_reg2 <= slv_reg2;
262
                              slv_reg3 <= slv_reg3;
263
                            end
264
                endcase
265
              end
266
          end
267
        end
268
 
269
        // Implement write response logic generation
270
        // The write response and response valid signals are asserted by the slave 
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        // when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.  
272
        // This marks the acceptance of address and indicates the status of 
273
        // write transaction.
274
 
275
        always @( posedge S_AXI_ACLK )
276
        begin
277
          if ( S_AXI_ARESETN == 1'b0 )
278
            begin
279
              axi_bvalid  <= 0;
280
              axi_bresp   <= 2'b0;
281
            end
282
          else
283
            begin
284
              if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
285
                begin
286
                  // indicates a valid write response is available
287
                  axi_bvalid <= 1'b1;
288
                  axi_bresp  <= 2'b0; // 'OKAY' response 
289
                end                   // work error responses in future
290
              else
291
                begin
292
                  if (S_AXI_BREADY && axi_bvalid)
293
                    //check if bready is asserted while bvalid is high) 
294
                    //(there is a possibility that bready is always asserted high)   
295
                    begin
296
                      axi_bvalid <= 1'b0;
297
                    end
298
                end
299
            end
300
        end
301
 
302
        // Implement axi_arready generation
303
        // axi_arready is asserted for one S_AXI_ACLK clock cycle when
304
        // S_AXI_ARVALID is asserted. axi_awready is 
305
        // de-asserted when reset (active low) is asserted. 
306
        // The read address is also latched when S_AXI_ARVALID is 
307
        // asserted. axi_araddr is reset to zero on reset assertion.
308
 
309
        always @( posedge S_AXI_ACLK )
310
        begin
311
          if ( S_AXI_ARESETN == 1'b0 )
312
            begin
313
              axi_arready <= 1'b0;
314
              axi_araddr  <= 32'b0;
315
            end
316
          else
317
            begin
318
              if (~axi_arready && S_AXI_ARVALID)
319
                begin
320
                  // indicates that the slave has acceped the valid read address
321
                  axi_arready <= 1'b1;
322
                  // Read address latching
323
                  axi_araddr  <= S_AXI_ARADDR;
324
                end
325
              else
326
                begin
327
                  axi_arready <= 1'b0;
328
                end
329
            end
330
        end
331
 
332
        // Implement axi_arvalid generation
333
        // axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both 
334
        // S_AXI_ARVALID and axi_arready are asserted. The slave registers 
335
        // data are available on the axi_rdata bus at this instance. The 
336
        // assertion of axi_rvalid marks the validity of read data on the 
337
        // bus and axi_rresp indicates the status of read transaction.axi_rvalid 
338
        // is deasserted on reset (active low). axi_rresp and axi_rdata are 
339
        // cleared to zero on reset (active low).  
340
        always @( posedge S_AXI_ACLK )
341
        begin
342
          if ( S_AXI_ARESETN == 1'b0 )
343
            begin
344
              axi_rvalid <= 0;
345
              axi_rresp  <= 0;
346
            end
347
          else
348
            begin
349
              if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
350
                begin
351
                  // Valid read data is available at the read data bus
352
                  axi_rvalid <= 1'b1;
353
                  axi_rresp  <= 2'b0; // 'OKAY' response
354
                end
355
              else if (axi_rvalid && S_AXI_RREADY)
356
                begin
357
                  // Read data is accepted by the master
358
                  axi_rvalid <= 1'b0;
359
                end
360
            end
361
        end
362
 
363
        // Implement memory mapped register select and read logic generation
364
        // Slave register read enable is asserted when valid address is available
365
        // and the slave is ready to accept the read address.
366
        assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
367
        always @(*)
368
        begin
369
              // Address decoding for reading registers
370
              case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
371
                2'h0   : reg_data_out <= slv_reg0;
372
                2'h1   : reg_data_out <= slv_reg1;
373
                2'h2   : reg_data_out <= slv_reg2;
374
                2'h3   : reg_data_out <= slv_reg3;
375
                default : reg_data_out <= 0;
376
              endcase
377
        end
378
 
379
        // Output register or memory read data
380
        always @( posedge S_AXI_ACLK )
381
        begin
382
          if ( S_AXI_ARESETN == 1'b0 )
383
            begin
384
              axi_rdata  <= 0;
385
            end
386
          else
387
            begin
388
              // When there is a valid read address (S_AXI_ARVALID) with 
389
              // acceptance of read address by the slave (axi_arready), 
390
              // output the read dada 
391
              if (slv_reg_rden)
392
                begin
393
                  axi_rdata <= reg_data_out;     // register read data
394
                end
395
            end
396
        end
397
 
398
        // Add user logic here
399
 
400
        // User logic ends
401
 
402
        endmodule

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