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[/] [qspiflash/] [trunk/] [bench/] [cpp/] [eqspiflashsim.h] - Blame information for rev 12

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1 12 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    eqspiflashsim.h
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//
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// Project:     OpenArty, an entirely open SoC based upon the Arty platform
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//
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// Purpose:     This library simulates the operation of an Extended Quad-SPI
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//              commanded flash, such as the N25Q128A used on the Arty
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//              development board by Digilent.  As such, it is defined by
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//              16 MBytes of memory (4 MWords).
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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#ifndef EQSPIFLASHSIM_H
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#define EQSPIFLASHSIM_H
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#define EQSPIF_WIP_FLAG                 0x0001
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#define EQSPIF_WEL_FLAG                 0x0002
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#define EQSPIF_DEEP_POWER_DOWN_FLAG     0x0200
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class   EQSPIFLASHSIM {
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        typedef enum {
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                EQSPIF_IDLE,
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                EQSPIF_XIP,
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                EQSPIF_RDSR,
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                EQSPIF_RDCR,
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                EQSPIF_RDNVCONFIG,
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                EQSPIF_RDEVCONFIG,
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                EQSPIF_WRSR,
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                EQSPIF_WRCR,
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                EQSPIF_WRNVCONFIG,
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                EQSPIF_WREVCONFIG,
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                EQSPIF_RDFLAGS,
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                EQSPIF_CLRFLAGS,
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                EQSPIF_RDLOCK,
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                EQSPIF_WRLOCK,
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                EQSPIF_RDID,
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                EQSPIF_RELEASE,
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                EQSPIF_FAST_READ,
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                EQSPIF_QUAD_READ_CMD,
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                EQSPIF_QUAD_READ,
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                EQSPIF_PP,
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                EQSPIF_QPP,
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        // Erase states
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                EQSPIF_SUBSECTOR_ERASE,
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                EQSPIF_SECTOR_ERASE,
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                EQSPIF_BULK_ERASE,
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        // OTP memory
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                EQSPIF_PROGRAM_OTP,
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                EQSPIF_READ_OTP,
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        //
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                EQSPIF_INVALID
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        } EQSPIF_STATE;
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        EQSPIF_STATE    m_state;
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        char            *m_mem, *m_pmem, *m_otp, *m_lockregs;
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        int             m_last_sck;
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        unsigned        m_write_count, m_ireg, m_oreg, m_sreg, m_addr,
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                        m_count, m_config, m_mode_byte, m_creg,
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                        m_nvconfig, m_evconfig, m_flagreg, m_nxtout[4];
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        bool            m_quad_mode, m_debug, m_otp_wp;
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public:
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        EQSPIFLASHSIM(void);
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        void    load(const char *fname) { load(0, fname); }
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        void    load(const unsigned addr, const char *fname);
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        void    debug(const bool dbg) { m_debug = dbg; }
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        bool    debug(void) const { return m_debug; }
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        bool    write_enabled(void) const { return m_debug; }
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        unsigned counts_till_idle(void) const {
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                return m_write_count; }
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        unsigned operator[](const int index) {
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                unsigned char   *cptr = (unsigned char *)&m_mem[index<<2];
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                unsigned        v;
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                v = (*cptr++);
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                v = (v<<8)|(*cptr++);
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                v = (v<<8)|(*cptr++);
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                v = (v<<8)|(*cptr);
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                return v; }
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        void set(const unsigned addr, const unsigned val) {
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                unsigned char   *cptr = (unsigned char *)&m_mem[addr<<2];
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                *cptr++ = (val>>24);
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                *cptr++ = (val>>16);
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                *cptr++ = (val>> 8);
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                *cptr   = (val);
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                return;}
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        int     operator()(const int csn, const int sck, const int dat);
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};
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#endif

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