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[/] [qspiflash/] [trunk/] [bench/] [cpp/] [qspiflashsim.cpp] - Blame information for rev 16

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1 15 dgisselq
////////////////////////////////////////////////////////////////////////////////
2 3 dgisselq
//
3
//
4 15 dgisselq
// Filename:    qspiflashsim.cpp
5 3 dgisselq
//
6
// Project:     Wishbone Controlled Quad SPI Flash Controller
7
//
8
// Purpose:     This library simulates the operation of a Quad-SPI commanded
9
//              flash, such as the S25FL032P used on the Basys-3 development
10 15 dgisselq
//              board by Digilent.
11 3 dgisselq
//
12
//              This simulator is useful for testing in a Verilator/C++
13
//              environment, where this simulator can be used in place of
14
//              the actual hardware.
15
//
16 15 dgisselq
// Creator:     Dan Gisselquist, Ph.D.
17 8 dgisselq
//              Gisselquist Technology, LLC
18 3 dgisselq
//
19 15 dgisselq
////////////////////////////////////////////////////////////////////////////////
20 3 dgisselq
//
21 15 dgisselq
// Copyright (C) 2015,2017, Gisselquist Technology, LLC
22 3 dgisselq
//
23
// This program is free software (firmware): you can redistribute it and/or
24
// modify it under the terms of  the GNU General Public License as published
25
// by the Free Software Foundation, either version 3 of the License, or (at
26
// your option) any later version.
27
//
28
// This program is distributed in the hope that it will be useful, but WITHOUT
29
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
30
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
31
// for more details.
32
//
33
// You should have received a copy of the GNU General Public License along
34 15 dgisselq
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
35 3 dgisselq
// target there if the PDF file isn't present.)  If not, see
36
// <http://www.gnu.org/licenses/> for a copy.
37
//
38
// License:     GPL, v3, as defined and found on www.gnu.org,
39
//              http://www.gnu.org/licenses/gpl.html
40
//
41
//
42 15 dgisselq
////////////////////////////////////////////////////////////////////////////////
43
//
44
//
45 3 dgisselq
#include <stdio.h>
46
#include <string.h>
47
#include <assert.h>
48
#include <stdlib.h>
49 15 dgisselq
#include <stdint.h>
50 3 dgisselq
 
51
#include "qspiflashsim.h"
52
 
53
static  const unsigned  DEVID = 0x0115,
54
        DEVESD = 0x014,
55
        MICROSECONDS = 100,
56
        MILLISECONDS = MICROSECONDS * 1000,
57
        SECONDS = MILLISECONDS * 1000,
58
        tW     =   50 * MICROSECONDS, // write config cycle time
59
        tBE    =   32 * SECONDS,
60
        tDP    =   10 * SECONDS,
61
        tRES   =   30 * SECONDS,
62
// Shall we artificially speed up this process?
63
        tPP    = 12 * MICROSECONDS,
64
        tSE    = 15 * MILLISECONDS;
65
// or keep it at the original speed
66
        // tPP    = 1200 * MICROSECONDS,
67
        // tSE    = 1500 * MILLISECONDS;
68
 
69 15 dgisselq
QSPIFLASHSIM::QSPIFLASHSIM(const int lglen, bool debug) {
70
        m_membytes = (1<<lglen);
71
        m_memmask = (m_membytes - 1);
72
        m_mem = new char[m_membytes];
73 3 dgisselq
        m_pmem = new char[256];
74
        m_state = QSPIF_IDLE;
75
        m_last_sck = 1;
76
        m_write_count = 0;
77
        m_ireg = m_oreg = 0;
78
        m_sreg = 0x01c;
79
        m_creg = 0x001; // Iinitial creg on delivery
80
        m_quad_mode = false;
81
        m_mode_byte = 0;
82
 
83 15 dgisselq
        memset(m_mem, 0x0ff, m_membytes);
84 3 dgisselq
}
85
 
86 9 dgisselq
void    QSPIFLASHSIM::load(const unsigned addr, const char *fname) {
87 3 dgisselq
        FILE    *fp;
88 9 dgisselq
        size_t  len;
89 15 dgisselq
        int     nr = 0;
90 3 dgisselq
 
91 15 dgisselq
        if (addr >= m_membytes)
92 9 dgisselq
                return;
93 15 dgisselq
        // If not given, then length is from the given address until the end
94
        // of the flash memory
95
        len = m_membytes-addr*4;
96 9 dgisselq
 
97 3 dgisselq
        if (NULL != (fp = fopen(fname, "r"))) {
98 9 dgisselq
                nr = fread(&m_mem[addr], sizeof(char), len, fp);
99 3 dgisselq
                fclose(fp);
100 9 dgisselq
                if (nr == 0) {
101
                        fprintf(stderr, "SPI-FLASH: Could not read %s\n", fname);
102
                        perror("O/S Err:");
103
                }
104 3 dgisselq
        } else {
105
                fprintf(stderr, "SPI-FLASH: Could not open %s\n", fname);
106
                perror("O/S Err:");
107
        }
108 15 dgisselq
 
109
        for(unsigned i=nr; i<m_membytes; i++)
110
                m_mem[i] = 0x0ff;
111 3 dgisselq
}
112
 
113 15 dgisselq
void    QSPIFLASHSIM::load(const uint32_t offset, const char *data, const uint32_t len) {
114
        uint32_t        moff = (offset & (m_memmask));
115
 
116
        memcpy(&m_mem[moff], data, len);
117
}
118
 
119 3 dgisselq
#define QOREG(A)        m_oreg = ((m_oreg & (~0x0ff))|(A&0x0ff))
120
 
121
int     QSPIFLASHSIM::operator()(const int csn, const int sck, const int dat) {
122
        // Keep track of a timer to determine when page program and erase
123
        // cycles complete.
124
 
125
        if (m_write_count > 0) {
126
                if (0 == (--m_write_count)) {// When done with erase/page pgm,
127
                        m_sreg &= 0x0fc; // Clear the write in progress bit
128
                        if (m_debug) printf("Write complete, clearing WIP (inside SIM)\n");
129
                }
130
        }
131
 
132
        if (csn) {
133
                m_last_sck = 1;
134
                m_ireg = 0; m_oreg = 0;
135
                m_count= 0;
136
 
137
                if ((QSPIF_PP == m_state)||(QSPIF_QPP == m_state)) {
138
                        // Start a page program
139
                        if (m_debug) printf("QSPI: Page Program write cycle begins\n");
140
                        if (m_debug) printf("CK = %d & 7 = %d\n", m_count, m_count & 0x07);
141
                        if (m_debug) printf("QSPI: pmem = %08lx\n", (unsigned long)m_pmem);
142
                        m_write_count = tPP;
143
                        m_state = QSPIF_IDLE;
144
                        m_sreg &= (~QSPIF_WEL_FLAG);
145
                        m_sreg |= (QSPIF_WIP_FLAG);
146
                        for(int i=0; i<256; i++) {
147
                                /*
148
                                if (m_debug) printf("%02x: m_mem[%02x] = %02x &= %02x = %02x\n",
149
                                        i, (m_addr&(~0x0ff))+i,
150
                                        m_mem[(m_addr&(~0x0ff))+i]&0x0ff, m_pmem[i]&0x0ff,
151
                                        m_mem[(m_addr&(~0x0ff))+i]& m_pmem[i]&0x0ff);
152
                                */
153
                                m_mem[(m_addr&(~0x0ff))+i] &= m_pmem[i];
154
                        }
155
                        m_quad_mode = false;
156
                } else if (m_state == QSPIF_SECTOR_ERASE) {
157
                        if (m_debug) printf("Actually Erasing sector, from %08x\n", m_addr);
158
                        m_write_count = tSE;
159
                        m_state = QSPIF_IDLE;
160
                        m_sreg &= (~QSPIF_WEL_FLAG);
161
                        m_sreg |= (QSPIF_WIP_FLAG);
162
                        m_addr &= (-1<<16);
163
                        for(int i=0; i<(1<<16); i++)
164
                                m_mem[m_addr + i] = 0x0ff;
165
                        if (m_debug) printf("Now waiting %d ticks delay\n", m_write_count);
166
                } else if (QSPIF_WRSR == m_state) {
167
                        if (m_debug) printf("Actually writing status register\n");
168
                        m_write_count = tW;
169
                        m_state = QSPIF_IDLE;
170
                        m_sreg &= (~QSPIF_WEL_FLAG);
171
                        m_sreg |= (QSPIF_WIP_FLAG);
172
                } else if (QSPIF_CLSR == m_state) {
173
                        if (m_debug) printf("Actually clearing the status register bits\n");
174
                        m_state = QSPIF_IDLE;
175
                        m_sreg &= 0x09f;
176
                } else if (m_state == QSPIF_BULK_ERASE) {
177
                        m_write_count = tBE;
178
                        m_state = QSPIF_IDLE;
179
                        m_sreg &= (~QSPIF_WEL_FLAG);
180
                        m_sreg |= (QSPIF_WIP_FLAG);
181 15 dgisselq
                        for(unsigned i=0; i<m_membytes; i++)
182 3 dgisselq
                                m_mem[i] = 0x0ff;
183
                } else if (m_state == QSPIF_DEEP_POWER_DOWN) {
184
                        m_write_count = tDP;
185
                        m_state = QSPIF_IDLE;
186
                } else if (m_state == QSPIF_RELEASE) {
187
                        m_write_count = tRES;
188
                        m_state = QSPIF_IDLE;
189
                } else if (m_state == QSPIF_QUAD_READ_CMD) {
190
                        if ((m_mode_byte & 0x0f0)!=0x0a0)
191
                                m_quad_mode = false;
192
                        else
193
                                m_state = QSPIF_QUAD_READ_IDLE;
194
                } else if (m_state == QSPIF_QUAD_READ) {
195
                        if ((m_mode_byte & 0x0f0)!=0x0a0)
196
                                m_quad_mode = false;
197
                        else
198
                                m_state = QSPIF_QUAD_READ_IDLE;
199
                } else if (m_state == QSPIF_QUAD_READ_IDLE) {
200
                }
201
 
202
                m_oreg = 0x0fe;
203
                return dat;
204
        } else if ((!m_last_sck)||(sck == m_last_sck)) {
205
                // Only change on the falling clock edge
206
                // printf("SFLASH-SKIP, CLK=%d -> %d\n", m_last_sck, sck);
207
                m_last_sck = sck;
208
                if (m_quad_mode)
209
                        return (m_oreg>>8)&0x0f;
210
                else
211
                        // return ((m_oreg & 0x0100)?2:0) | (dat & 0x0d);
212
                        return (m_oreg & 0x0100)?2:0;
213
        }
214
 
215
        // We'll only get here if ...
216
        //      last_sck = 1, and sck = 0, thus transitioning on the
217
        //      negative edge as with everything else in this interface
218
        if (m_quad_mode) {
219
                m_ireg = (m_ireg << 4) | (dat & 0x0f);
220
                m_count+=4;
221
                m_oreg <<= 4;
222
        } else {
223
                m_ireg = (m_ireg << 1) | (dat & 1);
224
                m_count++;
225
                m_oreg <<= 1;
226
        }
227
 
228
 
229
        // printf("PROCESS, COUNT = %d, IREG = %02x\n", m_count, m_ireg);
230
        if (m_state == QSPIF_QUAD_READ_IDLE) {
231
                assert(m_quad_mode);
232
                if (m_count == 24) {
233
                        if (m_debug) printf("QSPI: Entering from Quad-Read Idle to Quad-Read\n");
234 4 dgisselq
                        if (m_debug) printf("QSPI: QI/O Idle Addr = %02x\n", m_ireg&0x0ffffff);
235 15 dgisselq
                        m_addr = (m_ireg) & m_memmask;
236
                        assert((m_addr & (~(m_memmask)))==0);
237 3 dgisselq
                        m_state = QSPIF_QUAD_READ;
238
                } m_oreg = 0;
239
        } else if (m_count == 8) {
240
                QOREG(0x0a5);
241
                // Figure out what command we've been given
242
                if (m_debug) printf("SPI FLASH CMD %02x\n", m_ireg&0x0ff);
243
                switch(m_ireg & 0x0ff) {
244
                case 0x01: // Write status register
245
                        if (2 !=(m_sreg & 0x203)) {
246
                                if (m_debug) printf("QSPI: WEL not set, cannot write status reg\n");
247
                                m_state = QSPIF_INVALID;
248
                        } else
249
                                m_state = QSPIF_WRSR;
250
                        break;
251
                case 0x02: // Page program
252
                        if (2 != (m_sreg & 0x203)) {
253
                                if (m_debug) printf("QSPI: Cannot program at this time, SREG = %x\n", m_sreg);
254
                                m_state = QSPIF_INVALID;
255
                        } else {
256
                                m_state = QSPIF_PP;
257
                                if (m_debug) printf("PAGE-PROGRAM COMMAND ACCEPTED\n");
258
                        }
259
                        break;
260
                case 0x03: // Read data bytes
261
                        // Our clock won't support this command, so go
262
                        // to an invalid state
263
                        if (m_debug) printf("QSPI INVALID: This sim does not support slow reading\n");
264
                        m_state = QSPIF_INVALID;
265
                        break;
266
                case 0x04: // Write disable
267
                        m_state = QSPIF_IDLE;
268
                        m_sreg &= (~QSPIF_WEL_FLAG);
269
                        break;
270
                case 0x05: // Read status register
271
                        m_state = QSPIF_RDSR;
272
                        if (m_debug) printf("QSPI: READING STATUS REGISTER: %02x\n", m_sreg);
273
                        QOREG(m_sreg);
274
                        break;
275
                case 0x06: // Write enable
276
                        m_state = QSPIF_IDLE;
277
                        m_sreg |= QSPIF_WEL_FLAG;
278
                        if (m_debug) printf("QSPI: WRITE-ENABLE COMMAND ACCEPTED\n");
279
                        break;
280
                case 0x0b: // Here's the read that we support
281
                        if (m_debug) printf("QSPI: FAST-READ (single-bit)\n");
282
                        m_state = QSPIF_FAST_READ;
283
                        break;
284
                case 0x30:
285
                        if (m_debug) printf("QSPI: CLEAR STATUS REGISTER COMMAND\n");
286
                        m_state = QSPIF_CLSR;
287
                        break;
288
                case 0x32: // QUAD Page program, 4 bits at a time
289
                        if (2 != (m_sreg & 0x203)) {
290
                                if (m_debug) printf("QSPI: Cannot program at this time, SREG = %x\n", m_sreg);
291
                                m_state = QSPIF_INVALID;
292
                        } else {
293
                                m_state = QSPIF_QPP;
294
                                if (m_debug) printf("QSPI: QUAD-PAGE-PROGRAM COMMAND ACCEPTED\n");
295
                                if (m_debug) printf("QSPI: pmem = %08lx\n", (unsigned long)m_pmem);
296
                        }
297
                        break;
298
                case 0x35: // Read configuration register
299
                        m_state = QSPIF_RDCR;
300
                        if (m_debug) printf("QSPI: READING CONFIGURATION REGISTER: %02x\n", m_creg);
301
                        QOREG(m_creg);
302
                        break;
303
                case 0x9f: // Read ID
304
                        m_state = QSPIF_RDID;
305
                        if (m_debug) printf("QSPI: READING ID, %02x\n", (DEVID>>24)&0x0ff);
306
                        QOREG(0xfe);
307
                        break;
308
                case 0xab: // Release from DEEP POWER DOWN
309
                        if (m_sreg & QSPIF_DEEP_POWER_DOWN_FLAG) {
310
                                if (m_debug) printf("QSPI: Release from deep power down\n");
311
                                m_sreg &= (~QSPIF_DEEP_POWER_DOWN_FLAG);
312
                                m_write_count = tRES;
313
                        } m_state = QSPIF_RELEASE;
314
                        break;
315
                case 0xb9: // DEEP POWER DOWN
316
                        if (0 != (m_sreg & 0x01)) {
317
                                if (m_debug) printf("QSPI: Cannot enter DEEP POWER DOWN, in middle of write/erase\n");
318
                                m_state = QSPIF_INVALID;
319
                        } else {
320
                                m_sreg  |= QSPIF_DEEP_POWER_DOWN_FLAG;
321
                                m_state  = QSPIF_IDLE;
322
                        }
323
                        break;
324
                case 0xc7: // Bulk Erase
325
                        if (2 != (m_sreg & 0x203)) {
326
                                if (m_debug) printf("QSPI: WEL not set, cannot erase device\n");
327
                                m_state = QSPIF_INVALID;
328
                        } else
329
                                m_state = QSPIF_BULK_ERASE;
330
                        break;
331
                case 0xd8: // Sector Erase
332
                        if (2 != (m_sreg & 0x203)) {
333
                                if (m_debug) printf("QSPI: WEL not set, cannot erase sector\n");
334
                                m_state = QSPIF_INVALID;
335
                        } else {
336
                                m_state = QSPIF_SECTOR_ERASE;
337
                                if (m_debug) printf("QSPI: SECTOR_ERASE COMMAND\n");
338
                        }
339
                        break;
340
                case 0x0eb: // Here's the (other) read that we support
341
                        // printf("QSPI: QUAD-I/O-READ\n");
342
                        m_state = QSPIF_QUAD_READ_CMD;
343
                        m_quad_mode = true;
344
                        break;
345
                default:
346
                        printf("QSPI: UNRECOGNIZED SPI FLASH CMD: %02x\n", m_ireg&0x0ff);
347
                        m_state = QSPIF_INVALID;
348
                        assert(0 && "Unrecognized command\n");
349
                        break;
350
                }
351
        } else if ((0 == (m_count&0x07))&&(m_count != 0)) {
352
                QOREG(0);
353
                switch(m_state) {
354
                case QSPIF_IDLE:
355
                        printf("TOO MANY CLOCKS, SPIF in IDLE\n");
356
                        break;
357
                case QSPIF_WRSR:
358
                        if (m_count == 16) {
359
                                m_sreg = (m_sreg & 0x061) | (m_ireg & 0x09c);
360
                                if (m_debug) printf("Request to set sreg to 0x%02x\n",
361
                                        m_ireg&0x0ff);
362
                        } else if (m_count == 24) {
363
                                m_creg = (m_creg & 0x0fd) | (m_ireg & 0x02);
364
                                if (m_debug) printf("Request to set creg to 0x%02x\n",
365
                                        m_ireg&0x0ff);
366
                        } else {
367
                                printf("TOO MANY CLOCKS FOR WRR!!!\n");
368
                                exit(-2);
369
                                m_state = QSPIF_IDLE;
370
                        }
371
                        break;
372
                case QSPIF_CLSR:
373
                        assert(0 && "Too many clocks for CLSR command!!\n");
374
                        break;
375
                case QSPIF_RDID:
376
                        if (m_count == 32) {
377 15 dgisselq
                                m_addr = m_ireg & m_memmask;
378 3 dgisselq
                                if (m_debug) printf("READID, ADDR = %08x\n", m_addr);
379
                                QOREG((DEVID>>8));
380
                                if (m_debug) printf("QSPI: READING ID, %02x\n", (DEVID>>8)&0x0ff);
381
                        } else if (m_count > 32) {
382
                                if (((m_count-32)>>3)&1)
383
                                        QOREG((DEVID));
384
                                else
385
                                        QOREG((DEVID>>8));
386
                                if (m_debug) printf("QSPI: READING ID, %02x -- DONE\n", 0x00);
387
                        }
388
                        // m_oreg = (DEVID >> (2-(m_count>>3)-1)) & 0x0ff;
389
                        break;
390
                case QSPIF_RDSR:
391
                        // printf("Read SREG = %02x, wait = %08x\n", m_sreg,
392
                                // m_write_count);
393
                        QOREG(m_sreg);
394
                        break;
395
                case QSPIF_RDCR:
396
                        if (m_debug) printf("Read CREG = %02x\n", m_creg);
397
                        QOREG(m_creg);
398
                        break;
399
                case QSPIF_FAST_READ:
400
                        if (m_count == 32) {
401 15 dgisselq
                                m_addr = m_ireg & m_memmask;
402 3 dgisselq
                                if (m_debug) printf("FAST READ, ADDR = %08x\n", m_addr);
403
                                QOREG(0x0c3);
404 15 dgisselq
                                assert((m_addr & (~(m_memmask)))==0);
405 3 dgisselq
                        } else if ((m_count >= 40)&&(0 == (m_sreg&0x01))) {
406 9 dgisselq
                                //if (m_count == 40)
407
                                        //printf("DUMMY BYTE COMPLETE ...\n");
408 3 dgisselq
                                QOREG(m_mem[m_addr++]);
409
                                // if (m_debug) printf("SPIF[%08x] = %02x\n", m_addr-1, m_oreg);
410
                        } else m_oreg = 0;
411
                        break;
412
                case QSPIF_QUAD_READ_CMD:
413
                        // The command to go into quad read mode took 8 bits
414
                        // that changes the timings, else we'd use quad_Read
415
                        // below
416
                        if (m_count == 32) {
417 15 dgisselq
                                m_addr = m_ireg & m_memmask;
418 3 dgisselq
                                // printf("FAST READ, ADDR = %08x\n", m_addr);
419
                                // printf("QSPI: QUAD READ, ADDR = %06x\n", m_addr);
420 15 dgisselq
                                assert((m_addr & (~(m_memmask)))==0);
421 3 dgisselq
                        } else if (m_count == 32+24) {
422
                                m_mode_byte = (m_ireg>>16) & 0x0ff;
423
                                // printf("QSPI: MODE BYTE = %02x\n", m_mode_byte);
424
                        } else if ((m_count > 32+24)&&(0 == (m_sreg&0x01))) {
425
                                QOREG(m_mem[m_addr++]);
426
                                // printf("QSPIF[%08x]/QR = %02x\n",
427
                                        // m_addr-1, m_oreg);
428
                        } else m_oreg = 0;
429
                        break;
430
                case QSPIF_QUAD_READ:
431
                        if (m_count == 32) {
432
                                m_mode_byte = (m_ireg & 0x0ff);
433
                                // printf("QSPI/QR: MODE BYTE = %02x\n", m_mode_byte);
434
                        } else if ((m_count >= 32+16)&&(0 == (m_sreg&0x01))) {
435
                                QOREG(m_mem[m_addr++]);
436 4 dgisselq
                                // printf("QSPIF[%08x]/QR = %02x\n", m_addr-1, m_oreg & 0x0ff);
437 3 dgisselq
                        } else m_oreg = 0;
438
                        break;
439
                case QSPIF_PP:
440
                        if (m_count == 32) {
441 15 dgisselq
                                m_addr = m_ireg & m_memmask;
442 3 dgisselq
                                if (m_debug) printf("QSPI: PAGE-PROGRAM ADDR = %06x\n", m_addr);
443 15 dgisselq
                                assert((m_addr & (~(m_memmask)))==0);
444 3 dgisselq
                                // m_page = m_addr >> 8;
445
                                for(int i=0; i<256; i++)
446
                                        m_pmem[i] = 0x0ff;
447
                        } else if (m_count >= 40) {
448
                                m_pmem[m_addr & 0x0ff] = m_ireg & 0x0ff;
449
                                // printf("QSPI: PMEM[%02x] = 0x%02x -> %02x\n", m_addr & 0x0ff, m_ireg & 0x0ff, (m_pmem[(m_addr & 0x0ff)]&0x0ff));
450
                                m_addr = (m_addr & (~0x0ff)) | ((m_addr+1)&0x0ff);
451
                        } break;
452
                case QSPIF_QPP:
453
                        if (m_count == 32) {
454 15 dgisselq
                                m_addr = m_ireg & m_memmask;
455 3 dgisselq
                                m_quad_mode = true;
456
                                if (m_debug) printf("QSPI/QR: PAGE-PROGRAM ADDR = %06x\n", m_addr);
457 15 dgisselq
                                assert((m_addr & (~(m_memmask)))==0);
458 3 dgisselq
                                // m_page = m_addr >> 8;
459
                                for(int i=0; i<256; i++)
460
                                        m_pmem[i] = 0x0ff;
461
                        } else if (m_count >= 40) {
462
                                m_pmem[m_addr & 0x0ff] = m_ireg & 0x0ff;
463
                                // printf("QSPI/QR: PMEM[%02x] = 0x%02x -> %02x\n", m_addr & 0x0ff, m_ireg & 0x0ff, (m_pmem[(m_addr & 0x0ff)]&0x0ff));
464
                                m_addr = (m_addr & (~0x0ff)) | ((m_addr+1)&0x0ff);
465
                        } break;
466
                case QSPIF_SECTOR_ERASE:
467
                        if (m_count == 32) {
468
                                m_addr = m_ireg & 0x0ffc000;
469
                                if (m_debug) printf("SECTOR_ERASE ADDRESS = %08x\n", m_addr);
470
                                assert((m_addr & 0xfc00000)==0);
471
                        } break;
472
                case QSPIF_RELEASE:
473
                        if (m_count >= 32) {
474
                                QOREG(DEVESD);
475
                        } break;
476
                default:
477
                        break;
478
                }
479
        } // else printf("SFLASH->count = %d\n", m_count);
480
 
481
        m_last_sck = sck;
482
        if (m_quad_mode)
483
                return (m_oreg>>8)&0x0f;
484
        else
485
                // return ((m_oreg & 0x0100)?2:0) | (dat & 0x0d);
486
                return (m_oreg & 0x0100)?2:0;
487
}
488
 

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