OpenCores
URL https://opencores.org/ocsvn/qspiflash/qspiflash/trunk

Subversion Repositories qspiflash

[/] [qspiflash/] [trunk/] [bench/] [cpp/] [qspiflashsim.h] - Blame information for rev 16

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 dgisselq
////////////////////////////////////////////////////////////////////////////////
2 3 dgisselq
//
3 15 dgisselq
// Filename:    qspiflashsim.h
4 3 dgisselq
//
5
// Project:     Wishbone Controlled Quad SPI Flash Controller
6
//
7
// Purpose:     This library simulates the operation of a Quad-SPI commanded
8
//              flash, such as the S25FL032P used on the Basys-3 development
9
//              board by Digilent.  As such, it is defined by 32 Mbits of
10
//              memory (4 Mbyte).
11
//
12 15 dgisselq
// Creator:     Dan Gisselquist, Ph.D.
13 8 dgisselq
//              Gisselquist Technology, LLC
14 3 dgisselq
//
15 15 dgisselq
////////////////////////////////////////////////////////////////////////////////
16 3 dgisselq
//
17 15 dgisselq
// Copyright (C) 2015,2017, Gisselquist Technology, LLC
18 3 dgisselq
//
19
// This program is free software (firmware): you can redistribute it and/or
20
// modify it under the terms of  the GNU General Public License as published
21
// by the Free Software Foundation, either version 3 of the License, or (at
22
// your option) any later version.
23
//
24
// This program is distributed in the hope that it will be useful, but WITHOUT
25
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
26
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
27
// for more details.
28
//
29
// You should have received a copy of the GNU General Public License along
30 15 dgisselq
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
31 3 dgisselq
// target there if the PDF file isn't present.)  If not, see
32
// <http://www.gnu.org/licenses/> for a copy.
33
//
34
// License:     GPL, v3, as defined and found on www.gnu.org,
35
//              http://www.gnu.org/licenses/gpl.html
36
//
37
//
38 15 dgisselq
////////////////////////////////////////////////////////////////////////////////
39
//
40
//
41 3 dgisselq
#ifndef QSPIFLASHSIM_H
42
#define QSPIFLASHSIM_H
43
 
44
#define QSPIF_WIP_FLAG                  0x0001
45
#define QSPIF_WEL_FLAG                  0x0002
46
#define QSPIF_DEEP_POWER_DOWN_FLAG      0x0200
47
class   QSPIFLASHSIM {
48
        typedef enum {
49
                QSPIF_IDLE,
50
                QSPIF_QUAD_READ_IDLE,
51
                QSPIF_RDSR,
52
                QSPIF_RDCR,
53
                QSPIF_WRSR,
54
                QSPIF_CLSR,
55
                QSPIF_RDID,
56
                QSPIF_RELEASE,
57
                QSPIF_FAST_READ,
58
                QSPIF_QUAD_READ_CMD,
59
                QSPIF_QUAD_READ,
60
                QSPIF_SECTOR_ERASE,
61
                QSPIF_PP,
62
                QSPIF_QPP,
63
                QSPIF_BULK_ERASE,
64
                QSPIF_DEEP_POWER_DOWN,
65
                QSPIF_INVALID
66
        } QSPIF_STATE;
67
 
68
        QSPIF_STATE     m_state;
69
        char            *m_mem, *m_pmem;
70
        int             m_last_sck;
71
        unsigned        m_write_count, m_ireg, m_oreg, m_sreg, m_addr,
72 15 dgisselq
                        m_count, m_config, m_mode_byte, m_creg, m_membytes,
73
                        m_memmask;
74 3 dgisselq
        bool            m_quad_mode, m_debug;
75
 
76
public:
77 15 dgisselq
        QSPIFLASHSIM(const int lglen = 24, bool debug = false);
78 9 dgisselq
        void    load(const char *fname) { load(0, fname); }
79
        void    load(const unsigned addr, const char *fname);
80 15 dgisselq
        void    load(const uint32_t offset, const char *data, const uint32_t len);
81 16 dgisselq
        bool    write_protect(void) { return ((m_sreg & QSPIF_WEL_FLAG)==0); }
82
        bool    write_in_progress(void) { return ((m_sreg | QSPIF_WIP_FLAG)!=0); }
83
        bool    xip_mode(void) { return (QSPIF_QUAD_READ_IDLE == m_state); }
84
        bool    quad_mode(void) { return m_quad_mode; }
85 3 dgisselq
        void    debug(const bool dbg) { m_debug = dbg; }
86
        bool    debug(void) const { return m_debug; }
87 15 dgisselq
        unsigned operator[](const int index) {
88 16 dgisselq
                unsigned char   *cptr = (unsigned char *)&m_mem[index];
89 15 dgisselq
                unsigned        v;
90
                v = (*cptr++);
91
                v = (v<<8)|(*cptr++);
92
                v = (v<<8)|(*cptr++);
93
                v = (v<<8)|(*cptr);
94
 
95
                return v; }
96
        void set(const unsigned addr, const unsigned val) {
97 16 dgisselq
                unsigned char   *cptr = (unsigned char *)&m_mem[addr];
98 15 dgisselq
                *cptr++ = (val>>24);
99
                *cptr++ = (val>>16);
100
                *cptr++ = (val>> 8);
101
                *cptr   = (val);
102
                return;}
103 3 dgisselq
        int     operator()(const int csn, const int sck, const int dat);
104
};
105
 
106
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.