OpenCores
URL https://opencores.org/ocsvn/qspiflash/qspiflash/trunk

Subversion Repositories qspiflash

[/] [qspiflash/] [trunk/] [bench/] [cpp/] [testb.h] - Blame information for rev 23

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 16 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    testb.h
4
//
5 23 dgisselq
// Project:     A Set of Wishbone Controlled SPI Flash Controllers
6 16 dgisselq
//
7
// Purpose:     A wrapper for a common interface to a clocked FPGA core
8
//              begin exercised in Verilator.
9
//
10
// Creator:     Dan Gisselquist, Ph.D.
11
//              Gisselquist Technology, LLC
12
//
13
////////////////////////////////////////////////////////////////////////////////
14
//
15 23 dgisselq
// Copyright (C) 2015,2017-2018, Gisselquist Technology, LLC
16 16 dgisselq
//
17 23 dgisselq
// This file is part of the set of Wishbone controlled SPI flash controllers
18
// project
19 16 dgisselq
//
20 23 dgisselq
// The Wishbone SPI flash controller project is free software (firmware):
21
// you can redistribute it and/or modify it under the terms of the GNU Lesser
22
// General Public License as published by the Free Software Foundation, either
23
// version 3 of the License, or (at your option) any later version.
24 16 dgisselq
//
25 23 dgisselq
// The Wishbone SPI flash controller project is distributed in the hope
26
// that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
27
// warranty of MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
28
// GNU Lesser General Public License for more details.
29
//
30
// You should have received a copy of the GNU Lesser General Public License
31
// along with this program.  (It's in the $(ROOT)/doc directory.  Run make
32
// with no target there if the PDF file isn't present.)  If not, see
33 16 dgisselq
// <http://www.gnu.org/licenses/> for a copy.
34
//
35 23 dgisselq
// License:     LGPL, v3, as defined and found on www.gnu.org,
36
//              http://www.gnu.org/licenses/lgpl.html
37 16 dgisselq
//
38
//
39
////////////////////////////////////////////////////////////////////////////////
40
//
41
//
42
#ifndef TESTB_H
43
#define TESTB_H
44
 
45
#include <stdio.h>
46
#include <stdint.h>
47
#include <verilated_vcd_c.h>
48
 
49
#define TBASSERT(TB,A) do { if (!(A)) { (TB).closetrace(); } assert(A); } while(0);
50
 
51
template <class VA>     class TESTB {
52
public:
53
        VA      *m_core;
54
        VerilatedVcdC*  m_trace;
55
        unsigned long   m_tickcount;
56
 
57
        TESTB(void) : m_trace(NULL), m_tickcount(0l) {
58
                m_core = new VA;
59
                Verilated::traceEverOn(true);
60
                m_core->i_clk = 0;
61
                eval(); // Get our initial values set properly.
62
        }
63
        virtual ~TESTB(void) {
64
                if (m_trace) m_trace->close();
65
                delete m_core;
66
                m_core = NULL;
67
        }
68
 
69
        virtual void    opentrace(const char *vcdname) {
70
                if (!m_trace) {
71
                        m_trace = new VerilatedVcdC;
72
                        m_core->trace(m_trace, 99);
73
                        m_trace->open(vcdname);
74
                }
75
        }
76
 
77
        virtual void    closetrace(void) {
78
                if (m_trace) {
79
                        m_trace->close();
80
                        m_trace = NULL;
81
                }
82
        }
83
 
84
        virtual void    eval(void) {
85
                m_core->eval();
86
        }
87
 
88
        virtual void    tick(void) {
89
                m_tickcount++;
90
 
91
                // Make sure we have our evaluations straight before the top
92
                // of the clock.  This is necessary since some of the 
93
                // connection modules may have made changes, for which some
94
                // logic depends.  This forces that logic to be recalculated
95
                // before the top of the clock.
96
                eval();
97
                if (m_trace) m_trace->dump(10*m_tickcount-2);
98
                m_core->i_clk = 1;
99
                eval();
100
                if (m_trace) m_trace->dump(10*m_tickcount);
101
                m_core->i_clk = 0;
102
                eval();
103
                if (m_trace) {
104
                        m_trace->dump(10*m_tickcount+5);
105
                        m_trace->flush();
106
                }
107
        }
108
 
109
        virtual void    reset(void) {
110
        }
111
};
112
 
113
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.