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[/] [qspiflash/] [trunk/] [rtl/] [eqspiflash.v] - Blame information for rev 11

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1 9 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    eqspiflash.v
4
//
5
// Project:     OpenArty, an entirely open SoC based upon the Arty platform
6
//
7
// Purpose:     Provide access to the flash device on an Arty, via the Extended
8
//              SPI interface.  Reads and writes will use the QuadSPI interface
9
//      (4-bits at a time) all other commands (register and otherwise) will use
10
//      the SPI interface (1 bit at a time).
11
//
12
// Registers:
13
//      0. Erase register control.  Provides status of pending writes, erases,
14
//              and commands (sub)sector erase operations.
15
//         Bit-Fields:
16
//              31. WIP (Write-In-Progress), write a '1' to this bit to command
17
//                      an erase sequence.
18
//              30. WriteEnabled -- set to a '1' to disable write protection and
19
//                      to write a WRITE-ENABLE to the device.  Set to a '0' to
20
//                      disable WRITE-ENABLE-LATCH.  (Key is required to enable
21
//                      writes)
22
//              29. Quad mode read/writes enabled.  (Rest of controller will use
23
//                      extended SPI mode, but reads and writes will use Quad
24
//                      mode.)
25
//              28. Subsector erase bit (set 1 to erase a subsector, 0 to 
26
//                      erase a full sector, maintains last value written from
27
//                      an erase command, starts at '0')
28
//              27. SD ID loaded
29
//              26. Write protect violation--cleared upon any valid write
30
//              25. XIP enabled.  (Leave read mode in XIP, so you can start
31
//                      next read faster.)
32
//              24. Unused
33
//              23..0: Address of erase sector upon erase command
34
//              23..14: Sector address (can only be changed w/ key)
35
//              23..10: Subsector address (can only be changed w/ key)
36
//               9.. 0: write protect KEY bits, always read a '0', write
37
//                      commands, such as WP disable or erase, must always
38
//                      write with a '1be' to activate.
39
//      0. WEL: All writes that do not command an erase will be used
40
//                      to set/clear the write enable latch.
41
//                      Send 0x06, return, if WP is clear (enable writes)
42
//                      Send 0x04, return
43
//      1. STATUS
44
//              Send 0x05, read  1-byte
45
//              Send 0x01, write 1-byte: i_wb_data[7:0]
46
//      2. NV-CONFIG (16-bits)
47
//              Send 0xB5, read  2-bytes
48
//              Send 0xB1, write 2-bytes: i_wb_data[15:0]
49
//      3. V-CONFIG (8-bits)
50
//              Send 0x85, read  1-byte
51
//              Send 0x81, write 1-byte: i_wb_data[7:0]
52
//      4. EV-CONFIG (8-bits)
53
//              Send 0x65, read  1-byte
54
//              Send 0x61, write 1-byte: i_wb_data[7:0]
55
//      5. Lock (send 32-bits, rx 1 byte)
56
//              Send 0xE8, last-sector-addr (3b), read  1-byte
57
//              Send 0xE5, last-sector-addr (3b), write 1-byte: i_wb_data[7:0]
58
//      6. Flag Status
59
//              Send 0x70, read  1-byte
60
//              Send 0x50, to clear, no bytes to write
61
//      7. Asynch Read-ID: Write here to cause controller to read ID into buffer
62
//      8.-12.  ID buffer (20 bytes, 5 words)
63
//              Attempted reads before buffer is full will stall bus until 
64
//              buffer is read.  Writes act like the asynch-Read-ID command,
65
//              and will cause the controller to read the buffer.
66
//      13.-14. Unused, mapped to Asynch-read-ID
67
//      15.     OTP control word
68
//                      Write zero to permanently lock OTP
69
//                      Read to determine if OTP is permanently locked
70
//      16.-31. OTP (64-bytes, 16 words, buffered until write)
71
//              (Send DWP before writing to clear write enable latch)
72
//
73
//
74
// Creator:     Dan Gisselquist, Ph.D.
75
//              Gisselquist Technology, LLC
76
//
77
////////////////////////////////////////////////////////////////////////////////
78
//
79
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
80
//
81
// This program is free software (firmware): you can redistribute it and/or
82
// modify it under the terms of  the GNU General Public License as published
83
// by the Free Software Foundation, either version 3 of the License, or (at
84
// your option) any later version.
85
//
86
// This program is distributed in the hope that it will be useful, but WITHOUT
87
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
88
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
89
// for more details.
90
//
91
// You should have received a copy of the GNU General Public License along
92
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
93
// target there if the PDF file isn't present.)  If not, see
94
// <http://www.gnu.org/licenses/> for a copy.
95
//
96
// License:     GPL, v3, as defined and found on www.gnu.org,
97
//              http://www.gnu.org/licenses/gpl.html
98
//
99
//
100
////////////////////////////////////////////////////////////////////////////////
101
//
102
//
103
// `define      QSPI_READ_ONLY
104
module  eqspiflash(i_clk_200mhz, i_rst,
105
                // Incoming wishbone connection(s)
106
                //      The two strobe lines allow the data to live on a
107
                //      separate part of the master bus from the control 
108
                //      registers.  Only one strobe will ever be active at any
109
                //      time, no strobes will ever be active unless i_wb_cyc
110
                //      is also active.
111
                i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,
112
                i_wb_addr, i_wb_data,
113
                // Outgoing wishbone data
114
                o_wb_ack, o_wb_stall, o_wb_data,
115
                // Quad SPI connections
116
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
117
                // Interrupt the CPU
118
                o_interrupt, o_cmd_accepted,
119
                // Debug the interface
120
                o_dbg);
121
 
122
        input                   i_clk_200mhz, i_rst;
123
        // Wishbone bus inputs
124
        input                   i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
125
        input           [21:0]   i_wb_addr;      // 24 bits of addr space
126
        input           [31:0]   i_wb_data;
127
        // Wishbone bus outputs
128
        output  reg             o_wb_ack;
129
        output  wire            o_wb_stall;
130
        output  reg     [31:0]   o_wb_data;
131
        // Quad SPI connections
132
        output  wire            o_qspi_sck, o_qspi_cs_n;
133
        output  wire    [1:0]    o_qspi_mod;
134
        output  wire    [3:0]    o_qspi_dat;
135
        input   wire    [3:0]    i_qspi_dat;
136
        //
137
        output  reg             o_interrupt;
138
        //
139
        output  reg             o_cmd_accepted;
140
        //
141
        output  wire    [31:0]   o_dbg;
142
 
143
        initial o_cmd_accepted = 1'b0;
144
        always @(posedge i_clk_200mhz)
145
                o_cmd_accepted=((i_wb_data_stb)||(i_wb_ctrl_stb))&&(~o_wb_stall);
146
        //
147 10 dgisselq
        // lleqspi
148 9 dgisselq
        //
149
        //      Providing the low-level SPI interface
150
        //
151
        reg     spi_wr, spi_hold, spi_spd, spi_dir, spi_recycle;
152
        reg     [31:0]   spi_word;
153
        reg     [1:0]    spi_len;
154
        wire    [31:0]   spi_out;
155
        wire            spi_valid, spi_busy, spi_stopped;
156 10 dgisselq
        lleqspi lowlvl(i_clk_200mhz, spi_wr, spi_hold, spi_word, spi_len,
157 9 dgisselq
                        spi_spd, spi_dir, spi_recycle, spi_out, spi_valid, spi_busy,
158
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat);
159
        assign  spi_stopped = (o_qspi_cs_n)&&(~spi_busy)&&(~spi_wr);
160
 
161
 
162
        //
163
        // Bus module
164
        //
165
        //      Providing a shared interface to the WB bus
166
        //
167
        // Wishbone data (returns)
168
        wire            bus_wb_ack, bus_wb_stall;
169
        wire    [31:0]   bus_wb_data;
170
        // Latched request data
171
        wire            bus_wr;
172
        wire    [21:0]   bus_addr;
173
        wire    [31:0]   bus_data;
174
        wire    [21:0]   bus_sector;
175
        // Strobe commands
176
        wire    bus_ack;
177
        wire    bus_readreq, bus_piperd, bus_ereq, bus_wreq,
178
                        bus_pipewr, bus_endwr, bus_ctreq, bus_idreq,
179
                        bus_other_req,
180
        // Live parameters
181
                        w_xip, w_quad, w_idloaded;
182
        reg             bus_wip;
183
        qspibus preproc(i_clk_200mhz, i_rst,
184
                        i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb,
185
                                i_wb_we, i_wb_addr, i_wb_data,
186
                                bus_wb_ack, bus_wb_stall, bus_wb_data,
187
                        bus_wr, bus_addr, bus_data, bus_sector,
188
                                bus_readreq, bus_piperd,
189
                                        bus_wreq, bus_ereq,
190
                                        bus_pipewr, bus_endwr,
191
                                bus_ctreq, bus_idreq, bus_other_req, bus_ack,
192
                        w_xip, w_quad, w_idloaded, bus_wip, spi_stopped);
193
 
194
        //
195
        // Read flash module
196
        //
197
        //      Providing a means of (and the logic to support) reading from
198
        //      the flash
199
        //
200
        wire            rd_data_ack;
201
        wire    [31:0]   rd_data;
202
        //
203
        wire            rd_bus_ack;
204
        //
205
        wire            rd_qspi_req;
206
        wire            rd_qspi_grant;
207
        //
208
        wire            rd_spi_wr, rd_spi_hold, rd_spi_spd, rd_spi_dir,
209
                        rd_spi_recycle;
210
        wire    [31:0]   rd_spi_word;
211
        wire    [1:0]    rd_spi_len;
212
        //
213
        readqspi        rdproc(i_clk_200mhz, bus_readreq, bus_piperd,
214
                                        bus_other_req,
215
                                bus_addr, rd_bus_ack,
216
                                rd_qspi_req, rd_qspi_grant,
217
                                rd_spi_wr, rd_spi_hold, rd_spi_word, rd_spi_len,
218
                                rd_spi_spd, rd_spi_dir, rd_spi_recycle,
219
                                        spi_out, spi_valid,
220
                                        spi_busy, spi_stopped, rd_data_ack, rd_data,
221
                                        w_quad, w_xip);
222
 
223
        //
224
        // Write/Erase flash module
225
        //
226
        //      Logic to write (program) and erase the flash.
227
        //
228
        // Wishbone bus return
229
        wire            ew_data_ack;
230
        wire    [31:0]   ew_data;
231
        // Arbiter interaction
232
        wire            ew_qspi_req;
233
        wire            ew_qspi_grant;
234
        // Bus controller return
235
        wire            ew_bus_ack;
236
        // SPI control wires
237
        wire            ew_spi_wr, ew_spi_hold, ew_spi_spd, ew_spi_dir;
238
        wire    [31:0]   ew_spi_word;
239
        wire    [1:0]    ew_spi_len;
240
        //
241
        wire            w_ew_wip;
242
        //
243
        writeqspi       ewproc(i_clk_200mhz, bus_wreq,bus_ereq,
244
                                        bus_pipewr, bus_endwr,
245
                                        bus_addr, bus_data,
246
                                ew_bus_ack, ew_qspi_req, ew_qspi_grant,
247
                                ew_spi_wr, ew_spi_hold, ew_spi_word, ew_spi_len,
248
                                        ew_spi_spd, ew_spi_dir,
249
                                        spi_out, spi_valid, spi_busy, spi_stopped,
250
                                ew_data_ack, w_quad, w_ew_wip);
251
 
252
        //
253
        // Control module
254
        //
255
        //      Logic to read/write status and configuration registers
256
        //
257
        // Wishbone bus return
258
        wire            ct_data_ack;
259
        wire    [31:0]   ct_data;
260
        // Arbiter interaction
261
        wire            ct_qspi_req;
262
        wire            ct_grant;
263
        // Bus controller return
264
        wire            ct_ack;
265
        // SPI control wires
266
        wire            ct_spi_wr, ct_spi_hold, ct_spi_spd, ct_spi_dir;
267
        wire    [31:0]   ct_spi_word;
268
        wire    [1:0]    ct_spi_len;
269
        //
270
        ctrlspi         ctproc(i_clk_200mhz,
271
                                bus_ctreq, bus_wr, bus_addr[2:0], bus_data, bus_sector,
272
                                ct_qspi_req, ct_grant,
273
                                ct_spi_wr, ct_spi_hold, ct_spi_word, ct_spi_len,
274
                                        ct_spi_spd, ct_spi_dir,
275
                                        spi_out, spi_valid, spi_busy, spi_stopped,
276
                                ct_ack, ct_data_ack, ct_data, w_xip, w_quad);
277
        assign  ct_spi_hold = 1'b0;
278
        assign  ct_spi_spd  = 1'b0;
279
 
280
        //
281
        // ID/OTP module
282
        //
283
        //      Access to ID and One-Time-Programmable registers, but to read
284
        //      and to program (the OTP), and to finally lock (OTP) registers.
285
        //
286
        // Wishbone bus return
287
        wire            id_data_ack;
288
        wire    [31:0]   id_data;
289
        // Arbiter interaction
290
        wire            id_qspi_req;
291
        wire            id_qspi_grant;
292
        // Bus controller return
293
        wire            id_bus_ack;
294
        // SPI control wires
295
        wire            id_spi_wr, id_spi_hold, id_spi_spd, id_spi_dir;
296
        wire    [31:0]   id_spi_word;
297
        wire    [1:0]    id_spi_len;
298
        //
299
        wire            w_id_wip;
300
        //
301
        idotpqspi       idotp(i_clk_200mhz, bus_idreq,
302
                                bus_wr, bus_pipewr, bus_addr[4:0], bus_data, id_bus_ack,
303
                                id_qspi_req, id_qspi_grant,
304
                                id_spi_wr, id_spi_hold, id_spi_word, id_spi_len,
305
                                        id_spi_spd, id_spi_dir,
306
                                        spi_out, spi_valid, spi_busy, spi_stopped,
307
                                id_data_ack, id_data, w_idloaded, w_id_wip);
308
 
309
        // Arbitrator
310
        reg             owned;
311
        reg     [1:0]    owner;
312
        initial         owned = 1'b0;
313
        always @(posedge i_clk_200mhz) // 7 inputs (spi_stopped is the CE)
314
                if ((~owned)&&(spi_stopped))
315
                begin
316
                        casez({rd_qspi_req,ew_qspi_req,id_qspi_req,ct_qspi_req})
317
                        4'b1???: begin owned<= 1'b1; owner <= 2'b00; end
318
                        4'b01??: begin owned<= 1'b1; owner <= 2'b01; end
319
                        4'b001?: begin owned<= 1'b1; owner <= 2'b10; end
320
                        4'b0001: begin owned<= 1'b1; owner <= 2'b11; end
321
                        default: begin owned<= 1'b0; owner <= 2'b00; end
322
                        endcase
323
                end else if ((owned)&&(spi_stopped))
324
                begin
325
                        casez({rd_qspi_req,ew_qspi_req,id_qspi_req,ct_qspi_req,owner})
326
                        6'b0???00: owned<= 1'b0;
327
                        6'b?0??01: owned<= 1'b0;
328
                        6'b??0?10: owned<= 1'b0;
329
                        6'b???011: owned<= 1'b0;
330
                        default: begin ; end
331
                        endcase
332
                end
333
 
334
        assign  rd_qspi_grant = (owned)&&(owner == 2'b00);
335
        assign  ew_qspi_grant = (owned)&&(owner == 2'b01);
336
        assign  id_qspi_grant = (owned)&&(owner == 2'b10);
337
        assign  ct_grant      = (owned)&&(owner == 2'b11);
338
 
339
        // Module controller
340
        always @(posedge i_clk_200mhz)
341
        case(owner)
342
        2'b00: begin
343
                spi_wr      <= (owned)&&(rd_spi_wr);
344
                spi_hold    <= rd_spi_hold;
345
                spi_word    <= rd_spi_word;
346
                spi_len     <= rd_spi_len;
347
                spi_spd     <= rd_spi_spd;
348
                spi_dir     <= rd_spi_dir;
349
                spi_recycle <= rd_spi_recycle;
350
                end
351
        2'b01: begin
352
                spi_wr      <= (owned)&&(ew_spi_wr);
353
                spi_hold    <= ew_spi_hold;
354
                spi_word    <= ew_spi_word;
355
                spi_len     <= ew_spi_len;
356
                spi_spd     <= ew_spi_spd;
357
                spi_dir     <= ew_spi_dir;
358
                spi_recycle <= 1'b1; // Long recycle time
359
                end
360
        2'b10: begin
361
                spi_wr      <= (owned)&&(id_spi_wr);
362
                spi_hold    <= id_spi_hold;
363
                spi_word    <= id_spi_word;
364
                spi_len     <= id_spi_len;
365
                spi_spd     <= id_spi_spd;
366
                spi_dir     <= id_spi_dir;
367
                spi_recycle <= 1'b1; // Long recycle time
368
                end
369
        2'b11: begin
370
                spi_wr      <= (owned)&&(ct_spi_wr);
371
                spi_hold    <= ct_spi_hold;
372
                spi_word    <= ct_spi_word;
373
                spi_len     <= ct_spi_len;
374
                spi_spd     <= ct_spi_spd;
375
                spi_dir     <= ct_spi_dir;
376
                spi_recycle <= 1'b1; // Long recycle time
377
                end
378
        endcase
379
 
380
        reg     last_wip;
381
        initial bus_wip = 1'b0;
382
        initial last_wip = 1'b0;
383
        initial o_interrupt = 1'b0;
384
        always @(posedge i_clk_200mhz)
385
        begin
386
                bus_wip <= w_ew_wip || w_id_wip;
387
                last_wip <= bus_wip;
388
                o_interrupt <= ((~bus_wip)&&(last_wip));
389
        end
390
 
391
 
392
        // Now, let's return values onto the wb bus
393
        always @(posedge i_clk_200mhz)
394
        begin
395
                // Ack our internal bus controller.  This means the command was
396
                // accepted, and the bus can go on to looking for the next 
397
                // command.  It controls the i_wb_stall line, just not the
398
                // i_wb_ack line.
399
 
400
                // Ack the wishbone with any response
401
                o_wb_ack <= (bus_wb_ack)|(rd_data_ack)|(ew_data_ack)|(id_data_ack)|(ct_data_ack);
402
                o_wb_data <= (bus_wb_ack)?bus_wb_data
403
                        : (id_data_ack) ? id_data : spi_out;
404
        end
405
 
406
        assign  o_wb_stall = bus_wb_stall;
407
        assign  bus_ack = (rd_bus_ack|ew_bus_ack|id_bus_ack|ct_ack);
408
 
409
        assign  o_dbg = {
410
                i_wb_cyc, i_wb_ctrl_stb, i_wb_data_stb, o_wb_ack, bus_ack, //5
411
                //
412
                (spi_wr)&&(~spi_busy), spi_valid, spi_word[31:25],
413
                spi_out[7:2],
414
                //
415
                o_qspi_cs_n, o_qspi_sck, o_qspi_mod,    // 4 bits
416
                o_qspi_dat, i_qspi_dat                  // 8 bits
417
                };
418
endmodule
419
 
420
module  qspibus(i_clk, i_rst, i_cyc, i_data_stb, i_ctrl_stb,
421
                i_we, i_addr, i_data,
422
                        o_wb_ack, o_wb_stall, o_wb_data,
423
                o_wr, o_addr, o_data, o_sector,
424
                o_readreq, o_piperd, o_wrreq, o_erreq, o_pipewr, o_endwr,
425
                        o_ctreq, o_idreq, o_other,
426
                i_ack, i_xip, i_quad, i_idloaded, i_wip, i_spi_stopped);
427
        //
428
        input                   i_clk, i_rst;
429
        // Wishbone bus inputs
430
        input                   i_cyc, i_data_stb, i_ctrl_stb, i_we;
431
        input           [21:0]   i_addr;
432
        input           [31:0]   i_data;
433
        // Wishbone bus outputs
434
        output  reg             o_wb_ack;
435
        output  reg             o_wb_stall;
436
        output  wire    [31:0]   o_wb_data;
437
        // Internal signals to the QSPI flash interface
438
        output  reg             o_wr;
439
        output  reg     [21:0]   o_addr;
440
        output  reg     [31:0]   o_data;
441
        output  wire    [21:0]   o_sector;
442
        output  reg             o_readreq, o_piperd, o_wrreq, o_erreq,
443
                                o_pipewr, o_endwr,
444
                                o_ctreq, o_idreq;
445
        output  wire            o_other;
446
        input                   i_ack, i_xip, i_quad, i_idloaded;
447
        input                   i_wip, i_spi_stopped;
448
 
449
 
450
        //
451
        reg     pending, lcl_wrreq, lcl_ctreq, lcl_ack, ack, wp_err, wp;
452
        reg     lcl_reg;
453
        reg     [14:0]   esector;
454
        reg     [21:0]   next_addr;
455
 
456
 
457
        reg     pipeable;
458
        reg     same_page;
459
        always @(posedge i_clk)
460
                same_page <= (i_data_stb)&&(i_we)
461
                        &&(i_addr[21:6] == o_addr[21:6])
462
                        &&(i_addr[5:0] == o_addr[5:0] + 6'h1);
463
 
464
        initial pending = 1'b0;
465
        initial o_readreq = 1'b0;
466
        initial lcl_wrreq = 1'b0;
467
        initial lcl_ctreq = 1'b0;
468
        initial o_ctreq   = 1'b0;
469
        initial o_idreq   = 1'b0;
470
 
471
        initial ack = 1'b0;
472
        always @(posedge i_clk)
473
                ack <= (i_ack)||(lcl_ack);
474
 
475
        // wire [9:0]   key;
476
        // assign       key = 10'h1be;
477
        reg     lcl_key, set_sector, ctreg_stb;
478
        initial lcl_key = 1'b0;
479
        always @(posedge i_clk)
480
                // Write protect "key" to enable the disabling of write protect
481
                lcl_key<= (i_ctrl_stb)&&(~wp)&&(i_we)&&(i_addr[5:0]==6'h00)
482
                                &&(i_data[9:0] == 10'h1be)&&(i_data[31:30]==2'b11);
483
        initial set_sector = 1'b0;
484
        always @(posedge i_clk)
485
                set_sector <= (i_ctrl_stb)&&(~o_wb_stall)
486
                                &&(i_we)&&(i_addr[5:0]==6'h00)
487
                                &&(i_data[9:0] == 10'h1be);
488
 
489
        always @(posedge i_clk)
490
                if (i_ctrl_stb)
491
                        lcl_reg <= (i_addr[3:0] == 4'h00);
492
 
493
        initial ctreg_stb = 1'b0;
494
        initial o_wb_stall = 1'b0;
495
        always @(posedge i_clk)
496
        begin // Inputs: rst, stb, stb, stall, ack, addr[4:0] -- 9
497
                if (i_rst)
498
                        o_wb_stall <= 1'b0;
499
                else
500
                        o_wb_stall <= (((i_data_stb)||(i_ctrl_stb))&&(~o_wb_stall))
501
                                ||((pending)&&(~ack));
502
 
503
                ctreg_stb <= (i_ctrl_stb)&&(~o_wb_stall)&&(i_addr[4:0]==5'h00)&&(~pending)
504
                                ||(pending)&&(ctreg_stb)&&(~lcl_ack)&&(~i_ack);
505
                if (~o_wb_stall)
506
                begin // Bus command accepted!
507
                        if ((i_data_stb)||(i_ctrl_stb))
508
                        begin
509
                                pending <= 1'b1;
510
                                o_addr <= i_addr;
511
                                o_data <= i_data;
512
                                o_wr   <= i_we;
513
                                next_addr <= i_addr + 22'h1;
514
                        end
515
 
516
                        if ((i_data_stb)&&(~i_we))
517
                                o_readreq <= 1'b1;
518
 
519
                        if ((i_data_stb)&&(i_we))
520
                                lcl_wrreq <= 1'b1;
521
                        if ((i_ctrl_stb)&&(~i_addr[4]))
522
                        begin
523
                                casez(i_addr[4:0])
524
                                5'h0: lcl_ctreq<= 1'b1;
525
                                5'h1: lcl_ctreq <= 1'b1;
526
                                5'h2: lcl_ctreq <= 1'b1;
527
                                5'h3: lcl_ctreq <= 1'b1;
528
                                5'h4: lcl_ctreq <= 1'b1;
529
                                5'h5: lcl_ctreq <= 1'b1;
530
                                5'h6: lcl_ctreq <= 1'b1;
531
                                5'h7: lcl_ctreq <= 1'b1;
532
                                5'h8: o_idreq <= 1'b1;  // ID[0]
533
                                5'h9: o_idreq <= 1'b1;  // ID[1]
534
                                5'ha: o_idreq <= 1'b1;  // ID[2]
535
                                5'hb: o_idreq <= 1'b1;  // ID[3]
536
                                5'hc: o_idreq <= 1'b1;  // ID[4]
537
                                5'hd: o_idreq <= 1'b1;  //
538
                                5'he: o_idreq <= 1'b1;
539
                                5'hf: o_idreq <= 1'b1; // Program OTP register
540
                                default: begin o_idreq <= 1'b1; end
541
                                endcase
542
                        end else if (i_ctrl_stb)
543
                                o_idreq <= 1'b1;
544
                end else if (ack)
545
                begin
546
                        pending <= 1'b0;
547
                        o_readreq <= 1'b0;
548
                        o_idreq <= 1'b0;
549
                        lcl_ctreq <= 1'b0;
550
                        lcl_wrreq <= 1'b0;
551
                end
552
 
553
                if(i_rst)
554
                begin
555
                        pending <= 1'b0;
556
                        o_readreq <= 1'b0;
557
                        o_idreq <= 1'b0;
558
                        lcl_ctreq <= 1'b0;
559
                        lcl_wrreq <= 1'b0;
560
                end
561
 
562
                if ((i_data_stb)&&(~o_wb_stall))
563
                        o_piperd <= ((~i_we)&&(~o_wb_stall)&&(pipeable)&&(i_addr == next_addr));
564
                else if ((i_ack)||(((i_ctrl_stb)||(i_data_stb))&&(~o_wb_stall)))
565
                        o_piperd <= 1'b0;
566
                if ((i_data_stb)&&(~o_wb_stall))
567
                        pipeable <= (~i_we);
568
                else if ((i_ctrl_stb)&&(~o_wb_stall))
569
                        pipeable <= 1'b0;
570
 
571
                o_pipewr <= (same_page)||(pending)&&(o_pipewr);
572
        end
573
 
574
        reg     r_other, last_wip;
575
 
576
        reg     last_pending;
577
        always @(posedge i_clk)
578
                last_pending <= pending;
579
        always @(posedge i_clk)
580
                last_wip <= i_wip;
581
        wire    new_req;
582
        assign  new_req = (pending)&&(~last_pending);
583
 
584
        initial o_wrreq   = 1'b0;
585
        initial o_erreq   = 1'b0;
586
        initial wp_err    = 1'b0;
587
        initial lcl_ack   = 1'b0;
588
        initial r_other   = 1'b0;
589
        initial o_endwr   = 1'b1;
590
        initial wp        = 1'b1;
591
        always @(posedge i_clk)
592
        begin
593
                if (i_ack)
594
                begin
595
                        o_erreq <= 1'b0;
596
                        o_wrreq <= 1'b0;
597
                        o_ctreq <= 1'b0;
598
                        r_other <= 1'b0;
599
                end
600
 
601
                if ((last_wip)&&(~i_wip))
602
                        wp <= 1'b1;
603
 
604
                // o_endwr  <= ((~i_cyc)||(~o_wr)||(o_pipewr))
605
                                // ||(~new_req)&&(o_endwr);
606
                o_endwr <= ((pending)&&(~o_pipewr))||((~pending)&&(~i_cyc));
607
 
608
                // Default ACK is always set to zero, unless the following ...
609
                o_wb_ack <= 1'b0;
610
 
611
                if (set_sector)
612
                begin
613
                        esector[13:0] <= { o_data[23:14], 4'h0 };
614
                        wp <= (o_data[30])&&(new_req)||(wp)&&(~new_req);
615
                        if (o_data[28])
616
                        begin
617
                                esector[14] <= o_data[28];
618
                                esector[3:0] <= o_data[13:10];
619
                        end
620
                end
621
 
622
                lcl_ack <= 1'b0;
623
                if ((i_wip)&&(new_req)&&(~same_page))
624
                begin
625
                        o_wb_ack <= 1'b1;
626
                        lcl_ack <= 1'b1;
627
                end else if ((ctreg_stb)&&(new_req))
628
                begin // A request of the status register
629
                        // Always ack control register, even on failed attempts
630
                        // to erase.
631
                        o_wb_ack <= 1'b1;
632
                        lcl_ack <= 1'b1;
633
 
634
                        if (lcl_key)
635
                        begin
636
                                o_ctreq <= 1'b0;
637
                                o_erreq <= 1'b1;
638
                                r_other <= 1'b1;
639
                                lcl_ack <= 1'b0;
640
                        end else if ((o_wr)&&(~o_data[31]))
641
                        begin // WEL or WEL disable
642
                                o_ctreq <= (wp == o_data[30]);
643
                                r_other <= (wp == o_data[30]);
644
                                lcl_ack <= (wp != o_data[30]);
645
                                wp <= !o_data[30];
646
                        end else if (~o_wr)
647
                                lcl_ack <= 1'b1;
648
                        wp_err <= (o_data[31])&&(~lcl_key);
649
                end else if ((lcl_ctreq)&&(new_req))
650
                begin
651
                        o_ctreq <= 1'b1;
652
                        r_other <= 1'b1;
653
                end else if ((lcl_wrreq)&&(new_req))
654
                begin
655
                        if (~wp)
656
                        begin
657
                                o_wrreq <= 1'b1;
658
                                r_other <= 1'b1;
659
                                o_endwr  <= 1'b0;
660
                                lcl_ack <= 1'b0;
661
                        end else begin
662
                                o_wb_ack <= 1'b1;
663
                                wp_err <= 1'b1;
664
                                lcl_ack <= 1'b1;
665
                        end
666
                end
667
 
668
                if (i_rst)
669
                begin
670
                        o_ctreq <= 1'b0;
671
                        o_erreq <= 1'b0;
672
                        o_wrreq <= 1'b0;
673
                        r_other <= 1'b0;
674
                end
675
 
676
        end
677
 
678
 
679
        assign o_wb_data[31:0] = { i_wip, ~wp, i_quad, esector[14],
680
                        i_idloaded, wp_err, i_xip, i_spi_stopped,
681
                        esector[13:0], 10'h00 };
682
        assign  o_sector = { esector[13:0], 8'h00 }; // 22 bits
683
        assign  o_other = (r_other)||(o_idreq);
684
 
685
endmodule
686
 
687
 
688
`define RD_IDLE                 4'h0
689
`define RD_IDLE_GET_PORT        4'h1
690
`define RD_SLOW_DUMMY           4'h2
691
`define RD_SLOW_READ_DATA       4'h3
692
`define RD_QUAD_READ_DATA       4'h4
693
`define RD_QUAD_DUMMY           4'h5
694
`define RD_QUAD_ADDRESS         4'h6
695
`define RD_XIP                  4'h7
696
`define RD_GO_TO_IDLE           4'h8
697
`define RD_GO_TO_XIP            4'h9
698
 
699
module  readqspi(i_clk, i_readreq, i_piperd, i_other_req, i_addr, o_bus_ack,
700
                o_qspi_req, i_grant,
701
                        o_spi_wr, o_spi_hold, o_spi_word, o_spi_len,
702
                                o_spi_spd, o_spi_dir, o_spi_recycle,
703
                        i_spi_data, i_spi_valid, i_spi_busy, i_spi_stopped,
704
                        o_data_ack, o_data, i_quad, i_xip);
705
        input                   i_clk;
706
        input                   i_readreq, i_piperd, i_other_req;
707
        input           [21:0]   i_addr;
708
        output  reg             o_bus_ack, o_qspi_req;
709
        input   wire            i_grant;
710
        output  reg             o_spi_wr;
711
        output  wire            o_spi_hold;
712
        output  reg     [31:0]   o_spi_word;
713
        output  reg     [1:0]    o_spi_len;
714
        output  reg             o_spi_spd, o_spi_dir, o_spi_recycle;
715
        input           [31:0]   i_spi_data;
716
        input                   i_spi_valid, i_spi_busy, i_spi_stopped;
717
        output  reg             o_data_ack;
718
        output  reg     [31:0]   o_data;
719
        input                   i_quad, i_xip;
720
 
721
        reg     accepted;
722
        initial accepted = 1'b0;
723
        always @(posedge i_clk)
724
                accepted <= (~i_spi_busy)&&(i_grant)&&(o_spi_wr)&&(~accepted);
725
 
726
        reg     [3:0]    rd_state;
727
        reg             r_leave_xip, r_xip, r_quad, r_requested;
728 11 dgisselq
        reg     [3:0]    invalid_ack_pipe;
729 9 dgisselq
        initial rd_state = `RD_IDLE;
730
        initial o_data_ack = 1'b0;
731
        initial o_bus_ack  = 1'b0;
732
        initial o_qspi_req = 1'b0;
733
        always @(posedge i_clk)
734
        begin
735
                o_data_ack <= 1'b0;
736
                o_bus_ack <= 1'b0;
737
                o_spi_recycle <= 1'b0;
738
                if (i_spi_valid)
739
                        o_data <= i_spi_data;
740 11 dgisselq
                invalid_ack_pipe <= { invalid_ack_pipe[2:0], accepted };
741 9 dgisselq
                case(rd_state)
742
                `RD_IDLE: begin
743
                        r_requested <= 1'b0;
744
                        o_qspi_req <= 1'b0;
745
                        o_spi_word <= { ((i_quad)? 8'h6B: 8'h0b), i_addr, 2'b00 };
746
                        o_spi_wr <= 1'b0;
747
                        o_spi_dir <= 1'b0;
748
                        o_spi_spd <= 1'b0;
749
                        o_spi_len <= 2'b11;
750
                        r_xip <= (i_xip)&&(i_quad);
751
                        r_leave_xip <= 1'b0; // Not in it, so can't leave it
752
                        r_quad <= i_quad;
753
                        if (i_readreq)
754
                        begin
755
                                rd_state <= `RD_IDLE_GET_PORT;
756
                                o_bus_ack <= 1'b1;
757
                        end end
758
                `RD_IDLE_GET_PORT: begin
759
                        o_spi_wr <= 1'b1; // Write the address
760
                        o_qspi_req <= 1'b1;
761
                        if (accepted)
762
                                rd_state <= `RD_SLOW_DUMMY;
763
                        end
764
                `RD_SLOW_DUMMY: begin
765
                        o_spi_wr <= 1'b1; // Write 8 dummy clocks
766
                        o_qspi_req <= 1'b1;
767
                        o_spi_dir <= 1'b0;
768
                        o_spi_spd <= 1'b0;
769
                        o_spi_word[31:24] <= (r_xip) ? 8'h00 : 8'hff;
770
                        o_spi_len  <= 2'b00; // 8 clocks = 8-bits
771
                        if (accepted)
772
                                rd_state <= (r_quad)?`RD_QUAD_READ_DATA
773
                                                : `RD_SLOW_READ_DATA;
774
                        end
775
                `RD_SLOW_READ_DATA: begin
776
                        o_qspi_req <= 1'b1;
777
                        o_spi_dir <= 1'b1;
778
                        o_spi_spd <= 1'b0;
779
                        o_spi_len <= 2'b11;
780
                        o_spi_wr <= (~r_requested)||(i_piperd);
781 11 dgisselq
                        invalid_ack_pipe[0] <= (!r_requested);
782
                        o_data_ack <=  (!invalid_ack_pipe[3])&&(i_spi_valid)&&(r_requested);
783 9 dgisselq
                        o_bus_ack <=   (r_requested)&&(accepted)&&(i_piperd);
784
                        r_requested <= (r_requested)||(accepted);
785
                        if ((i_spi_valid)&&(~o_spi_wr))
786
                                rd_state <= `RD_GO_TO_IDLE;
787
                        end
788
                `RD_QUAD_READ_DATA: begin
789
                        o_qspi_req <= 1'b1;
790
                        o_spi_dir <= 1'b1;
791
                        o_spi_spd <= 1'b1;
792
                        o_spi_len <= 2'b11;
793
                        o_spi_recycle <= (r_leave_xip)? 1'b1: 1'b0;
794 11 dgisselq
                        invalid_ack_pipe[0] <= (!r_requested);
795 9 dgisselq
                        r_requested <= (r_requested)||(accepted);
796 11 dgisselq
                        o_data_ack <=  (!invalid_ack_pipe[3])&&(i_spi_valid)&&(r_requested)&&(~r_leave_xip);
797 9 dgisselq
                        o_bus_ack  <= (r_requested)&&(accepted)&&(i_piperd)&&(~r_leave_xip);
798
                        o_spi_wr <= (~r_requested)||(i_piperd);
799
                        // if (accepted)
800
                                // o_spi_wr <= (i_piperd);
801 11 dgisselq
                        if (accepted) // only happens if (o_spi_wr)
802 9 dgisselq
                                o_data <= i_spi_data;
803
                        if ((i_spi_valid)&&(~o_spi_wr))
804
                                rd_state <= ((r_leave_xip)||(~r_xip))?`RD_GO_TO_IDLE:`RD_GO_TO_XIP;
805
                        end
806
                `RD_QUAD_ADDRESS: begin
807
                        o_qspi_req <= 1'b1;
808
                        o_spi_wr <= 1'b1;
809
                        o_spi_dir <= 1'b0; // Write the address
810
                        o_spi_spd <= 1'b1; // High speed
811
                        o_spi_word[31:0] <= { i_addr, 2'b00, 8'h00 };
812
                        o_spi_len  <= 2'b10; // 24 bits, High speed, 6 clocks
813
                        if (accepted)
814
                                rd_state <= `RD_QUAD_DUMMY;
815
                        end
816
                `RD_QUAD_DUMMY: begin
817
                        o_qspi_req <= 1'b1;
818
                        o_spi_wr <= 1'b1;
819
                        o_spi_dir <= 1'b0; // Write the dummy
820
                        o_spi_spd <= 1'b1; // High speed
821
                        o_spi_word[31:0] <= (r_xip)? 32'h00 : 32'hffffffff;
822
                        o_spi_len  <= 2'b11; // 8 clocks = 32-bits, quad speed
823
                        if (accepted)
824
                                rd_state <= (r_quad)?`RD_QUAD_READ_DATA
825
                                                : `RD_SLOW_READ_DATA;
826
                        end
827
                `RD_XIP: begin
828
                        r_requested <= 1'b0;
829
                        o_qspi_req <= 1'b1;
830
                        o_spi_word <= { i_addr, 2'b00, 8'h00 };
831
                        o_spi_wr <= 1'b0;
832
                        o_spi_dir <= 1'b0; // Write to SPI
833
                        o_spi_spd <= 1'b1; // High speed
834
                        o_spi_len <= 2'b11;
835
                        r_leave_xip <= i_other_req;
836
                        r_xip <= (~i_other_req);
837
                        o_bus_ack <= 1'b0;
838
                        if ((i_readreq)||(i_other_req))
839
                        begin
840
                                rd_state <= `RD_QUAD_ADDRESS;
841
                                o_bus_ack <= i_readreq;
842
                        end end
843
                `RD_GO_TO_IDLE: begin
844 11 dgisselq
                        if ((!invalid_ack_pipe[3])&&(i_spi_valid)&&(~r_leave_xip))
845
                                o_data_ack <=  1'b1;
846
                        o_spi_wr   <= 1'b0;
847 9 dgisselq
                        o_qspi_req <= 1'b0;
848
                        if ((i_spi_stopped)&&(~i_grant))
849
                                rd_state <= `RD_IDLE;
850
                        end
851
                `RD_GO_TO_XIP: begin
852 11 dgisselq
                        r_requested <= 1'b0;
853
                        if ((i_spi_valid)&&(!invalid_ack_pipe[3]))
854
                                o_data_ack <=  1'b1;
855 9 dgisselq
                        o_qspi_req <= 1'b1;
856
                        o_spi_wr   <= 1'b0;
857
                        if (i_spi_stopped)
858
                                rd_state <= `RD_XIP;
859
                        end
860
                default: begin
861
                        // rd_state <= (i_grant)?`RD_BREAK;
862
                        o_qspi_req <= 1'b0;
863
                        o_spi_wr <= 1'b0;
864
                        if ((i_spi_stopped)&&(~i_grant))
865
                                rd_state <= `RD_IDLE;
866
                        end
867
                endcase
868
        end
869
 
870
        assign  o_spi_hold = 1'b0;
871
 
872
endmodule
873
 
874
module  writeqspi(i_clk, i_wreq, i_ereq, i_pipewr, i_endpipe, i_addr, i_data,
875
                        o_bus_ack, o_qspi_req, i_qspi_grant,
876
                                o_spi_wr, o_spi_hold, o_spi_word, o_spi_len,
877
                                o_spi_spd, o_spi_dir, i_spi_data, i_spi_valid,
878
                                        i_spi_busy, i_spi_stopped,
879
                                o_data_ack, i_quad, o_wip);
880
        input           i_clk;
881
        //
882
        input           i_wreq, i_ereq, i_pipewr, i_endpipe;
883
        input           [21:0]   i_addr;
884
        input           [31:0]   i_data;
885
        output  reg             o_bus_ack, o_qspi_req;
886
        input                   i_qspi_grant;
887
        output  reg             o_spi_wr, o_spi_hold;
888
        output  reg     [31:0]   o_spi_word;
889
        output  reg     [1:0]    o_spi_len;
890
        output  reg             o_spi_spd, o_spi_dir;
891
        input           [31:0]   i_spi_data;
892
        input                   i_spi_valid;
893
        input                   i_spi_busy, i_spi_stopped;
894
        output  reg             o_data_ack;
895
        input                   i_quad;
896
        output  reg             o_wip;
897
 
898
`ifdef  QSPI_READ_ONLY
899
        always @(posedge i_clk)
900
                o_data_ack <= (i_wreq)||(i_ereq);
901
        always @(posedge i_clk)
902
                o_bus_ack <= (i_wreq)||(i_ereq);
903
 
904
        always @(posedge i_clk)
905
        begin
906
                o_qspi_req <= 1'b0;
907
                o_spi_wr   <= 1'b0;
908
                o_spi_hold <= 1'b0;
909
                o_spi_dir  <= 1'b1; // Read
910
                o_spi_spd  <= i_quad;
911
                o_spi_len  <= 2'b00;
912
                o_spi_word <= 32'h00;
913
                o_wip <= 1'b0;
914
        end
915
`else
916
 
917
`define WR_IDLE                         4'h0
918
`define WR_START_WRITE                  4'h1
919
`define WR_START_QWRITE                 4'h2
920
`define WR_PROGRAM                      4'h3
921
`define WR_PROGRAM_GETNEXT              4'h4
922
`define WR_START_ERASE                  4'h5
923
`define WR_WAIT_ON_STOP                 4'h6
924
`define WR_REQUEST_STATUS               4'h7
925
`define WR_REQUEST_STATUS_NEXT          4'h8
926
`define WR_READ_STATUS                  4'h9
927
`define WR_WAIT_ON_FINAL_STOP           4'ha
928
 
929
        reg     accepted;
930
        initial accepted = 1'b0;
931
        always @(posedge i_clk)
932
                accepted <= (~i_spi_busy)&&(i_qspi_grant)&&(o_spi_wr)&&(~accepted);
933
 
934
 
935 11 dgisselq
        reg             cyc, chk_wip, valid_status;
936 9 dgisselq
        reg     [3:0]    wr_state;
937
        initial wr_state = `WR_IDLE;
938
        initial cyc = 1'b0;
939
        always @(posedge i_clk)
940
        begin
941
                chk_wip <= 1'b0;
942
                o_bus_ack  <= 1'b0;
943
                o_data_ack <= 1'b0;
944
                case(wr_state)
945
                `WR_IDLE: begin
946 11 dgisselq
                        valid_status <= 1'b0;
947 9 dgisselq
                        o_qspi_req <= 1'b0;
948
                        cyc <= 1'b0;
949
                        if (i_ereq)
950
                                wr_state <= `WR_START_ERASE;
951
                        else if (i_wreq)
952
                                wr_state <= (i_quad)?`WR_START_QWRITE
953
                                        : `WR_START_WRITE;
954
                        end
955
                `WR_START_WRITE: begin
956
                        o_wip      <= 1'b1;
957
                        o_qspi_req <= 1'b1;
958
                        o_spi_wr   <= 1'b1;
959
                        o_spi_dir  <= 1'b0;
960
                        o_spi_len  <= 2'b11;
961
                        o_spi_spd  <= 1'b0;
962
                        o_spi_hold <= 1'b1;
963
                        o_spi_word <= { 8'h02, i_addr, 2'b00 };
964
                        cyc <= 1'b1;
965
                        if (accepted)
966
                        begin
967
                                o_bus_ack  <= 1'b1;
968
                                o_data_ack <= 1'b1;
969
                                wr_state <= `WR_PROGRAM;
970
                                o_spi_word <= i_data;
971
                        end end
972
                `WR_START_QWRITE: begin
973
                        o_wip      <= 1'b1;
974
                        o_qspi_req <= 1'b1;
975
                        o_spi_wr   <= 1'b1;
976
                        o_spi_dir  <= 1'b0;
977
                        o_spi_len  <= 2'b11;
978
                        o_spi_spd  <= 1'b0;
979
                        o_spi_hold <= 1'b1;
980
                        o_spi_word <= { 8'h32, i_addr, 2'b00 };
981
                        cyc <= 1'b1;
982
                        if (accepted)
983
                        begin
984
                                o_bus_ack  <= 1'b1;
985
                                o_data_ack <= 1'b1;
986
                                wr_state <= `WR_PROGRAM;
987
                                o_spi_word <= i_data;
988
                        end end
989
                `WR_PROGRAM: begin
990
                        o_wip     <= 1'b1;
991
                        o_qspi_req <= 1'b1;
992
                        o_spi_wr   <= 1'b1;
993
                        o_spi_dir  <= 1'b0;
994
                        o_spi_len  <= 2'b11;
995
                        o_spi_spd  <= i_quad;
996
                        o_spi_hold <= 1'b1;
997
                        // o_spi_word <= i_data;
998
                        if (accepted)
999
                                wr_state <= `WR_PROGRAM_GETNEXT;
1000
                        end
1001
                `WR_PROGRAM_GETNEXT: begin
1002
                        o_wip      <= 1'b1;
1003
                        o_qspi_req <= 1'b1;
1004
                        o_spi_wr   <= 1'b0;
1005
                        o_spi_dir  <= 1'b0;
1006
                        o_spi_len  <= 2'b11;
1007
                        o_spi_spd  <= i_quad;
1008
                        o_spi_hold <= 1'b1;
1009
                        o_spi_word <= i_data;
1010 11 dgisselq
                        cyc <= (cyc)&&(~i_endpipe);
1011 9 dgisselq
                        if (~cyc)
1012
                                wr_state <= `WR_WAIT_ON_STOP;
1013
                        else if (i_pipewr)
1014
                        begin
1015
                                o_bus_ack  <= 1'b1;
1016
                                o_data_ack <= 1'b1;
1017
                                wr_state <= `WR_PROGRAM;
1018
                        end end
1019
                `WR_START_ERASE: begin
1020
                        o_wip <= 1'b1;
1021
                        o_qspi_req <= 1'b1;
1022
                        o_spi_wr  <= 1'b1;
1023
                        o_spi_dir <= 1'b0;
1024
                        o_spi_spd <= 1'b0;
1025
                        o_spi_len <= 2'b11;
1026
                        if (i_data[28])
1027
                                // Subsector erase
1028
                                o_spi_word[31:24] <= 8'h20;
1029
                        else
1030
                                // Sector erase
1031
                                o_spi_word[31:24] <= 8'hd8;
1032
                        o_spi_word[23:0] <= { i_data[21:10], 12'h0 };
1033
                        // Data has already been ack'd, so no need to ack
1034
                        // it again.  However, we can now free the QSPI
1035
                        // bus processor to accept another command from the
1036
                        // bus.
1037
                        o_bus_ack <= accepted;
1038
                        if (accepted)
1039
                                wr_state <= `WR_WAIT_ON_STOP;
1040
                        end
1041
                `WR_WAIT_ON_STOP: begin
1042
                        o_wip <= 1'b1;
1043
                        o_qspi_req <= 1'b0;
1044
                        o_spi_wr   <= 1'b0;
1045
                        o_spi_hold <= 1'b0;
1046
                        if (i_spi_stopped)
1047
                                wr_state <= `WR_REQUEST_STATUS;
1048
                        end
1049
                `WR_REQUEST_STATUS: begin
1050
                        o_wip <= 1'b1;
1051
                        o_qspi_req <= 1'b1;
1052
                        o_spi_hold <= 1'b0;
1053
                        o_spi_wr   <= 1'b1;
1054
                        o_spi_spd  <= 1'b0; // Slow speed
1055
                        o_spi_len  <= 2'b00; // 8 bytes
1056
                        o_spi_dir  <= 1'b0; // Write
1057
                        o_spi_word <= { 8'h05, 24'h00 };
1058
                        if (accepted)
1059
                                wr_state <= `WR_REQUEST_STATUS_NEXT;
1060
                        end
1061
                `WR_REQUEST_STATUS_NEXT: begin
1062
                        o_wip <= 1'b1;
1063
                        o_qspi_req <= 1'b1;
1064
                        o_spi_hold <= 1'b0;
1065
                        o_spi_wr   <= 1'b1;
1066
                        o_spi_spd  <= 1'b0; // Slow speed
1067
                        o_spi_len  <= 2'b00; // 8 bytes
1068
                        o_spi_dir  <= 1'b1; // Read
1069
                        o_spi_word <= 32'h00;
1070
                        if (accepted)
1071
                                wr_state <= `WR_READ_STATUS;
1072 11 dgisselq
                        valid_status <= 1'b0;
1073 9 dgisselq
                        end
1074
                `WR_READ_STATUS: begin
1075
                        o_wip <= 1'b1;
1076
                        o_qspi_req <= 1'b1;
1077
                        o_spi_hold <= 1'b0;
1078
                        o_spi_wr   <= 1'b1;
1079
                        o_spi_spd  <= 1'b0; // Slow speed
1080
                        o_spi_len  <= 2'b00; // 8 bytes
1081
                        o_spi_dir  <= 1'b1; // Read
1082
                        o_spi_word <= 32'h00;
1083
                        if (i_spi_valid)
1084 11 dgisselq
                                valid_status <= 1'b1;
1085
                        if ((i_spi_valid)&&(valid_status))
1086 9 dgisselq
                                chk_wip <= 1'b1;
1087
                        if ((chk_wip)&&(~i_spi_data[0]))
1088
                                wr_state <= `WR_WAIT_ON_FINAL_STOP;
1089
                        end
1090
                // `WR_WAIT_ON_FINAL_STOP: // Same as the default
1091
                default: begin
1092
                        o_qspi_req <= 1'b0;
1093
                        o_spi_wr <= 1'b0;
1094
                        o_wip <= 1'b0;
1095
                        if (i_spi_stopped)
1096
                                wr_state <= `WR_IDLE;
1097
                        end
1098
                endcase
1099
        end
1100
`endif
1101
 
1102
endmodule
1103
 
1104
 
1105
`define CT_SAFE
1106
`define CT_IDLE                 3'h0
1107
`define CT_NEXT                 3'h1
1108
`define CT_GRANTED              3'h2
1109
`define CT_DATA                 3'h3
1110
`define CT_READ_DATA            3'h4
1111
`define CT_WAIT_FOR_IDLE        3'h5
1112
 
1113
// CTRL commands:
1114
//      WEL (write-enable latch)
1115
//      Read Status
1116
module  ctrlspi(i_clk, i_req, i_wr, i_addr, i_data, i_sector_address,
1117
                                o_spi_req, i_grant,
1118
                                o_spi_wr, o_spi_hold, o_spi_word, o_spi_len,
1119
                                        o_spi_spd, o_spi_dir,
1120
                                i_spi_data, i_spi_valid, i_spi_busy,
1121
                                        i_spi_stopped,
1122
                                o_bus_ack, o_data_ack, o_data, o_xip, o_quad);
1123
        input           i_clk;
1124
        // From the WB bus controller
1125
        input                   i_req;
1126
        input                   i_wr;
1127
        input           [2:0]    i_addr;
1128
        input           [31:0]   i_data;
1129
        input           [21:0]   i_sector_address;
1130
        // To/from the arbiter
1131
        output  reg             o_spi_req;
1132
        input                   i_grant;
1133
        // To/from the low-level SPI driver
1134
        output  reg             o_spi_wr;
1135
        output  wire            o_spi_hold;
1136
        output  reg     [31:0]   o_spi_word;
1137
        output  reg     [1:0]    o_spi_len;
1138
        output  wire            o_spi_spd;
1139
        output  reg             o_spi_dir;
1140
        input           [31:0]   i_spi_data;
1141
        input                   i_spi_valid;
1142
        input                   i_spi_busy, i_spi_stopped;
1143
        // Return data to the bus controller, and the wishbone bus
1144
        output  reg             o_bus_ack, o_data_ack;
1145
        output  reg     [31:0]   o_data;
1146
        // Configuration items that we may have configured.
1147
        output  reg             o_xip;
1148
        output  wire            o_quad;
1149
 
1150
        // Command registers
1151
        reg     [1:0]    ctcmd_len;
1152
        reg     [31:0]   ctcmd_word;
1153
        // Data stage registers
1154
        reg             ctdat_skip, // Skip the data phase?
1155
                        ctdat_wr;       // Write during data? (or not read)
1156
        wire    [1:0]    ctdat_len;
1157
        reg     [31:0]   ctdat_word;
1158
 
1159
        reg     [2:0]    ctstate;
1160
        reg             accepted;
1161 11 dgisselq
        reg     [3:0]    invalid_ack_pipe;
1162 9 dgisselq
 
1163
 
1164
        initial accepted = 1'b0;
1165
        always @(posedge i_clk)
1166
                accepted <= (~i_spi_busy)&&(i_grant)&&(o_spi_wr)&&(~accepted);
1167
 
1168 11 dgisselq
        reg     r_ctdat_len, ctbus_ack, first_valid;
1169 9 dgisselq
        assign  ctdat_len = { 1'b0, r_ctdat_len };
1170
 
1171
        // First step, calculate the values for our state machine
1172
        initial o_xip = 1'b0;
1173
        // initial o_quad = 1'b0;
1174
        always @(posedge i_clk)
1175
        if (i_req) // A request for us to act from the bus controller
1176
        begin
1177
                ctdat_skip <= 1'b0;
1178
                ctbus_ack  <= 1'b1;
1179
                ctcmd_word[23:0] <= { i_sector_address, 2'b00 };
1180
                ctdat_word <= { i_data[7:0], 24'h00 };
1181
                ctcmd_len <= 2'b00; // 8bit command (for all but Lock regs)
1182
                r_ctdat_len <= 1'b0; // 8bit data (read or write)
1183
                ctdat_wr <= i_wr;
1184
                casez({ i_addr[2:0], i_wr, i_data[30] })
1185
                5'b00010: begin // Write Disable
1186
                        ctcmd_word[31:24] <= 8'h04;
1187
                        ctdat_skip <= 1'b1;
1188
                        ctbus_ack  <= 1'b0;
1189
                        end
1190
                5'b00011: begin // Write enable
1191
                        ctcmd_word[31:24] <= 8'h06;
1192
                        ctdat_skip <= 1'b1;
1193
                        ctbus_ack  <= 1'b0;
1194
                        end
1195
                // 4'b0010?: begin // Read Status register
1196
                //      Moved to defaults section
1197
                5'b0011?: begin // Write Status register (Requires WEL)
1198
                        ctcmd_word[31:24] <= 8'h01;
1199
`ifdef  CT_SAFE
1200
                        ctdat_word <= { 6'h00, i_data[1:0], 24'h00 };
1201
`else
1202
                        ctdat_word <= { i_data[7:0], 24'h00 };
1203
`endif
1204
                        end
1205
                5'b0100?: begin // Read NV-Config register (two bytes)
1206
                        ctcmd_word[31:24] <= 8'hB5;
1207
                        r_ctdat_len <= 1'b1; // 16-bit data
1208
                        end
1209
                5'b0101?: begin // Write NV-Config reg (2 bytes, Requires WEL)
1210
                        ctcmd_word[31:24] <= 8'hB1;
1211
                        r_ctdat_len <= 1'b1; // 16-bit data
1212
`ifdef  CT_SAFE
1213
                        ctdat_word <= { 4'h8, 3'h7, 3'h7, i_data[5:1], 1'b1, 16'h00 };
1214
`else
1215
                        ctdat_word <= { i_data[15:0], 16'h00 };
1216
`endif
1217
                        end
1218
                5'b0110?: begin // Read V-Config register
1219
                        ctcmd_word[31:24] <= 8'h85;
1220
                        end
1221
                5'b0111?: begin // Write V-Config register (Requires WEL)
1222
                        ctcmd_word[31:24] <= 8'h81;
1223
                        r_ctdat_len <= 1'b0; // 8-bit data
1224
`ifdef  CT_SAFE
1225
                        ctdat_word <= { 4'h8, i_data[3:2], 2'b11, 24'h00 };
1226
`else
1227
                        ctdat_word <= { i_data[7:0], 24'h00 };
1228
`endif
1229
                        o_xip <= i_data[3];
1230
                        end
1231
                5'b1000?: begin // Read EV-Config register
1232
                        ctcmd_word[31:24] <= 8'h65;
1233
                        end
1234
                5'b1001?: begin // Write EV-Config register (Requires WEL)
1235
                        ctcmd_word[31:24] <= 8'h61;
1236
                        // o_quad <= (~i_data[7]);
1237
`ifdef  CT_SAFE
1238
                        ctdat_word <= { 1'b1, 3'h5, 4'hf, 24'h00 };
1239
`else
1240
                        ctdat_word <= { i_data[7:0], 24'h00 };
1241
`endif
1242
                        end
1243
                5'b1010?: begin // Read Lock register
1244
                        ctcmd_word[31:0] <= { 8'he8,  i_sector_address, 2'b00 };
1245
                        ctcmd_len <= 2'b11;
1246
                        ctdat_wr  <= 1'b0;  // Read, not write
1247
                        end
1248
                5'b1011?: begin // Write Lock register (Requires WEL)
1249
                        ctcmd_word[31:0] <= { 8'he5, i_sector_address, 2'b00 };
1250
                        ctcmd_len <= 2'b11;
1251
                        ctdat_wr  <= 1'b1;  // Write
1252
                        end
1253
                5'b1100?: begin // Read Flag Status register
1254
                        ctcmd_word[31:24] <= 8'h70;
1255
                        ctdat_wr  <= 1'b0;  // Read, not write
1256
                        end
1257
                5'b1101?: begin // Write/Clear Flag Status register (No WEL required)
1258
                        ctcmd_word[31:24] <= 8'h50;
1259
                        ctdat_skip <= 1'b1;
1260
                        end
1261
                default: begin // Default to reading the status register
1262
                        ctcmd_word[31:24] <= 8'h05;
1263
                        ctdat_wr  <= 1'b0;  // Read, not write
1264
                        r_ctdat_len <= 1'b0; // 8-bit data
1265
                        end
1266
                endcase
1267
        end
1268
 
1269 10 dgisselq
        assign  o_quad = 1'b1;
1270 9 dgisselq
 
1271
        reg     nxt_data_ack;
1272
 
1273
        // Second step, actually drive the state machine
1274
        initial ctstate = `CT_IDLE;
1275
        always @(posedge i_clk)
1276
        begin
1277
                o_spi_wr <= 1'b1;
1278
                o_bus_ack <= 1'b0;
1279
                o_data_ack <= 1'b0;
1280 11 dgisselq
                invalid_ack_pipe <= { invalid_ack_pipe[2:0], accepted };
1281 9 dgisselq
                if (i_spi_valid)
1282
                        o_data <= i_spi_data;
1283
                case(ctstate)
1284
                `CT_IDLE: begin
1285
                        o_spi_req <= 1'b0;
1286
                        o_spi_wr  <= 1'b0;
1287
                        if (i_req) // Need a clock to let the digestion
1288
                                ctstate <= `CT_NEXT; // process complete
1289
                        end
1290
                `CT_NEXT: begin
1291
                        o_spi_wr <= 1'b1;
1292
                        o_spi_req <= 1'b1;
1293
                        o_spi_word <= ctcmd_word;
1294
                        o_spi_len <= ctcmd_len;
1295
                        o_spi_dir <= 1'b0; // Write
1296
                        if (accepted)
1297
                        begin
1298
                                ctstate <= (ctdat_skip)?`CT_WAIT_FOR_IDLE:`CT_DATA;
1299
                                o_bus_ack <= (ctdat_skip);
1300
                                o_data_ack <= (ctdat_skip)&&(ctbus_ack);
1301
                        end end
1302
                `CT_GRANTED: begin
1303
                        o_spi_wr <= 1'b1;
1304
                        if ((accepted)&&(ctdat_skip))
1305
                                ctstate <= `CT_WAIT_FOR_IDLE;
1306
                        else if (accepted)//&&(~ctdat_skip)
1307
                                ctstate <= `CT_DATA;
1308
                        end
1309
                `CT_DATA: begin
1310
                        o_spi_wr   <= 1'b1;
1311
                        o_spi_len  <= ctdat_len;
1312
                        o_spi_dir  <= ~ctdat_wr;
1313
                        o_spi_word <= ctdat_word;
1314
                        if (accepted)
1315
                                o_bus_ack <= 1'b1;
1316
                        if (accepted)
1317
                                ctstate <= (ctdat_wr)?`CT_WAIT_FOR_IDLE:`CT_READ_DATA;
1318
                        if ((accepted)&&(ctdat_wr))
1319
                                o_data_ack <= 1'b1;
1320 11 dgisselq
                        first_valid <= 1'b0;
1321 9 dgisselq
                        end
1322
                `CT_READ_DATA: begin
1323
                        o_spi_wr <= 1'b0; // No more words to go, just to wait
1324
                        o_spi_req <= 1'b1;
1325 11 dgisselq
                        invalid_ack_pipe[0] <= 1'b0;
1326
                        if ((i_spi_valid)&&(!invalid_ack_pipe[3])) // for a value to read
1327 9 dgisselq
                        begin
1328
                                o_data_ack <= 1'b1;
1329
                                o_data <= i_spi_data;
1330
                                ctstate <= `CT_WAIT_FOR_IDLE;
1331
                        end end
1332
                default: begin // `CT_WAIT_FOR_IDLE
1333
                        o_spi_wr <= 1'b0;
1334
                        o_spi_req <= 1'b0;
1335
                        if (i_spi_stopped)
1336
                                ctstate <= `CT_IDLE;
1337
                        end
1338
                endcase
1339
        end
1340
 
1341
        // All of this is done in straight SPI mode, so our speed will always be zero
1342
        assign  o_spi_hold = 1'b0;
1343
        assign  o_spi_spd  = 1'b0;
1344
 
1345
endmodule
1346
 
1347
`define ID_IDLE                         5'h00
1348
`define ID_WAIT_ON_START_ID             5'h01
1349
`define ID_WAIT_ON_START_OTP            5'h02
1350
`define ID_WAIT_ON_START_OTP_WRITE      5'h03
1351
`define ID_READ_DATA_COMMAND            5'h04
1352
`define ID_GET_DATA                     5'h05
1353
`define ID_LOADED                       5'h06
1354
`define ID_LOADED_NEXT                  5'h07
1355
`define ID_OTP_SEND_DUMMY               5'h08
1356
`define ID_OTP_CLEAR                    5'h09
1357
`define ID_OTP_GET_DATA                 5'h0a
1358
`define ID_OTP_WRITE                    5'h0b
1359
`define ID_WAIT_ON_STOP                 5'h0c
1360
`define ID_REQ_STATUS                   5'h0d
1361
`define ID_REQ_STATUS_NEXT              5'h0e
1362
`define ID_READ_STATUS                  5'h0f
1363
//
1364
`define ID_FINAL_STOP                   5'h10
1365
 
1366
module  idotpqspi(i_clk, i_req, i_wr, i_pipewr, i_addr, i_data, o_bus_ack,
1367
                o_qspi_req, i_qspi_grant,
1368
                o_spi_wr, o_spi_hold, o_spi_word, o_spi_len,
1369
                o_spi_spd, o_spi_dir, i_spi_data, i_spi_valid,
1370
                i_spi_busy, i_spi_stopped, o_data_ack, o_data, o_loaded,
1371
                o_wip);
1372
        input                   i_clk;
1373
        input                   i_req, i_wr, i_pipewr;
1374
        input           [4:0]    i_addr;
1375
        input           [31:0]   i_data;
1376
        output  reg             o_bus_ack, o_qspi_req;
1377
        input                   i_qspi_grant;
1378
        output  reg             o_spi_wr, o_spi_hold;
1379
        output  reg     [31:0]   o_spi_word;
1380
        output  reg     [1:0]    o_spi_len;
1381
        output  wire            o_spi_spd;
1382
        output  reg             o_spi_dir;
1383
        input           [31:0]   i_spi_data;
1384
        input                   i_spi_valid, i_spi_busy, i_spi_stopped;
1385
        output  reg             o_data_ack;
1386
        output  reg     [31:0]   o_data;
1387
        output  wire            o_loaded;
1388
        output  reg             o_wip;
1389
 
1390
        reg     id_loaded;
1391
        initial id_loaded = 1'b0;
1392
        assign  o_loaded= id_loaded;
1393
 
1394
/*
1395
        // Only the ID register will be kept in memory, OTP will be read
1396
        // or written upon request
1397
        always @(posedge i_clk)
1398
                if (i_addr[4])
1399
                        o_data <= otpmem[i_addr[3:0]];
1400
                else
1401
                        o_data <= idmem[i_addr[2:0]];
1402
 
1403
        always @(posedge i_clk)
1404
                if ((otp_loaded)&&(i_req)&&(i_addr[4]))
1405
                        o_data_ack <= 1'b1;
1406
                else if ((id_loaded)&&(i_req)&&(~i_addr[4]))
1407
                        o_data_ack <= idmem[i_addr[2:0]];
1408
                else
1409
                        o_data_ack <= 1'b0;
1410
*/
1411
 
1412
        reg     otp_read_request, id_read_request, accepted, otp_wr_request,
1413
                id_read_device, last_id_read;
1414
        reg     [4:0]    req_addr;
1415
        reg     [2:0]    lcl_id_addr;
1416
        reg     [4:0]    id_state;
1417
        always @(posedge i_clk)
1418
        begin
1419
                otp_read_request <= (i_req)&&(~i_wr)&&((i_addr[4])||(i_addr[3:0]==4'hf));
1420
                last_id_read     <= (i_req)&&(~i_addr[4])&&(i_addr[3:0]!=4'hf);
1421
                id_read_request  <= (i_req)&&(~i_addr[4])&&(i_addr[3:0]!=4'hf)&&(~last_id_read);
1422
                id_read_device   <= (i_req)&&(~i_addr[4])&&(i_addr[3:0]!=4'hf)&&(~id_loaded);
1423
                accepted <= (~i_spi_busy)&&(i_qspi_grant)&&(o_spi_wr)&&(~accepted);
1424
 
1425
                otp_wr_request <= (i_req)&&(i_wr)&&((i_addr[4])||(i_addr[3:0]==4'hf));
1426
 
1427
                if (id_state == `ID_IDLE)
1428
                        req_addr <= (i_addr[4:0]==5'h0f) ? 5'h10
1429
                                : { 1'b0, i_addr[3:0] };
1430
        end
1431
 
1432
        reg     last_addr;
1433
        always @(posedge i_clk)
1434
                last_addr <= (lcl_id_addr >= 3'h4);
1435
 
1436
        reg     [31:0]   idmem[0:5];
1437
        reg     [31:0]   r_data;
1438
 
1439
        // Now, quickly, let's deal with the fact that the data from the
1440
        // bus comes one clock later ...
1441
        reg     nxt_data_ack, nxt_data_spi;
1442
        reg     [31:0]   nxt_data;
1443
 
1444 11 dgisselq
        reg     set_val, chk_wip, first_valid;
1445 9 dgisselq
        reg     [2:0]    set_addr;
1446 11 dgisselq
        reg     [3:0]    invalid_ack_pipe;
1447 9 dgisselq
 
1448
        always @(posedge i_clk)
1449
        begin // Depends upon state[4], otp_rd, otp_wr, otp_pipe, id_req, accepted, last_addr
1450
                o_bus_ack <= 1'b0;
1451
                // o_data_ack <= 1'b0;
1452
                o_spi_hold <= 1'b0;
1453
                nxt_data_ack <= 1'b0;
1454
                nxt_data_spi <= 1'b0;
1455
                chk_wip      <= 1'b0;
1456
                set_val <= 1'b0;
1457 11 dgisselq
                invalid_ack_pipe <= { invalid_ack_pipe[2:0], accepted };
1458 9 dgisselq
                if ((id_loaded)&&(id_read_request))
1459
                begin
1460
                        nxt_data_ack <= 1'b1;
1461
                        o_bus_ack  <= 1'b1;
1462
                end
1463
                nxt_data <= idmem[i_addr[2:0]];
1464
                o_spi_wr <= 1'b0; // By default, we send nothing
1465
                case(id_state)
1466
                `ID_IDLE: begin
1467
                        o_qspi_req <= 1'b0;
1468
                        o_spi_dir <= 1'b0; // Write to SPI
1469
                        lcl_id_addr <= 3'h0;
1470
                        o_spi_word[23:7] <= 17'h00;
1471
                        o_spi_word[6:0] <= { req_addr[4:0], 2'b00 };
1472
                        r_data <= i_data;
1473
                        o_wip <= 1'b0;
1474 11 dgisselq
                        first_valid <= 1'b0;
1475 9 dgisselq
                        if (otp_read_request)
1476
                        begin
1477
                                // o_spi_word <= { 8'h48, 8'h00, 8'h00, 8'h00 };
1478
                                id_state <= `ID_WAIT_ON_START_OTP;
1479
                                o_bus_ack <= 1'b1;
1480
                        end else if (otp_wr_request)
1481
                        begin
1482
                                o_bus_ack <= 1'b1;
1483
                                // o_data_ack <= 1'b1;
1484
                                nxt_data_ack <= 1'b1;
1485
                                id_state <= `ID_WAIT_ON_START_OTP_WRITE;
1486
                        end else if (id_read_device)
1487
                        begin
1488
                                id_state <= `ID_WAIT_ON_START_ID;
1489
                                o_bus_ack <= 1'b0;
1490
                                o_spi_word[31:24] <= 8'h9f;
1491
                        end end
1492
                `ID_WAIT_ON_START_ID: begin
1493
                        o_spi_wr <= 1'b1;
1494
                        o_qspi_req <= 1'b1;
1495
                        o_spi_len <= 2'b0; // 8 bits
1496
                        if (accepted)
1497
                                id_state <= `ID_READ_DATA_COMMAND;
1498
                        end
1499
                `ID_WAIT_ON_START_OTP: begin
1500
                        o_spi_wr <= 1'b1;
1501
                        o_spi_word[31:24] <= 8'h4B;
1502
                        o_qspi_req <= 1'b1;
1503
                        o_spi_len <= 2'b11; // 32 bits
1504
                        o_spi_word[6:0] <= { req_addr[4:0], 2'b00 };
1505
                        if (accepted) // Read OTP command was just sent
1506
                                id_state <= `ID_OTP_SEND_DUMMY;
1507
                        end
1508
                `ID_WAIT_ON_START_OTP_WRITE: begin
1509
                        o_spi_wr <= 1'b1;
1510
                        o_qspi_req <= 1'b1;
1511
                        o_wip <= 1'b1;
1512
                        o_spi_len <= 2'b11; // 32 bits
1513
                        o_spi_word[31:24] <= 8'h42;
1514
                        if (accepted) // Read OTP command was just sent
1515
                                id_state <= `ID_OTP_WRITE;
1516
                        end
1517
                `ID_READ_DATA_COMMAND: begin
1518
                        o_spi_len <= 2'b11; // 32-bits
1519 11 dgisselq
                        o_spi_wr <= 1'b1; // Still transmitting
1520 9 dgisselq
                        o_spi_dir <= 1'b1; // Read from SPI
1521
                        o_qspi_req <= 1'b1;
1522
                        if (accepted)
1523
                                id_state <= `ID_GET_DATA;
1524 11 dgisselq
                        first_valid <= 1'b0;
1525 9 dgisselq
                        end
1526
                `ID_GET_DATA: begin
1527
                        o_spi_len <= 2'b11; // 32-bits
1528
                        o_spi_wr <= (~last_addr); // Still transmitting
1529
                        o_spi_dir <= 1'b1; // Read from SPI
1530
                        o_qspi_req <= 1'b1;
1531 11 dgisselq
                        invalid_ack_pipe[0] <= 1'b0;
1532
                        if((i_spi_valid)&&(!invalid_ack_pipe[3]))
1533 9 dgisselq
                        begin
1534
                                set_val <= 1'b1;
1535
                                set_addr <= lcl_id_addr[2:0];
1536
                                // idmem[lcl_id_addr[2:0]] <= i_spi_data;
1537
                                lcl_id_addr <= lcl_id_addr + 3'h1;
1538
                                if (last_addr)
1539
                                        id_state <= `ID_LOADED;
1540
                        end end
1541
                `ID_LOADED: begin
1542
                        id_loaded <= 1'b1;
1543
                        o_bus_ack  <= 1'b1;
1544
                        o_spi_wr   <= 1'b0;
1545
                        nxt_data_ack <= 1'b1;
1546
                        id_state   <= `ID_LOADED_NEXT;
1547
                        end
1548
                `ID_LOADED_NEXT: begin
1549
                        o_spi_len <= 2'b11; // 32-bits
1550
                        o_bus_ack  <= 1'b0;
1551
                        o_spi_wr   <= 1'b0;
1552
                        nxt_data_ack <= 1'b1;
1553
                        id_state   <= `ID_IDLE;
1554
                        end
1555
                `ID_OTP_SEND_DUMMY: begin
1556
                        o_spi_len <= 2'b00; // 1 byte
1557
                        o_spi_wr  <= 1'b1; // Still writing
1558
                        o_spi_dir <= 1'b0; // Write to SPI
1559
                        if (accepted) // Wait for the command to be accepted
1560
                                id_state <= `ID_OTP_CLEAR;
1561
                        end
1562
                `ID_OTP_CLEAR: begin
1563
                        o_spi_wr  <= 1'b1; // Still writing
1564
                        o_spi_dir <= 1'b1; // Read from SPI
1565 11 dgisselq
                        o_spi_len <= 2'b11; // Read 32 bits
1566 9 dgisselq
                        if (accepted)
1567
                                id_state <= `ID_OTP_GET_DATA;
1568
                        end
1569
                `ID_OTP_GET_DATA: begin
1570 11 dgisselq
                        invalid_ack_pipe[0] <= 1'b0;
1571
                        if ((i_spi_valid)&&(!invalid_ack_pipe[3]))
1572 9 dgisselq
                        begin
1573
                                id_state <= `ID_FINAL_STOP;
1574
                                nxt_data_ack <= 1'b1;
1575
                                nxt_data_spi <= 1'b1;
1576
                        end end
1577
                `ID_OTP_WRITE: begin
1578
                        o_spi_wr  <= 1'b1;
1579
                        o_spi_len <= 2'b11;
1580
                        o_spi_dir <= 1'b0; // Write to SPI
1581
                        o_spi_word <= r_data;
1582
                        // o_bus_ack  <= (otp_wr_request)&&(accepted)&&(i_pipewr);
1583
                        // o_data_ack <= (otp_wr_request)&&(accepted);
1584
                        if (accepted) // &&(~i_pipewr)
1585
                                id_state <= `ID_WAIT_ON_STOP;
1586
                        else if(accepted)
1587
                        begin
1588
                                o_spi_word <= i_data;
1589
                                r_data <= i_data;
1590
                        end end
1591
                `ID_WAIT_ON_STOP: begin
1592
                        o_spi_wr <= 1'b0;
1593
                        if (i_spi_stopped)
1594
                                id_state <= `ID_REQ_STATUS;
1595
                        end
1596
                `ID_REQ_STATUS: begin
1597
                        o_spi_wr <= 1'b1;
1598
                        o_spi_hold <= 1'b0;
1599
                        o_spi_word[31:24] <= 8'h05;
1600
                        o_spi_dir <= 1'b0;
1601
                        o_spi_len <= 2'b00;
1602
                        if (accepted)
1603
                                id_state <= `ID_REQ_STATUS_NEXT;
1604
                        end
1605
                `ID_REQ_STATUS_NEXT: begin
1606
                        o_spi_wr <= 1'b1;
1607
                        o_spi_hold <= 1'b0;
1608
                        o_spi_dir <= 1'b1; // Read
1609
                        o_spi_len <= 2'b00; // 8 bits
1610
                        // o_spi_word <= dont care
1611
                        if (accepted)
1612
                                id_state <= `ID_READ_STATUS;
1613
                        end
1614
                `ID_READ_STATUS: begin
1615
                        o_spi_wr <= 1'b1;
1616
                        o_spi_hold <= 1'b0;
1617
                        o_spi_dir <= 1'b1; // Read
1618
                        o_spi_len <= 2'b00; // 8 bits
1619
                        // o_spi_word <= dont care
1620 11 dgisselq
                        invalid_ack_pipe[0] <= 1'b0;
1621
                        if ((i_spi_valid)&&(~invalid_ack_pipe[3]))
1622 9 dgisselq
                                chk_wip <= 1'b1;
1623
                        if ((chk_wip)&&(~i_spi_data[0]))
1624
                        begin
1625
                                o_wip <= 1'b0;
1626
                                id_state <= `ID_FINAL_STOP;
1627
                        end end
1628
                default: begin // ID_FINAL_STOP
1629
                        o_bus_ack <= 1'b0;
1630
                        nxt_data_ack <= 1'b0;
1631
                        o_qspi_req <= 1'b0;
1632
                        o_spi_wr <= 1'b0;
1633
                        o_spi_hold <= 1'b0;
1634
                        o_spi_dir <= 1'b1; // Read
1635
                        o_spi_len <= 2'b00; // 8 bits
1636
                        // o_spi_word <= dont care
1637
                        if (i_spi_stopped)
1638
                                id_state <= `ID_IDLE;
1639
                        end
1640
                endcase
1641
        end
1642
 
1643
        always @(posedge i_clk)
1644
        begin
1645
                if (nxt_data_ack)
1646
                        o_data <= (nxt_data_spi)?i_spi_data : nxt_data;
1647
                o_data_ack <= nxt_data_ack;
1648
        end
1649
 
1650
        always @(posedge i_clk)
1651
                if (set_val)
1652
                        idmem[set_addr] <= i_spi_data;
1653
 
1654
        assign  o_spi_spd = 1'b0; // Slow, 1-bit at a time
1655
 
1656
endmodule
1657
 
1658
 
1659
 

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