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///////////////////////////////////////////////////////////////////////////
//
// Filename:    llqspi.v
//
// Project:     Wishbone Controlled Quad SPI Flash Controller
//
// Purpose:     Reads/writes a word (user selectable number of bytes) of data
//              to/from a Quad SPI port.  The port is understood to be 
//              a normal SPI port unless the driver requests four bit mode.
//              When not in use, unlike our previous SPI work, no bits will
//              toggle.
//
// Creator:     Dan Gisselquist
//              Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////
`define EQSPI_IDLE      3'h0
`define EQSPI_START     3'h1
`define EQSPI_BITS      3'h2
`define EQSPI_READY     3'h3
`define EQSPI_HOLDING   3'h4
`define EQSPI_STOP      3'h5
`define EQSPI_STOP_B    3'h6
`define EQSPI_RECYCLE   3'h7
 
// Modes
`define EQSPI_MOD_SPI   2'b00
`define EQSPI_MOD_QOUT  2'b10   // Write
`define EQSPI_MOD_QIN   2'b11   // Read
 
module  lleqspi(i_clk,
                // Module interface
                i_wr, i_hold, i_word, i_len, i_spd, i_dir, i_recycle,
                        o_word, o_valid, o_busy,
                // QSPI interface
                o_sck, o_cs_n, o_mod, o_dat, i_dat);
        input                   i_clk;
        // Chip interface
        //      Can send info
        //              i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,
        //                      i_word = { 1'b0, 32'info to send },
        //                      i_len = # of bytes in word-1
        input                   i_wr, i_hold;
        input           [31:0]   i_word;
        input           [1:0]    i_len;  // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits
        input                   i_spd; // 0 -> normal QPI, 1 -> QSPI
        input                   i_dir; // 0 -> read, 1 -> write to SPI
        input                   i_recycle; // 0 = 20ns, 1 = 50ns
        output  reg     [31:0]   o_word;
        output  wire            o_valid;
        output  reg             o_busy;
        // Interface with the QSPI lines
        output  reg             o_sck;
        output  reg             o_cs_n;
        output  reg     [1:0]    o_mod;
        output  reg     [3:0]    o_dat;
        input           [3:0]    i_dat;
 
        // output       wire    [22:0]  o_dbg;
        // assign       o_dbg = { state, spi_len,
                // o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };
 
        // Timing:
        //
        //      Tick    Clk     BSY/WR  CS_n    BIT/MO  STATE
        //       0      1       0/0     1        -      
        //       1      1       0/1     1        -
        //       2      1       1/0     0         -      QSPI_START
        //       3      0        1/0     0         -      QSPI_START
        //       4      0        1/0     0         0      QSPI_BITS
        //       5      1       1/0     0         0      QSPI_BITS
        //       6      0        1/0     0         1      QSPI_BITS
        //       7      1       1/0     0         1      QSPI_BITS
        //       8      0        1/0     0         2      QSPI_BITS
        //       9      1       1/0     0         2      QSPI_BITS
        //      10      0        1/0     0         3      QSPI_BITS
        //      11      1       1/0     0         3      QSPI_BITS
        //      12      0        1/0     0         4      QSPI_BITS
        //      13      1       1/0     0         4      QSPI_BITS
        //      14      0        1/0     0         5      QSPI_BITS
        //      15      1       1/0     0         5      QSPI_BITS
        //      16      0        1/0     0         6      QSPI_BITS
        //      17      1       1/1     0         6      QSPI_BITS
        //      18      0        1/1     0         7      QSPI_READY
        //      19      1       0/1     0         7      QSPI_READY
        //      20      0        1/0/V   0         8      QSPI_BITS
        //      21      1       1/0     0         8      QSPI_BITS
        //      22      0        1/0     0         9      QSPI_BITS
        //      23      1       1/0     0         9      QSPI_BITS
        //      24      0        1/0     0        10      QSPI_BITS
        //      25      1       1/0     0        10      QSPI_BITS
        //      26      0        1/0     0        11      QSPI_BITS
        //      27      1       1/0     0        11      QSPI_BITS
        //      28      0        1/0     0        12      QSPI_BITS
        //      29      1       1/0     0        12      QSPI_BITS
        //      30      0        1/0     0        13      QSPI_BITS
        //      31      1       1/0     0        13      QSPI_BITS
        //      32      0        1/0     0        14      QSPI_BITS
        //      33      1       1/0     0        14      QSPI_BITS
        //      34      0        1/0     0        15      QSPI_READY
        //      35      1       1/0     0        15      QSPI_READY
        //      36      1       1/0/V   0         -      QSPI_STOP
        //      37      1       1/0     0         -      QSPI_STOPB
        //      38      1       1/0     1        -      QSPI_IDLE
        //      39      1       0/0     1        -
        // Now, let's switch from single bit to quad mode
        //      40      1       0/0     1        -      QSPI_IDLE
        //      41      1       0/1     1        -      QSPI_IDLE
        //      42      1       1/0     0         -      QSPI_START
        //      43      0        1/0     0         -      QSPI_START
        //      44      0        1/0     0         0      QSPI_BITS
        //      45      1       1/0     0         0      QSPI_BITS
        //      46      0        1/0     0         1      QSPI_BITS
        //      47      1       1/0     0         1      QSPI_BITS
        //      48      0        1/0     0         2      QSPI_BITS
        //      49      1       1/0     0         2      QSPI_BITS
        //      50      0        1/0     0         3      QSPI_BITS
        //      51      1       1/0     0         3      QSPI_BITS
        //      52      0        1/0     0         4      QSPI_BITS
        //      53      1       1/0     0         4      QSPI_BITS
        //      54      0        1/0     0         5      QSPI_BITS
        //      55      1       1/0     0         5      QSPI_BITS
        //      56      0        1/0     0         6      QSPI_BITS
        //      57      1       1/1/QR  0         6      QSPI_BITS
        //      58      0        1/1/QR  0         7      QSPI_READY
        //      59      1       0/1/QR  0         7      QSPI_READY
        //      60      0        1/0/?/V 0         8-11   QSPI_BITS
        //      61      1       1/0/?   0         8-11   QSPI_BITS
        //      62      0        1/0/?   0         12-15  QSPI_BITS
        //      63      1       1/0/?   0         12-15  QSPI_BITS
        //      64      1       1/0/?/V 0        -       QSPI_STOP
        //      65      1       1/0/?   0        -       QSPI_STOPB
        //      66      1       1/0/?   1       -       QSPI_IDLE
        //      67      1       0/0     1       -       QSPI_IDLE
        // Now let's try something entirely in Quad read mode, from the
        // beginning
        //      68      1       0/1/QR  1       -       QSPI_IDLE
        //      69      1       1/0     0        -       QSPI_START
        //      70      0        1/0     0        -       QSPI_START
        //      71      0        1/0     0        0-3     QSPI_BITS
        //      72      1       1/0     0        0-3     QSPI_BITS
        //      73      0        1/1/QR  0        4-7     QSPI_BITS
        //      74      1       0/1/QR  0        4-7     QSPI_BITS
        //      75      0        1/?/?/V 0        8-11    QSPI_BITS
        //      76      1       1/?/?   0        8-11    QSPI_BITS
        //      77      0        1/1/QR  0        12-15   QSPI_BITS
        //      78      1       0/1/QR  0        12-15   QSPI_BITS
        //      79      0        1/?/?/V 0        16-19   QSPI_BITS
        //      80      1       1/0     0        16-19   QSPI_BITS
        //      81      0        1/0     0        20-23   QSPI_BITS
        //      82      1       1/0     0        20-23   QSPI_BITS
        //      83      1       1/0/V   0        -       QSPI_STOP
        //      84      1       1/0     0        -       QSPI_STOPB
        //      85      1       1/0     1       -       QSPI_IDLE
        //      86      1       0/0     1       -       QSPI_IDLE
 
        wire    i_miso;
        assign  i_miso = i_dat[1];
 
        // These are used in creating a delayed input.
        reg             rd_input, rd_spd, rd_valid;
 
        reg             r_spd, r_dir;
        reg     [3:0]    r_recycle;
        reg     [5:0]    spi_len;
        reg     [31:0]   r_word;
        reg     [30:0]   r_input;
        reg     [2:0]    state;
        initial state = `EQSPI_IDLE;
        initial o_sck   = 1'b1;
        initial o_cs_n  = 1'b1;
        initial o_dat   = 4'hd;
        initial rd_valid = 1'b0;
        initial o_busy  = 1'b0;
        initial r_input = 31'h000;
        initial rd_valid = 1'b0;
        always @(posedge i_clk)
        begin
                rd_input <= 1'b0;
                rd_spd   <= r_spd;
                rd_valid <= 1'b0;
 
                if ((state == `EQSPI_IDLE)&&(o_sck))
                begin
                        o_cs_n <= 1'b1;
                        o_busy  <= 1'b0;
                        o_mod <= `EQSPI_MOD_SPI;
                        r_word <= i_word;
                        r_spd <= i_spd;
                        r_dir <= i_dir;
                        o_dat <= 4'hc;
                        r_recycle <= (i_recycle)? 4'h8 : 4'h2; // 4'ha : 4'h4
                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
                        o_sck <= 1'b1;
                        if (i_wr)
                        begin
                                state <= `EQSPI_START;
                                o_cs_n <= 1'b0;
                                o_busy <= 1'b1;
                        end
                end else if (state == `EQSPI_START)
                begin // We come in here with sck high, stay here 'til sck is low
                        o_sck <= 1'b0;
                        if (o_sck == 1'b0)
                        begin
                                state <= `EQSPI_BITS;
                                spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );
                                if (r_spd)
                                        r_word <= { r_word[27:0], 4'h0 };
                                else
                                        r_word <= { r_word[30:0], 1'b0 };
                        end
                        o_mod <= (r_spd) ? { 1'b1, r_dir } : `EQSPI_MOD_SPI;
                        o_cs_n <= 1'b0;
                        o_busy <= 1'b1;
                        if (r_spd)
                                o_dat <= r_word[31:28];
                        else
                                o_dat <= { 3'b110, r_word[31] };
                end else if (~o_sck)
                begin
                        o_sck <= 1'b1;
                        o_busy <= ((state != `EQSPI_READY)||(~i_wr));
                end else if (state == `EQSPI_BITS)
                begin
                        // Should enter into here with at least a spi_len
                        // of one, perhaps more
                        o_sck <= 1'b0;
                        o_busy <= 1'b1;
                        if (r_spd)
                        begin
                                o_dat <= r_word[31:28];
                                r_word <= { r_word[27:0], 4'h0 };
                                spi_len <= spi_len - 6'h4;
                                if (spi_len == 6'h4)
                                        state <= `EQSPI_READY;
                        end else begin
                                o_dat <= { 3'b110, r_word[31] };
                                r_word <= { r_word[30:0], 1'b0 };
                                spi_len <= spi_len - 6'h1;
                                if (spi_len == 6'h1)
                                        state <= `EQSPI_READY;
                        end
 
                        rd_input <= 1'b1;
                end else if (state == `EQSPI_READY)
                begin
                        o_cs_n <= 1'b0;
                        o_busy <= 1'b1;
                        // This is the state on the last clock (both low and
                        // high clocks) of the data.  Data is valid during
                        // this state.  Here we chose to either STOP or
                        // continue and transmit more.
                        o_sck <= (i_hold); // No clocks while holding
                        if((~o_busy)&&(i_wr))// Acknowledge a new request
                        begin
                                state <= `EQSPI_BITS;
                                o_busy <= 1'b1;
                                o_sck <= 1'b0;
 
                                // Read the new request off the bus
                                r_spd <= i_spd;
                                r_dir <= i_dir;
                                // Set up the first bits on the bus
                                o_mod <= (i_spd) ? { 1'b1, i_dir } : `EQSPI_MOD_SPI;
                                if (i_spd)
                                begin
                                        o_dat <= i_word[31:28];
                                        r_word <= { i_word[27:0], 4'h0 };
                                        // spi_len <= spi_len - 4;
                                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
                                                - 6'h4;
                                end else begin
                                        o_dat <= { 3'b110, i_word[31] };
                                        r_word <= { i_word[30:0], 1'b0 };
                                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
                                                - 6'h1;
                                end
 
                                // Read a bit upon any transition
                                rd_input <= 1'b1;
                                rd_valid <= 1'b1;
                        end else begin
                                o_sck <= 1'b1;
                                state <= (i_hold)?`EQSPI_HOLDING : `EQSPI_STOP;
                                o_busy <= (~i_hold);
 
                                // Read a bit upon any transition
                                rd_valid <= 1'b1;
                                rd_input <= 1'b1;
                        end
                end else if (state == `EQSPI_HOLDING)
                begin
                        // We need this state so that the o_valid signal
                        // can get strobed with our last result.  Otherwise
                        // we could just sit in READY waiting for a new command.
                        //
                        // Incidentally, the change producing this state was
                        // the result of a nasty race condition.  See the
                        // commends in wbqspiflash for more details.
                        //
                        rd_valid <= 1'b0;
                        o_cs_n <= 1'b0;
                        o_busy <= 1'b0;
                        if((~o_busy)&&(i_wr))// Acknowledge a new request
                        begin
                                state  <= `EQSPI_BITS;
                                o_busy <= 1'b1;
                                o_sck  <= 1'b0;
 
                                // Read the new request off the bus
                                r_spd <= i_spd;
                                r_dir <= i_dir;
                                // Set up the first bits on the bus
                                o_mod<=(i_spd)?{ 1'b1, i_dir } : `EQSPI_MOD_SPI;
                                if (i_spd)
                                begin
                                        o_dat <= i_word[31:28];
                                        r_word <= { i_word[27:0], 4'h0 };
                                        spi_len<= { 1'b0, i_len, 3'b100 };
                                end else begin
                                        o_dat <= { 3'b110, i_word[31] };
                                        r_word <= { i_word[30:0], 1'b0 };
                                        spi_len<= { 1'b0, i_len, 3'b111 };
                                end
                        end else begin
                                o_sck <= 1'b1;
                                state <= (i_hold)?`EQSPI_HOLDING : `EQSPI_STOP;
                                o_busy <= (~i_hold);
                        end
                end else if (state == `EQSPI_STOP)
                begin
                        o_sck   <= 1'b1; // Stop the clock
                        rd_valid <= 1'b0; // Output may have just been valid, but no more
                        o_busy  <= 1'b1; // Still busy till port is clear
                        state <= `EQSPI_STOP_B;
                        // Can't change modes for at least one cycle
                        // o_mod <= `EQSPI_MOD_SPI;
                end else if (state == `EQSPI_STOP_B)
                begin
                        o_cs_n <= 1'b1;
                        o_sck <= 1'b1;
                        // Do I need this????
                        // spi_len <= 3; // Minimum CS high time before next cmd
                        state <= `EQSPI_RECYCLE;
                        o_busy <= 1'b1;
                        o_mod <= `EQSPI_MOD_SPI;
                end else begin // Recycle state
                        r_recycle <= r_recycle - 1'b1;
                        o_cs_n <= 1'b1;
                        o_sck <= 1'b1;
                        o_busy <= 1'b1;
                        o_mod <= `EQSPI_MOD_SPI;
                        o_dat <= 4'hc;
                        if (r_recycle[3:1] == 3'h0)
                                state <= `EQSPI_IDLE;
                end
                /*
                end else begin // Invalid states, should never get here
                        state   <= `EQSPI_STOP;
                        o_valid <= 1'b0;
                        o_busy  <= 1'b1;
                        o_cs_n  <= 1'b1;
                        o_sck   <= 1'b1;
                        o_mod   <= `EQSPI_MOD_SPI;
                        o_dat   <= 4'hd;
                end
                */
        end
 
        always @(posedge i_clk)
        begin
                if ((state == `EQSPI_IDLE)||(rd_valid))
                        r_input <= 31'h00;
                else if ((rd_input)&&(r_spd))
                        r_input <= { r_input[26:0], i_dat };
                else if (rd_input)
                        r_input <= { r_input[29:0], i_miso };
 
                if ((rd_valid)&&(r_spd))
                        o_word  <= { r_input[27:0], i_dat };
                else if (rd_valid)
                        o_word  <= { r_input[30:0], i_miso };
        end
 
        assign  o_valid = rd_valid;
 
endmodule
 

Line No.	Rev	Author	Line
1	9	dgisselq	`///////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// Filename: llqspi.v`
4			`//`
5			`// Project: Wishbone Controlled Quad SPI Flash Controller`
6			`//`
7			`// Purpose: Reads/writes a word (user selectable number of bytes) of data`
8			`// to/from a Quad SPI port. The port is understood to be`
9			`// a normal SPI port unless the driver requests four bit mode.`
10			`// When not in use, unlike our previous SPI work, no bits will`
11			`// toggle.`
12			`//`
13			`// Creator: Dan Gisselquist`
14			`// Gisselquist Technology, LLC`
15			`//`
16			`///////////////////////////////////////////////////////////////////////////`
17			`//`
18	10	dgisselq	`// Copyright (C) 2015-2016, Gisselquist Technology, LLC`
19	9	dgisselq	`//`
20			`// This program is free software (firmware): you can redistribute it and/or`
21			`// modify it under the terms of the GNU General Public License as published`
22			`// by the Free Software Foundation, either version 3 of the License, or (at`
23			`// your option) any later version.`
24			`//`
25			`// This program is distributed in the hope that it will be useful, but WITHOUT`
26			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
27			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
28			`// for more details.`
29			`//`
30			`// You should have received a copy of the GNU General Public License along`
31			`// with this program. (It's in the $(ROOT)/doc directory, run make with no`
32			`// target there if the PDF file isn't present.) If not, see`
33			`// <http://www.gnu.org/licenses/> for a copy.`
34			`//`
35			`// License: GPL, v3, as defined and found on www.gnu.org,`
36			`// http://www.gnu.org/licenses/gpl.html`
37			`//`
38			`//`
39			`///////////////////////////////////////////////////////////////////////////`
40	10	dgisselq	`define EQSPI_IDLE 3'h0
41			`define EQSPI_START 3'h1
42			`define EQSPI_BITS 3'h2
43			`define EQSPI_READY 3'h3
44			`define EQSPI_HOLDING 3'h4
45			`define EQSPI_STOP 3'h5
46			`define EQSPI_STOP_B 3'h6
47			`define EQSPI_RECYCLE 3'h7
48	9	dgisselq
49			`// Modes`
50	10	dgisselq	`define EQSPI_MOD_SPI 2'b00
51			`define EQSPI_MOD_QOUT 2'b10 // Write
52			`define EQSPI_MOD_QIN 2'b11 // Read
53	9	dgisselq
54	10	dgisselq	`module lleqspi(i_clk,`
55	9	dgisselq	`// Module interface`
56			`i_wr, i_hold, i_word, i_len, i_spd, i_dir, i_recycle,`
57			`o_word, o_valid, o_busy,`
58			`// QSPI interface`
59			`o_sck, o_cs_n, o_mod, o_dat, i_dat);`
60			`input i_clk;`
61			`// Chip interface`
62			`// Can send info`
63			`// i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,`
64			`// i_word = { 1'b0, 32'info to send },`
65			`// i_len = # of bytes in word-1`
66			`input i_wr, i_hold;`
67			`input [31:0] i_word;`
68			`input [1:0] i_len; // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits`
69			`input i_spd; // 0 -> normal QPI, 1 -> QSPI`
70			`input i_dir; // 0 -> read, 1 -> write to SPI`
71			`input i_recycle; // 0 = 20ns, 1 = 50ns`
72			`output reg [31:0] o_word;`
73			`output wire o_valid;`
74			`output reg o_busy;`
75			`// Interface with the QSPI lines`
76			`output reg o_sck;`
77			`output reg o_cs_n;`
78			`output reg [1:0] o_mod;`
79			`output reg [3:0] o_dat;`
80			`input [3:0] i_dat;`
81
82			`// output wire [22:0] o_dbg;`
83			`// assign o_dbg = { state, spi_len,`
84			`// o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };`
85
86			`// Timing:`
87			`//`
88			`// Tick Clk BSY/WR CS_n BIT/MO STATE`
89			`// 0 1 0/0 1 -`
90			`// 1 1 0/1 1 -`
91			`// 2 1 1/0 0 - QSPI_START`
92			`// 3 0 1/0 0 - QSPI_START`
93			`// 4 0 1/0 0 0 QSPI_BITS`
94			`// 5 1 1/0 0 0 QSPI_BITS`
95			`// 6 0 1/0 0 1 QSPI_BITS`
96			`// 7 1 1/0 0 1 QSPI_BITS`
97			`// 8 0 1/0 0 2 QSPI_BITS`
98			`// 9 1 1/0 0 2 QSPI_BITS`
99			`// 10 0 1/0 0 3 QSPI_BITS`
100			`// 11 1 1/0 0 3 QSPI_BITS`
101			`// 12 0 1/0 0 4 QSPI_BITS`
102			`// 13 1 1/0 0 4 QSPI_BITS`
103			`// 14 0 1/0 0 5 QSPI_BITS`
104			`// 15 1 1/0 0 5 QSPI_BITS`
105			`// 16 0 1/0 0 6 QSPI_BITS`
106			`// 17 1 1/1 0 6 QSPI_BITS`
107			`// 18 0 1/1 0 7 QSPI_READY`
108			`// 19 1 0/1 0 7 QSPI_READY`
109			`// 20 0 1/0/V 0 8 QSPI_BITS`
110			`// 21 1 1/0 0 8 QSPI_BITS`
111			`// 22 0 1/0 0 9 QSPI_BITS`
112			`// 23 1 1/0 0 9 QSPI_BITS`
113			`// 24 0 1/0 0 10 QSPI_BITS`
114			`// 25 1 1/0 0 10 QSPI_BITS`
115			`// 26 0 1/0 0 11 QSPI_BITS`
116			`// 27 1 1/0 0 11 QSPI_BITS`
117			`// 28 0 1/0 0 12 QSPI_BITS`
118			`// 29 1 1/0 0 12 QSPI_BITS`
119			`// 30 0 1/0 0 13 QSPI_BITS`
120			`// 31 1 1/0 0 13 QSPI_BITS`
121			`// 32 0 1/0 0 14 QSPI_BITS`
122			`// 33 1 1/0 0 14 QSPI_BITS`
123			`// 34 0 1/0 0 15 QSPI_READY`
124			`// 35 1 1/0 0 15 QSPI_READY`
125			`// 36 1 1/0/V 0 - QSPI_STOP`
126			`// 37 1 1/0 0 - QSPI_STOPB`
127			`// 38 1 1/0 1 - QSPI_IDLE`
128			`// 39 1 0/0 1 -`
129			`// Now, let's switch from single bit to quad mode`
130			`// 40 1 0/0 1 - QSPI_IDLE`
131			`// 41 1 0/1 1 - QSPI_IDLE`
132			`// 42 1 1/0 0 - QSPI_START`
133			`// 43 0 1/0 0 - QSPI_START`
134			`// 44 0 1/0 0 0 QSPI_BITS`
135			`// 45 1 1/0 0 0 QSPI_BITS`
136			`// 46 0 1/0 0 1 QSPI_BITS`
137			`// 47 1 1/0 0 1 QSPI_BITS`
138			`// 48 0 1/0 0 2 QSPI_BITS`
139			`// 49 1 1/0 0 2 QSPI_BITS`
140			`// 50 0 1/0 0 3 QSPI_BITS`
141			`// 51 1 1/0 0 3 QSPI_BITS`
142			`// 52 0 1/0 0 4 QSPI_BITS`
143			`// 53 1 1/0 0 4 QSPI_BITS`
144			`// 54 0 1/0 0 5 QSPI_BITS`
145			`// 55 1 1/0 0 5 QSPI_BITS`
146			`// 56 0 1/0 0 6 QSPI_BITS`
147			`// 57 1 1/1/QR 0 6 QSPI_BITS`
148			`// 58 0 1/1/QR 0 7 QSPI_READY`
149			`// 59 1 0/1/QR 0 7 QSPI_READY`
150			`// 60 0 1/0/?/V 0 8-11 QSPI_BITS`
151			`// 61 1 1/0/? 0 8-11 QSPI_BITS`
152			`// 62 0 1/0/? 0 12-15 QSPI_BITS`
153			`// 63 1 1/0/? 0 12-15 QSPI_BITS`
154			`// 64 1 1/0/?/V 0 - QSPI_STOP`
155			`// 65 1 1/0/? 0 - QSPI_STOPB`
156			`// 66 1 1/0/? 1 - QSPI_IDLE`
157			`// 67 1 0/0 1 - QSPI_IDLE`
158			`// Now let's try something entirely in Quad read mode, from the`
159			`// beginning`
160			`// 68 1 0/1/QR 1 - QSPI_IDLE`
161			`// 69 1 1/0 0 - QSPI_START`
162			`// 70 0 1/0 0 - QSPI_START`
163			`// 71 0 1/0 0 0-3 QSPI_BITS`
164			`// 72 1 1/0 0 0-3 QSPI_BITS`
165			`// 73 0 1/1/QR 0 4-7 QSPI_BITS`
166			`// 74 1 0/1/QR 0 4-7 QSPI_BITS`
167			`// 75 0 1/?/?/V 0 8-11 QSPI_BITS`
168			`// 76 1 1/?/? 0 8-11 QSPI_BITS`
169			`// 77 0 1/1/QR 0 12-15 QSPI_BITS`
170			`// 78 1 0/1/QR 0 12-15 QSPI_BITS`
171			`// 79 0 1/?/?/V 0 16-19 QSPI_BITS`
172			`// 80 1 1/0 0 16-19 QSPI_BITS`
173			`// 81 0 1/0 0 20-23 QSPI_BITS`
174			`// 82 1 1/0 0 20-23 QSPI_BITS`
175			`// 83 1 1/0/V 0 - QSPI_STOP`
176			`// 84 1 1/0 0 - QSPI_STOPB`
177			`// 85 1 1/0 1 - QSPI_IDLE`
178			`// 86 1 0/0 1 - QSPI_IDLE`
179
180			`wire i_miso;`
181			`assign i_miso = i_dat[1];`
182
183			`// These are used in creating a delayed input.`
184			`reg rd_input, rd_spd, rd_valid;`
185
186			`reg r_spd, r_dir;`
187			`reg [3:0] r_recycle;`
188			`reg [5:0] spi_len;`
189			`reg [31:0] r_word;`
190			`reg [30:0] r_input;`
191			`reg [2:0] state;`
192	10	dgisselq	initial state = `EQSPI_IDLE;
193	9	dgisselq	`initial o_sck = 1'b1;`
194			`initial o_cs_n = 1'b1;`
195			`initial o_dat = 4'hd;`
196			`initial rd_valid = 1'b0;`
197			`initial o_busy = 1'b0;`
198			`initial r_input = 31'h000;`
199			`initial rd_valid = 1'b0;`
200			`always @(posedge i_clk)`
201			`begin`
202			`rd_input <= 1'b0;`
203			`rd_spd <= r_spd;`
204			`rd_valid <= 1'b0;`
205
206	10	dgisselq	if ((state == `EQSPI_IDLE)&&(o_sck))
207	9	dgisselq	`begin`
208			`o_cs_n <= 1'b1;`
209			`o_busy <= 1'b0;`
210	10	dgisselq	o_mod <= `EQSPI_MOD_SPI;
211	9	dgisselq	`r_word <= i_word;`
212			`r_spd <= i_spd;`
213			`r_dir <= i_dir;`
214			`o_dat <= 4'hc;`
215			`r_recycle <= (i_recycle)? 4'h8 : 4'h2; // 4'ha : 4'h4`
216			`spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;`
217			`o_sck <= 1'b1;`
218			`if (i_wr)`
219			`begin`
220	10	dgisselq	state <= `EQSPI_START;
221	9	dgisselq	`o_cs_n <= 1'b0;`
222			`o_busy <= 1'b1;`
223			`end`
224	10	dgisselq	end else if (state == `EQSPI_START)
225	9	dgisselq	`begin // We come in here with sck high, stay here 'til sck is low`
226			`o_sck <= 1'b0;`
227			`if (o_sck == 1'b0)`
228			`begin`
229	10	dgisselq	state <= `EQSPI_BITS;
230	9	dgisselq	`spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );`
231			`if (r_spd)`
232			`r_word <= { r_word[27:0], 4'h0 };`
233			`else`
234			`r_word <= { r_word[30:0], 1'b0 };`
235			`end`
236	10	dgisselq	o_mod <= (r_spd) ? { 1'b1, r_dir } : `EQSPI_MOD_SPI;
237	9	dgisselq	`o_cs_n <= 1'b0;`
238			`o_busy <= 1'b1;`
239			`if (r_spd)`
240			`o_dat <= r_word[31:28];`
241			`else`
242			`o_dat <= { 3'b110, r_word[31] };`
243			`end else if (~o_sck)`
244			`begin`
245			`o_sck <= 1'b1;`
246	10	dgisselq	o_busy <= ((state != `EQSPI_READY)\|\|(~i_wr));
247			end else if (state == `EQSPI_BITS)
248	9	dgisselq	`begin`
249			`// Should enter into here with at least a spi_len`
250			`// of one, perhaps more`
251			`o_sck <= 1'b0;`
252			`o_busy <= 1'b1;`
253			`if (r_spd)`
254			`begin`
255			`o_dat <= r_word[31:28];`
256			`r_word <= { r_word[27:0], 4'h0 };`
257			`spi_len <= spi_len - 6'h4;`
258			`if (spi_len == 6'h4)`
259	10	dgisselq	state <= `EQSPI_READY;
260	9	dgisselq	`end else begin`
261			`o_dat <= { 3'b110, r_word[31] };`
262			`r_word <= { r_word[30:0], 1'b0 };`
263			`spi_len <= spi_len - 6'h1;`
264			`if (spi_len == 6'h1)`
265	10	dgisselq	state <= `EQSPI_READY;
266	9	dgisselq	`end`
267
268			`rd_input <= 1'b1;`
269	10	dgisselq	end else if (state == `EQSPI_READY)
270	9	dgisselq	`begin`
271			`o_cs_n <= 1'b0;`
272			`o_busy <= 1'b1;`
273			`// This is the state on the last clock (both low and`
274			`// high clocks) of the data. Data is valid during`
275			`// this state. Here we chose to either STOP or`
276			`// continue and transmit more.`
277			`o_sck <= (i_hold); // No clocks while holding`
278			`if((~o_busy)&&(i_wr))// Acknowledge a new request`
279			`begin`
280	10	dgisselq	state <= `EQSPI_BITS;
281	9	dgisselq	`o_busy <= 1'b1;`
282			`o_sck <= 1'b0;`
283
284			`// Read the new request off the bus`
285			`r_spd <= i_spd;`
286			`r_dir <= i_dir;`
287			`// Set up the first bits on the bus`
288	10	dgisselq	o_mod <= (i_spd) ? { 1'b1, i_dir } : `EQSPI_MOD_SPI;
289	9	dgisselq	`if (i_spd)`
290			`begin`
291			`o_dat <= i_word[31:28];`
292			`r_word <= { i_word[27:0], 4'h0 };`
293			`// spi_len <= spi_len - 4;`
294			`spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8`
295			`- 6'h4;`
296			`end else begin`
297			`o_dat <= { 3'b110, i_word[31] };`
298			`r_word <= { i_word[30:0], 1'b0 };`
299			`spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8`
300			`- 6'h1;`
301			`end`
302
303			`// Read a bit upon any transition`
304			`rd_input <= 1'b1;`
305			`rd_valid <= 1'b1;`
306			`end else begin`
307			`o_sck <= 1'b1;`
308	10	dgisselq	state <= (i_hold)?`EQSPI_HOLDING : `EQSPI_STOP;
309	9	dgisselq	`o_busy <= (~i_hold);`
310
311			`// Read a bit upon any transition`
312			`rd_valid <= 1'b1;`
313			`rd_input <= 1'b1;`
314			`end`
315	10	dgisselq	end else if (state == `EQSPI_HOLDING)
316	9	dgisselq	`begin`
317			`// We need this state so that the o_valid signal`
318			`// can get strobed with our last result. Otherwise`
319			`// we could just sit in READY waiting for a new command.`
320			`//`
321			`// Incidentally, the change producing this state was`
322			`// the result of a nasty race condition. See the`
323			`// commends in wbqspiflash for more details.`
324			`//`
325			`rd_valid <= 1'b0;`
326			`o_cs_n <= 1'b0;`
327			`o_busy <= 1'b0;`
328			`if((~o_busy)&&(i_wr))// Acknowledge a new request`
329			`begin`
330	10	dgisselq	state <= `EQSPI_BITS;
331	9	dgisselq	`o_busy <= 1'b1;`
332			`o_sck <= 1'b0;`
333
334			`// Read the new request off the bus`
335			`r_spd <= i_spd;`
336			`r_dir <= i_dir;`
337			`// Set up the first bits on the bus`
338	10	dgisselq	o_mod<=(i_spd)?{ 1'b1, i_dir } : `EQSPI_MOD_SPI;
339	9	dgisselq	`if (i_spd)`
340			`begin`
341			`o_dat <= i_word[31:28];`
342			`r_word <= { i_word[27:0], 4'h0 };`
343			`spi_len<= { 1'b0, i_len, 3'b100 };`
344			`end else begin`
345			`o_dat <= { 3'b110, i_word[31] };`
346			`r_word <= { i_word[30:0], 1'b0 };`
347			`spi_len<= { 1'b0, i_len, 3'b111 };`
348			`end`
349			`end else begin`
350			`o_sck <= 1'b1;`
351	10	dgisselq	state <= (i_hold)?`EQSPI_HOLDING : `EQSPI_STOP;
352	9	dgisselq	`o_busy <= (~i_hold);`
353			`end`
354	10	dgisselq	end else if (state == `EQSPI_STOP)
355	9	dgisselq	`begin`
356			`o_sck <= 1'b1; // Stop the clock`
357			`rd_valid <= 1'b0; // Output may have just been valid, but no more`
358			`o_busy <= 1'b1; // Still busy till port is clear`
359	10	dgisselq	state <= `EQSPI_STOP_B;
360			`// Can't change modes for at least one cycle`
361			// o_mod <= `EQSPI_MOD_SPI;
362			end else if (state == `EQSPI_STOP_B)
363	9	dgisselq	`begin`
364			`o_cs_n <= 1'b1;`
365			`o_sck <= 1'b1;`
366			`// Do I need this????`
367			`// spi_len <= 3; // Minimum CS high time before next cmd`
368	10	dgisselq	state <= `EQSPI_RECYCLE;
369	9	dgisselq	`o_busy <= 1'b1;`
370	10	dgisselq	o_mod <= `EQSPI_MOD_SPI;
371	9	dgisselq	`end else begin // Recycle state`
372			`r_recycle <= r_recycle - 1'b1;`
373			`o_cs_n <= 1'b1;`
374			`o_sck <= 1'b1;`
375			`o_busy <= 1'b1;`
376	10	dgisselq	o_mod <= `EQSPI_MOD_SPI;
377	9	dgisselq	`o_dat <= 4'hc;`
378			`if (r_recycle[3:1] == 3'h0)`
379	10	dgisselq	state <= `EQSPI_IDLE;
380	9	dgisselq	`end`
381			`/*`
382			`end else begin // Invalid states, should never get here`
383	10	dgisselq	state <= `EQSPI_STOP;
384	9	dgisselq	`o_valid <= 1'b0;`
385			`o_busy <= 1'b1;`
386			`o_cs_n <= 1'b1;`
387			`o_sck <= 1'b1;`
388	10	dgisselq	o_mod <= `EQSPI_MOD_SPI;
389	9	dgisselq	`o_dat <= 4'hd;`
390			`end`
391			`*/`
392			`end`
393
394			`always @(posedge i_clk)`
395			`begin`
396	10	dgisselq	if ((state == `EQSPI_IDLE)\|\|(rd_valid))
397	9	dgisselq	`r_input <= 31'h00;`
398			`else if ((rd_input)&&(r_spd))`
399			`r_input <= { r_input[26:0], i_dat };`
400			`else if (rd_input)`
401			`r_input <= { r_input[29:0], i_miso };`
402
403			`if ((rd_valid)&&(r_spd))`
404			`o_word <= { r_input[27:0], i_dat };`
405			`else if (rd_valid)`
406			`o_word <= { r_input[30:0], i_miso };`
407			`end`
408
409			`assign o_valid = rd_valid;`
410
411			`endmodule`
412

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