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[/] [qspiflash/] [trunk/] [rtl/] [lleqspi.v] - Blame information for rev 11

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1 9 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3 11 dgisselq
// Filename:    lleqspi.v
4 9 dgisselq
//
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// Project:     Wishbone Controlled Quad SPI Flash Controller
6
//
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// Purpose:     Reads/writes a word (user selectable number of bytes) of data
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//              to/from a Quad SPI port.  The port is understood to be 
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//              a normal SPI port unless the driver requests four bit mode.
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//              When not in use, unlike our previous SPI work, no bits will
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//              toggle.
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//
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// Creator:     Dan Gisselquist
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//              Gisselquist Technology, LLC
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//
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
19 9 dgisselq
//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
40 10 dgisselq
`define EQSPI_IDLE      3'h0
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`define EQSPI_START     3'h1
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`define EQSPI_BITS      3'h2
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`define EQSPI_READY     3'h3
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`define EQSPI_HOLDING   3'h4
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`define EQSPI_STOP      3'h5
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`define EQSPI_STOP_B    3'h6
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`define EQSPI_RECYCLE   3'h7
48 9 dgisselq
 
49
// Modes
50 10 dgisselq
`define EQSPI_MOD_SPI   2'b00
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`define EQSPI_MOD_QOUT  2'b10   // Write
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`define EQSPI_MOD_QIN   2'b11   // Read
53 9 dgisselq
 
54 10 dgisselq
module  lleqspi(i_clk,
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                // Module interface
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                i_wr, i_hold, i_word, i_len, i_spd, i_dir, i_recycle,
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                        o_word, o_valid, o_busy,
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                // QSPI interface
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                o_sck, o_cs_n, o_mod, o_dat, i_dat);
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        input                   i_clk;
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        // Chip interface
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        //      Can send info
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        //              i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,
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        //                      i_word = { 1'b0, 32'info to send },
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        //                      i_len = # of bytes in word-1
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        input                   i_wr, i_hold;
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        input           [31:0]   i_word;
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        input           [1:0]    i_len;  // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits
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        input                   i_spd; // 0 -> normal QPI, 1 -> QSPI
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        input                   i_dir; // 0 -> read, 1 -> write to SPI
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        input                   i_recycle; // 0 = 20ns, 1 = 50ns
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        output  reg     [31:0]   o_word;
73 11 dgisselq
        output  reg             o_valid;
74 9 dgisselq
        output  reg             o_busy;
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        // Interface with the QSPI lines
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        output  reg             o_sck;
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        output  reg             o_cs_n;
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        output  reg     [1:0]    o_mod;
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        output  reg     [3:0]    o_dat;
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        input           [3:0]    i_dat;
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82
        // output       wire    [22:0]  o_dbg;
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        // assign       o_dbg = { state, spi_len,
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                // o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };
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86
        wire    i_miso;
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        assign  i_miso = i_dat[1];
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89
        // These are used in creating a delayed input.
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        reg             rd_input, rd_spd, rd_valid;
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92
        reg             r_spd, r_dir;
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        reg     [3:0]    r_recycle;
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        reg     [5:0]    spi_len;
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        reg     [31:0]   r_word;
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        reg     [30:0]   r_input;
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        reg     [2:0]    state;
98 10 dgisselq
        initial state = `EQSPI_IDLE;
99 9 dgisselq
        initial o_sck   = 1'b1;
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        initial o_cs_n  = 1'b1;
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        initial o_dat   = 4'hd;
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        initial rd_valid = 1'b0;
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        initial o_busy  = 1'b0;
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        initial r_input = 31'h000;
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        initial rd_valid = 1'b0;
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        always @(posedge i_clk)
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        begin
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                rd_input <= 1'b0;
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                rd_spd   <= r_spd;
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                rd_valid <= 1'b0;
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112 10 dgisselq
                if ((state == `EQSPI_IDLE)&&(o_sck))
113 9 dgisselq
                begin
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                        o_cs_n <= 1'b1;
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                        o_busy  <= 1'b0;
116 10 dgisselq
                        o_mod <= `EQSPI_MOD_SPI;
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                        r_word <= i_word;
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                        r_spd <= i_spd;
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                        r_dir <= i_dir;
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                        o_dat <= 4'hc;
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                        r_recycle <= (i_recycle)? 4'h8 : 4'h2; // 4'ha : 4'h4
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                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
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                        o_sck <= 1'b1;
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                        if (i_wr)
125
                        begin
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                                state <= `EQSPI_START;
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                                o_cs_n <= 1'b0;
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                                o_busy <= 1'b1;
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                        end
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                end else if (state == `EQSPI_START)
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                begin // We come in here with sck high, stay here 'til sck is low
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                        o_sck <= 1'b0;
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                        if (o_sck == 1'b0)
134
                        begin
135 10 dgisselq
                                state <= `EQSPI_BITS;
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                                spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );
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                                if (r_spd)
138
                                        r_word <= { r_word[27:0], 4'h0 };
139
                                else
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                                        r_word <= { r_word[30:0], 1'b0 };
141
                        end
142 10 dgisselq
                        o_mod <= (r_spd) ? { 1'b1, r_dir } : `EQSPI_MOD_SPI;
143 9 dgisselq
                        o_cs_n <= 1'b0;
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                        o_busy <= 1'b1;
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                        if (r_spd)
146
                                o_dat <= r_word[31:28];
147
                        else
148
                                o_dat <= { 3'b110, r_word[31] };
149
                end else if (~o_sck)
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                begin
151
                        o_sck <= 1'b1;
152 10 dgisselq
                        o_busy <= ((state != `EQSPI_READY)||(~i_wr));
153
                end else if (state == `EQSPI_BITS)
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                begin
155
                        // Should enter into here with at least a spi_len
156
                        // of one, perhaps more
157
                        o_sck <= 1'b0;
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                        o_busy <= 1'b1;
159
                        if (r_spd)
160
                        begin
161
                                o_dat <= r_word[31:28];
162
                                r_word <= { r_word[27:0], 4'h0 };
163
                                spi_len <= spi_len - 6'h4;
164
                                if (spi_len == 6'h4)
165 10 dgisselq
                                        state <= `EQSPI_READY;
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                        end else begin
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                                o_dat <= { 3'b110, r_word[31] };
168
                                r_word <= { r_word[30:0], 1'b0 };
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                                spi_len <= spi_len - 6'h1;
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                                if (spi_len == 6'h1)
171 10 dgisselq
                                        state <= `EQSPI_READY;
172 9 dgisselq
                        end
173
 
174
                        rd_input <= 1'b1;
175 10 dgisselq
                end else if (state == `EQSPI_READY)
176 9 dgisselq
                begin
177
                        o_cs_n <= 1'b0;
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                        o_busy <= 1'b1;
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                        // This is the state on the last clock (both low and
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                        // high clocks) of the data.  Data is valid during
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                        // this state.  Here we chose to either STOP or
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                        // continue and transmit more.
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                        o_sck <= (i_hold); // No clocks while holding
184
                        if((~o_busy)&&(i_wr))// Acknowledge a new request
185
                        begin
186 10 dgisselq
                                state <= `EQSPI_BITS;
187 9 dgisselq
                                o_busy <= 1'b1;
188
                                o_sck <= 1'b0;
189
 
190
                                // Read the new request off the bus
191
                                r_spd <= i_spd;
192
                                r_dir <= i_dir;
193
                                // Set up the first bits on the bus
194 10 dgisselq
                                o_mod <= (i_spd) ? { 1'b1, i_dir } : `EQSPI_MOD_SPI;
195 9 dgisselq
                                if (i_spd)
196
                                begin
197
                                        o_dat <= i_word[31:28];
198
                                        r_word <= { i_word[27:0], 4'h0 };
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                                        // spi_len <= spi_len - 4;
200
                                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
201
                                                - 6'h4;
202
                                end else begin
203
                                        o_dat <= { 3'b110, i_word[31] };
204
                                        r_word <= { i_word[30:0], 1'b0 };
205
                                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
206
                                                - 6'h1;
207
                                end
208
 
209
                                // Read a bit upon any transition
210
                                rd_input <= 1'b1;
211
                                rd_valid <= 1'b1;
212
                        end else begin
213
                                o_sck <= 1'b1;
214 10 dgisselq
                                state <= (i_hold)?`EQSPI_HOLDING : `EQSPI_STOP;
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                                o_busy <= (~i_hold);
216
 
217
                                // Read a bit upon any transition
218
                                rd_valid <= 1'b1;
219
                                rd_input <= 1'b1;
220
                        end
221 10 dgisselq
                end else if (state == `EQSPI_HOLDING)
222 9 dgisselq
                begin
223
                        // We need this state so that the o_valid signal
224
                        // can get strobed with our last result.  Otherwise
225
                        // we could just sit in READY waiting for a new command.
226
                        //
227
                        // Incidentally, the change producing this state was
228
                        // the result of a nasty race condition.  See the
229
                        // commends in wbqspiflash for more details.
230
                        //
231
                        rd_valid <= 1'b0;
232
                        o_cs_n <= 1'b0;
233
                        o_busy <= 1'b0;
234
                        if((~o_busy)&&(i_wr))// Acknowledge a new request
235
                        begin
236 10 dgisselq
                                state  <= `EQSPI_BITS;
237 9 dgisselq
                                o_busy <= 1'b1;
238
                                o_sck  <= 1'b0;
239
 
240
                                // Read the new request off the bus
241
                                r_spd <= i_spd;
242
                                r_dir <= i_dir;
243
                                // Set up the first bits on the bus
244 10 dgisselq
                                o_mod<=(i_spd)?{ 1'b1, i_dir } : `EQSPI_MOD_SPI;
245 9 dgisselq
                                if (i_spd)
246
                                begin
247
                                        o_dat <= i_word[31:28];
248
                                        r_word <= { i_word[27:0], 4'h0 };
249
                                        spi_len<= { 1'b0, i_len, 3'b100 };
250
                                end else begin
251
                                        o_dat <= { 3'b110, i_word[31] };
252
                                        r_word <= { i_word[30:0], 1'b0 };
253
                                        spi_len<= { 1'b0, i_len, 3'b111 };
254
                                end
255
                        end else begin
256
                                o_sck <= 1'b1;
257 10 dgisselq
                                state <= (i_hold)?`EQSPI_HOLDING : `EQSPI_STOP;
258 9 dgisselq
                                o_busy <= (~i_hold);
259
                        end
260 10 dgisselq
                end else if (state == `EQSPI_STOP)
261 9 dgisselq
                begin
262
                        o_sck   <= 1'b1; // Stop the clock
263
                        rd_valid <= 1'b0; // Output may have just been valid, but no more
264
                        o_busy  <= 1'b1; // Still busy till port is clear
265 10 dgisselq
                        state <= `EQSPI_STOP_B;
266
                        // Can't change modes for at least one cycle
267
                        // o_mod <= `EQSPI_MOD_SPI;
268
                end else if (state == `EQSPI_STOP_B)
269 9 dgisselq
                begin
270
                        o_cs_n <= 1'b1;
271
                        o_sck <= 1'b1;
272
                        // Do I need this????
273
                        // spi_len <= 3; // Minimum CS high time before next cmd
274 10 dgisselq
                        state <= `EQSPI_RECYCLE;
275 9 dgisselq
                        o_busy <= 1'b1;
276 10 dgisselq
                        o_mod <= `EQSPI_MOD_SPI;
277 9 dgisselq
                end else begin // Recycle state
278
                        r_recycle <= r_recycle - 1'b1;
279
                        o_cs_n <= 1'b1;
280
                        o_sck <= 1'b1;
281
                        o_busy <= 1'b1;
282 10 dgisselq
                        o_mod <= `EQSPI_MOD_SPI;
283 9 dgisselq
                        o_dat <= 4'hc;
284
                        if (r_recycle[3:1] == 3'h0)
285 10 dgisselq
                                state <= `EQSPI_IDLE;
286 9 dgisselq
                end
287
                /*
288
                end else begin // Invalid states, should never get here
289 10 dgisselq
                        state   <= `EQSPI_STOP;
290 9 dgisselq
                        o_valid <= 1'b0;
291
                        o_busy  <= 1'b1;
292
                        o_cs_n  <= 1'b1;
293
                        o_sck   <= 1'b1;
294 10 dgisselq
                        o_mod   <= `EQSPI_MOD_SPI;
295 9 dgisselq
                        o_dat   <= 4'hd;
296
                end
297
                */
298
        end
299
 
300 11 dgisselq
`define EXTRA_DELAY
301
        wire    rd_input_N, rd_valid_N, r_spd_N;
302
`ifdef EXTRA_DELAY
303
        reg     [2:0]    rd_input_p, rd_valid_p, r_spd_p;
304 9 dgisselq
        always @(posedge i_clk)
305 11 dgisselq
                rd_input_p <= { rd_input_p[1:0], rd_input };
306
        always @(posedge i_clk)
307
                rd_valid_p <= { rd_valid_p[1:0], rd_valid };
308
        always @(posedge i_clk)
309
                r_spd_p <= { r_spd_p[1:0], r_spd };
310
 
311
        assign  rd_input_N = rd_input_p[2];
312
        assign  rd_valid_N = rd_valid_p[2];
313
        assign  r_spd_N = r_spd_p[2];
314
`else
315
        assign  rd_input_N = rd_input;
316
        assign  rd_valid_N = rd_valid;
317
        assign  r_spd_N    = rd_spd;
318
`endif
319
 
320
 
321
        always @(posedge i_clk)
322 9 dgisselq
        begin
323 11 dgisselq
                // if ((state == `EQSPI_IDLE)||(rd_valid_N))
324
                if (o_valid)
325 9 dgisselq
                        r_input <= 31'h00;
326 11 dgisselq
                if ((rd_input_N)&&(r_spd_N))
327 9 dgisselq
                        r_input <= { r_input[26:0], i_dat };
328 11 dgisselq
                else if (rd_input_N)
329 9 dgisselq
                        r_input <= { r_input[29:0], i_miso };
330
 
331 11 dgisselq
                if ((rd_valid_N)&&(r_spd_N))
332 9 dgisselq
                        o_word  <= { r_input[27:0], i_dat };
333 11 dgisselq
                else if (rd_valid_N)
334 9 dgisselq
                        o_word  <= { r_input[30:0], i_miso };
335 11 dgisselq
                o_valid <= rd_valid_N;
336 9 dgisselq
        end
337
 
338
endmodule
339
 

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