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////////////////////////////////////////////////////////////////////////////////
//
// Filename:    lleqspi.v
//
// Project:     Wishbone Controlled Quad SPI Flash Controller
//
// Purpose:     Reads/writes a word (user selectable number of bytes) of data
//              to/from a Quad SPI port.  The port is understood to be 
//              a normal SPI port unless the driver requests four bit mode.
//              When not in use, unlike our previous SPI work, no bits will
//              toggle.
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`define EQSPI_IDLE      3'h0
`define EQSPI_START     3'h1
`define EQSPI_BITS      3'h2
`define EQSPI_READY     3'h3
`define EQSPI_HOLDING   3'h4
`define EQSPI_STOP      3'h5
`define EQSPI_STOP_B    3'h6
`define EQSPI_RECYCLE   3'h7
 
// Modes
`define EQSPI_MOD_SPI   2'b00
`define EQSPI_MOD_QOUT  2'b10   // Write
`define EQSPI_MOD_QIN   2'b11   // Read
 
module  lleqspi(i_clk,
                // Module interface
                i_wr, i_hold, i_word, i_len, i_spd, i_dir, i_recycle,
                        o_word, o_valid, o_busy,
                // QSPI interface
                o_sck, o_cs_n, o_mod, o_dat, i_dat);
        input                   i_clk;
        // Chip interface
        //      Can send info
        //              i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,
        //                      i_word = { 1'b0, 32'info to send },
        //                      i_len = # of bytes in word-1
        input                   i_wr, i_hold;
        input           [31:0]   i_word;
        input           [1:0]    i_len;  // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits
        input                   i_spd; // 0 -> normal QPI, 1 -> QSPI
        input                   i_dir; // 0 -> read, 1 -> write to SPI
        input                   i_recycle; // 0 = 20ns, 1 = 50ns
        output  reg     [31:0]   o_word;
        output  reg             o_valid;
        output  reg             o_busy;
        // Interface with the QSPI lines
        output  reg             o_sck;
        output  reg             o_cs_n;
        output  reg     [1:0]    o_mod;
        output  reg     [3:0]    o_dat;
        input           [3:0]    i_dat;
 
        // output       wire    [22:0]  o_dbg;
        // assign       o_dbg = { state, spi_len,
                // o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };
 
        wire    i_miso;
        assign  i_miso = i_dat[1];
 
        // These are used in creating a delayed input.
        reg             rd_input, rd_spd, rd_valid;
 
        reg             r_spd, r_dir;
        reg     [3:0]    r_recycle;
        reg     [5:0]    spi_len;
        reg     [31:0]   r_word;
        reg     [30:0]   r_input;
        reg     [2:0]    state;
        initial state = `EQSPI_IDLE;
        initial o_sck   = 1'b1;
        initial o_cs_n  = 1'b1;
        initial o_dat   = 4'hd;
        initial rd_valid = 1'b0;
        initial o_busy  = 1'b0;
        initial r_input = 31'h000;
        initial rd_valid = 1'b0;
        always @(posedge i_clk)
        begin
                rd_input <= 1'b0;
                rd_spd   <= r_spd;
                rd_valid <= 1'b0;
 
                if ((state == `EQSPI_IDLE)&&(o_sck))
                begin
                        o_cs_n <= 1'b1;
                        o_busy  <= 1'b0;
                        o_mod <= `EQSPI_MOD_SPI;
                        r_word <= i_word;
                        r_spd <= i_spd;
                        r_dir <= i_dir;
                        o_dat <= 4'hc;
                        r_recycle <= (i_recycle)? 4'h8 : 4'h2; // 4'ha : 4'h4
                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
                        o_sck <= 1'b1;
                        if (i_wr)
                        begin
                                state <= `EQSPI_START;
                                o_cs_n <= 1'b0;
                                o_busy <= 1'b1;
                        end
                end else if (state == `EQSPI_START)
                begin // We come in here with sck high, stay here 'til sck is low
                        o_sck <= 1'b0;
                        if (o_sck == 1'b0)
                        begin
                                state <= `EQSPI_BITS;
                                spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );
                                if (r_spd)
                                        r_word <= { r_word[27:0], 4'h0 };
                                else
                                        r_word <= { r_word[30:0], 1'b0 };
                        end
                        o_mod <= (r_spd) ? { 1'b1, r_dir } : `EQSPI_MOD_SPI;
                        o_cs_n <= 1'b0;
                        o_busy <= 1'b1;
                        if (r_spd)
                                o_dat <= r_word[31:28];
                        else
                                o_dat <= { 3'b110, r_word[31] };
                end else if (~o_sck)
                begin
                        o_sck <= 1'b1;
                        o_busy <= ((state != `EQSPI_READY)||(~i_wr));
                end else if (state == `EQSPI_BITS)
                begin
                        // Should enter into here with at least a spi_len
                        // of one, perhaps more
                        o_sck <= 1'b0;
                        o_busy <= 1'b1;
                        if (r_spd)
                        begin
                                o_dat <= r_word[31:28];
                                r_word <= { r_word[27:0], 4'h0 };
                                spi_len <= spi_len - 6'h4;
                                if (spi_len == 6'h4)
                                        state <= `EQSPI_READY;
                        end else begin
                                o_dat <= { 3'b110, r_word[31] };
                                r_word <= { r_word[30:0], 1'b0 };
                                spi_len <= spi_len - 6'h1;
                                if (spi_len == 6'h1)
                                        state <= `EQSPI_READY;
                        end
 
                        rd_input <= 1'b1;
                end else if (state == `EQSPI_READY)
                begin
                        o_cs_n <= 1'b0;
                        o_busy <= 1'b1;
                        // This is the state on the last clock (both low and
                        // high clocks) of the data.  Data is valid during
                        // this state.  Here we chose to either STOP or
                        // continue and transmit more.
                        o_sck <= (i_hold); // No clocks while holding
                        if((~o_busy)&&(i_wr))// Acknowledge a new request
                        begin
                                state <= `EQSPI_BITS;
                                o_busy <= 1'b1;
                                o_sck <= 1'b0;
 
                                // Read the new request off the bus
                                r_spd <= i_spd;
                                r_dir <= i_dir;
                                // Set up the first bits on the bus
                                o_mod <= (i_spd) ? { 1'b1, i_dir } : `EQSPI_MOD_SPI;
                                if (i_spd)
                                begin
                                        o_dat <= i_word[31:28];
                                        r_word <= { i_word[27:0], 4'h0 };
                                        // spi_len <= spi_len - 4;
                                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
                                                - 6'h4;
                                end else begin
                                        o_dat <= { 3'b110, i_word[31] };
                                        r_word <= { i_word[30:0], 1'b0 };
                                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
                                                - 6'h1;
                                end
 
                                // Read a bit upon any transition
                                rd_input <= 1'b1;
                                rd_valid <= 1'b1;
                        end else begin
                                o_sck <= 1'b1;
                                state <= (i_hold)?`EQSPI_HOLDING : `EQSPI_STOP;
                                o_busy <= (~i_hold);
 
                                // Read a bit upon any transition
                                rd_valid <= 1'b1;
                                rd_input <= 1'b1;
                        end
                end else if (state == `EQSPI_HOLDING)
                begin
                        // We need this state so that the o_valid signal
                        // can get strobed with our last result.  Otherwise
                        // we could just sit in READY waiting for a new command.
                        //
                        // Incidentally, the change producing this state was
                        // the result of a nasty race condition.  See the
                        // commends in wbqspiflash for more details.
                        //
                        rd_valid <= 1'b0;
                        o_cs_n <= 1'b0;
                        o_busy <= 1'b0;
                        if((~o_busy)&&(i_wr))// Acknowledge a new request
                        begin
                                state  <= `EQSPI_BITS;
                                o_busy <= 1'b1;
                                o_sck  <= 1'b0;
 
                                // Read the new request off the bus
                                r_spd <= i_spd;
                                r_dir <= i_dir;
                                // Set up the first bits on the bus
                                o_mod<=(i_spd)?{ 1'b1, i_dir } : `EQSPI_MOD_SPI;
                                if (i_spd)
                                begin
                                        o_dat <= i_word[31:28];
                                        r_word <= { i_word[27:0], 4'h0 };
                                        spi_len<= { 1'b0, i_len, 3'b100 };
                                end else begin
                                        o_dat <= { 3'b110, i_word[31] };
                                        r_word <= { i_word[30:0], 1'b0 };
                                        spi_len<= { 1'b0, i_len, 3'b111 };
                                end
                        end else begin
                                o_sck <= 1'b1;
                                state <= (i_hold)?`EQSPI_HOLDING : `EQSPI_STOP;
                                o_busy <= (~i_hold);
                        end
                end else if (state == `EQSPI_STOP)
                begin
                        o_sck   <= 1'b1; // Stop the clock
                        rd_valid <= 1'b0; // Output may have just been valid, but no more
                        o_busy  <= 1'b1; // Still busy till port is clear
                        state <= `EQSPI_STOP_B;
                        // Can't change modes for at least one cycle
                        // o_mod <= `EQSPI_MOD_SPI;
                end else if (state == `EQSPI_STOP_B)
                begin
                        o_cs_n <= 1'b1;
                        o_sck <= 1'b1;
                        // Do I need this????
                        // spi_len <= 3; // Minimum CS high time before next cmd
                        state <= `EQSPI_RECYCLE;
                        o_busy <= 1'b1;
                        o_mod <= `EQSPI_MOD_SPI;
                end else begin // Recycle state
                        r_recycle <= r_recycle - 1'b1;
                        o_cs_n <= 1'b1;
                        o_sck <= 1'b1;
                        o_busy <= 1'b1;
                        o_mod <= `EQSPI_MOD_SPI;
                        o_dat <= 4'hc;
                        if (r_recycle[3:1] == 3'h0)
                                state <= `EQSPI_IDLE;
                end
                /*
                end else begin // Invalid states, should never get here
                        state   <= `EQSPI_STOP;
                        o_valid <= 1'b0;
                        o_busy  <= 1'b1;
                        o_cs_n  <= 1'b1;
                        o_sck   <= 1'b1;
                        o_mod   <= `EQSPI_MOD_SPI;
                        o_dat   <= 4'hd;
                end
                */
        end
 
`define EXTRA_DELAY
        wire    rd_input_N, rd_valid_N, r_spd_N;
`ifdef EXTRA_DELAY
        reg     [2:0]    rd_input_p, rd_valid_p, r_spd_p;
        always @(posedge i_clk)
                rd_input_p <= { rd_input_p[1:0], rd_input };
        always @(posedge i_clk)
                rd_valid_p <= { rd_valid_p[1:0], rd_valid };
        always @(posedge i_clk)
                r_spd_p <= { r_spd_p[1:0], r_spd };
 
        assign  rd_input_N = rd_input_p[2];
        assign  rd_valid_N = rd_valid_p[2];
        assign  r_spd_N = r_spd_p[2];
`else
        assign  rd_input_N = rd_input;
        assign  rd_valid_N = rd_valid;
        assign  r_spd_N    = rd_spd;
`endif
 
 
        always @(posedge i_clk)
        begin
                // if ((state == `EQSPI_IDLE)||(rd_valid_N))
                if (o_valid)
                        r_input <= 31'h00;
                if ((rd_input_N)&&(r_spd_N))
                        r_input <= { r_input[26:0], i_dat };
                else if (rd_input_N)
                        r_input <= { r_input[29:0], i_miso };
 
                if ((rd_valid_N)&&(r_spd_N))
                        o_word  <= { r_input[27:0], i_dat };
                else if (rd_valid_N)
                        o_word  <= { r_input[30:0], i_miso };
                o_valid <= rd_valid_N;
        end
 
endmodule
 

Line No.	Rev	Author	Line
1	16	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
2	9	dgisselq	`//`
3	11	dgisselq	`// Filename: lleqspi.v`
4	9	dgisselq	`//`
5			`// Project: Wishbone Controlled Quad SPI Flash Controller`
6			`//`
7			`// Purpose: Reads/writes a word (user selectable number of bytes) of data`
8			`// to/from a Quad SPI port. The port is understood to be`
9			`// a normal SPI port unless the driver requests four bit mode.`
10			`// When not in use, unlike our previous SPI work, no bits will`
11			`// toggle.`
12			`//`
13	16	dgisselq	`// Creator: Dan Gisselquist, Ph.D.`
14	9	dgisselq	`// Gisselquist Technology, LLC`
15			`//`
16	16	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
17	9	dgisselq	`//`
18	16	dgisselq	`// Copyright (C) 2015-2017, Gisselquist Technology, LLC`
19	9	dgisselq	`//`
20			`// This program is free software (firmware): you can redistribute it and/or`
21			`// modify it under the terms of the GNU General Public License as published`
22			`// by the Free Software Foundation, either version 3 of the License, or (at`
23			`// your option) any later version.`
24			`//`
25			`// This program is distributed in the hope that it will be useful, but WITHOUT`
26			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
27			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
28			`// for more details.`
29			`//`
30			`// You should have received a copy of the GNU General Public License along`
31	16	dgisselq	`// with this program. (It's in the $(ROOT)/doc directory. Run make with no`
32	9	dgisselq	`// target there if the PDF file isn't present.) If not, see`
33			`// <http://www.gnu.org/licenses/> for a copy.`
34			`//`
35			`// License: GPL, v3, as defined and found on www.gnu.org,`
36			`// http://www.gnu.org/licenses/gpl.html`
37			`//`
38			`//`
39	16	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
40			`//`
41			`//`
42	10	dgisselq	`define EQSPI_IDLE 3'h0
43			`define EQSPI_START 3'h1
44			`define EQSPI_BITS 3'h2
45			`define EQSPI_READY 3'h3
46			`define EQSPI_HOLDING 3'h4
47			`define EQSPI_STOP 3'h5
48			`define EQSPI_STOP_B 3'h6
49			`define EQSPI_RECYCLE 3'h7
50	9	dgisselq
51			`// Modes`
52	10	dgisselq	`define EQSPI_MOD_SPI 2'b00
53			`define EQSPI_MOD_QOUT 2'b10 // Write
54			`define EQSPI_MOD_QIN 2'b11 // Read
55	9	dgisselq
56	10	dgisselq	`module lleqspi(i_clk,`
57	9	dgisselq	`// Module interface`
58			`i_wr, i_hold, i_word, i_len, i_spd, i_dir, i_recycle,`
59			`o_word, o_valid, o_busy,`
60			`// QSPI interface`
61			`o_sck, o_cs_n, o_mod, o_dat, i_dat);`
62			`input i_clk;`
63			`// Chip interface`
64			`// Can send info`
65			`// i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,`
66			`// i_word = { 1'b0, 32'info to send },`
67			`// i_len = # of bytes in word-1`
68			`input i_wr, i_hold;`
69			`input [31:0] i_word;`
70			`input [1:0] i_len; // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits`
71			`input i_spd; // 0 -> normal QPI, 1 -> QSPI`
72			`input i_dir; // 0 -> read, 1 -> write to SPI`
73			`input i_recycle; // 0 = 20ns, 1 = 50ns`
74			`output reg [31:0] o_word;`
75	11	dgisselq	`output reg o_valid;`
76	9	dgisselq	`output reg o_busy;`
77			`// Interface with the QSPI lines`
78			`output reg o_sck;`
79			`output reg o_cs_n;`
80			`output reg [1:0] o_mod;`
81			`output reg [3:0] o_dat;`
82			`input [3:0] i_dat;`
83
84			`// output wire [22:0] o_dbg;`
85			`// assign o_dbg = { state, spi_len,`
86			`// o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };`
87
88			`wire i_miso;`
89			`assign i_miso = i_dat[1];`
90
91			`// These are used in creating a delayed input.`
92			`reg rd_input, rd_spd, rd_valid;`
93
94			`reg r_spd, r_dir;`
95			`reg [3:0] r_recycle;`
96			`reg [5:0] spi_len;`
97			`reg [31:0] r_word;`
98			`reg [30:0] r_input;`
99			`reg [2:0] state;`
100	10	dgisselq	initial state = `EQSPI_IDLE;
101	9	dgisselq	`initial o_sck = 1'b1;`
102			`initial o_cs_n = 1'b1;`
103			`initial o_dat = 4'hd;`
104			`initial rd_valid = 1'b0;`
105			`initial o_busy = 1'b0;`
106			`initial r_input = 31'h000;`
107			`initial rd_valid = 1'b0;`
108			`always @(posedge i_clk)`
109			`begin`
110			`rd_input <= 1'b0;`
111			`rd_spd <= r_spd;`
112			`rd_valid <= 1'b0;`
113
114	10	dgisselq	if ((state == `EQSPI_IDLE)&&(o_sck))
115	9	dgisselq	`begin`
116			`o_cs_n <= 1'b1;`
117			`o_busy <= 1'b0;`
118	10	dgisselq	o_mod <= `EQSPI_MOD_SPI;
119	9	dgisselq	`r_word <= i_word;`
120			`r_spd <= i_spd;`
121			`r_dir <= i_dir;`
122			`o_dat <= 4'hc;`
123			`r_recycle <= (i_recycle)? 4'h8 : 4'h2; // 4'ha : 4'h4`
124			`spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;`
125			`o_sck <= 1'b1;`
126			`if (i_wr)`
127			`begin`
128	10	dgisselq	state <= `EQSPI_START;
129	9	dgisselq	`o_cs_n <= 1'b0;`
130			`o_busy <= 1'b1;`
131			`end`
132	10	dgisselq	end else if (state == `EQSPI_START)
133	9	dgisselq	`begin // We come in here with sck high, stay here 'til sck is low`
134			`o_sck <= 1'b0;`
135			`if (o_sck == 1'b0)`
136			`begin`
137	10	dgisselq	state <= `EQSPI_BITS;
138	9	dgisselq	`spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );`
139			`if (r_spd)`
140			`r_word <= { r_word[27:0], 4'h0 };`
141			`else`
142			`r_word <= { r_word[30:0], 1'b0 };`
143			`end`
144	10	dgisselq	o_mod <= (r_spd) ? { 1'b1, r_dir } : `EQSPI_MOD_SPI;
145	9	dgisselq	`o_cs_n <= 1'b0;`
146			`o_busy <= 1'b1;`
147			`if (r_spd)`
148			`o_dat <= r_word[31:28];`
149			`else`
150			`o_dat <= { 3'b110, r_word[31] };`
151			`end else if (~o_sck)`
152			`begin`
153			`o_sck <= 1'b1;`
154	10	dgisselq	o_busy <= ((state != `EQSPI_READY)\|\|(~i_wr));
155			end else if (state == `EQSPI_BITS)
156	9	dgisselq	`begin`
157			`// Should enter into here with at least a spi_len`
158			`// of one, perhaps more`
159			`o_sck <= 1'b0;`
160			`o_busy <= 1'b1;`
161			`if (r_spd)`
162			`begin`
163			`o_dat <= r_word[31:28];`
164			`r_word <= { r_word[27:0], 4'h0 };`
165			`spi_len <= spi_len - 6'h4;`
166			`if (spi_len == 6'h4)`
167	10	dgisselq	state <= `EQSPI_READY;
168	9	dgisselq	`end else begin`
169			`o_dat <= { 3'b110, r_word[31] };`
170			`r_word <= { r_word[30:0], 1'b0 };`
171			`spi_len <= spi_len - 6'h1;`
172			`if (spi_len == 6'h1)`
173	10	dgisselq	state <= `EQSPI_READY;
174	9	dgisselq	`end`
175
176			`rd_input <= 1'b1;`
177	10	dgisselq	end else if (state == `EQSPI_READY)
178	9	dgisselq	`begin`
179			`o_cs_n <= 1'b0;`
180			`o_busy <= 1'b1;`
181			`// This is the state on the last clock (both low and`
182			`// high clocks) of the data. Data is valid during`
183			`// this state. Here we chose to either STOP or`
184			`// continue and transmit more.`
185			`o_sck <= (i_hold); // No clocks while holding`
186			`if((~o_busy)&&(i_wr))// Acknowledge a new request`
187			`begin`
188	10	dgisselq	state <= `EQSPI_BITS;
189	9	dgisselq	`o_busy <= 1'b1;`
190			`o_sck <= 1'b0;`
191
192			`// Read the new request off the bus`
193			`r_spd <= i_spd;`
194			`r_dir <= i_dir;`
195			`// Set up the first bits on the bus`
196	10	dgisselq	o_mod <= (i_spd) ? { 1'b1, i_dir } : `EQSPI_MOD_SPI;
197	9	dgisselq	`if (i_spd)`
198			`begin`
199			`o_dat <= i_word[31:28];`
200			`r_word <= { i_word[27:0], 4'h0 };`
201			`// spi_len <= spi_len - 4;`
202			`spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8`
203			`- 6'h4;`
204			`end else begin`
205			`o_dat <= { 3'b110, i_word[31] };`
206			`r_word <= { i_word[30:0], 1'b0 };`
207			`spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8`
208			`- 6'h1;`
209			`end`
210
211			`// Read a bit upon any transition`
212			`rd_input <= 1'b1;`
213			`rd_valid <= 1'b1;`
214			`end else begin`
215			`o_sck <= 1'b1;`
216	10	dgisselq	state <= (i_hold)?`EQSPI_HOLDING : `EQSPI_STOP;
217	9	dgisselq	`o_busy <= (~i_hold);`
218
219			`// Read a bit upon any transition`
220			`rd_valid <= 1'b1;`
221			`rd_input <= 1'b1;`
222			`end`
223	10	dgisselq	end else if (state == `EQSPI_HOLDING)
224	9	dgisselq	`begin`
225			`// We need this state so that the o_valid signal`
226			`// can get strobed with our last result. Otherwise`
227			`// we could just sit in READY waiting for a new command.`
228			`//`
229			`// Incidentally, the change producing this state was`
230			`// the result of a nasty race condition. See the`
231			`// commends in wbqspiflash for more details.`
232			`//`
233			`rd_valid <= 1'b0;`
234			`o_cs_n <= 1'b0;`
235			`o_busy <= 1'b0;`
236			`if((~o_busy)&&(i_wr))// Acknowledge a new request`
237			`begin`
238	10	dgisselq	state <= `EQSPI_BITS;
239	9	dgisselq	`o_busy <= 1'b1;`
240			`o_sck <= 1'b0;`
241
242			`// Read the new request off the bus`
243			`r_spd <= i_spd;`
244			`r_dir <= i_dir;`
245			`// Set up the first bits on the bus`
246	10	dgisselq	o_mod<=(i_spd)?{ 1'b1, i_dir } : `EQSPI_MOD_SPI;
247	9	dgisselq	`if (i_spd)`
248			`begin`
249			`o_dat <= i_word[31:28];`
250			`r_word <= { i_word[27:0], 4'h0 };`
251			`spi_len<= { 1'b0, i_len, 3'b100 };`
252			`end else begin`
253			`o_dat <= { 3'b110, i_word[31] };`
254			`r_word <= { i_word[30:0], 1'b0 };`
255			`spi_len<= { 1'b0, i_len, 3'b111 };`
256			`end`
257			`end else begin`
258			`o_sck <= 1'b1;`
259	10	dgisselq	state <= (i_hold)?`EQSPI_HOLDING : `EQSPI_STOP;
260	9	dgisselq	`o_busy <= (~i_hold);`
261			`end`
262	10	dgisselq	end else if (state == `EQSPI_STOP)
263	9	dgisselq	`begin`
264			`o_sck <= 1'b1; // Stop the clock`
265			`rd_valid <= 1'b0; // Output may have just been valid, but no more`
266			`o_busy <= 1'b1; // Still busy till port is clear`
267	10	dgisselq	state <= `EQSPI_STOP_B;
268			`// Can't change modes for at least one cycle`
269			// o_mod <= `EQSPI_MOD_SPI;
270			end else if (state == `EQSPI_STOP_B)
271	9	dgisselq	`begin`
272			`o_cs_n <= 1'b1;`
273			`o_sck <= 1'b1;`
274			`// Do I need this????`
275			`// spi_len <= 3; // Minimum CS high time before next cmd`
276	10	dgisselq	state <= `EQSPI_RECYCLE;
277	9	dgisselq	`o_busy <= 1'b1;`
278	10	dgisselq	o_mod <= `EQSPI_MOD_SPI;
279	9	dgisselq	`end else begin // Recycle state`
280			`r_recycle <= r_recycle - 1'b1;`
281			`o_cs_n <= 1'b1;`
282			`o_sck <= 1'b1;`
283			`o_busy <= 1'b1;`
284	10	dgisselq	o_mod <= `EQSPI_MOD_SPI;
285	9	dgisselq	`o_dat <= 4'hc;`
286			`if (r_recycle[3:1] == 3'h0)`
287	10	dgisselq	state <= `EQSPI_IDLE;
288	9	dgisselq	`end`
289			`/*`
290			`end else begin // Invalid states, should never get here`
291	10	dgisselq	state <= `EQSPI_STOP;
292	9	dgisselq	`o_valid <= 1'b0;`
293			`o_busy <= 1'b1;`
294			`o_cs_n <= 1'b1;`
295			`o_sck <= 1'b1;`
296	10	dgisselq	o_mod <= `EQSPI_MOD_SPI;
297	9	dgisselq	`o_dat <= 4'hd;`
298			`end`
299			`*/`
300			`end`
301
302	11	dgisselq	`define EXTRA_DELAY
303			`wire rd_input_N, rd_valid_N, r_spd_N;`
304			`ifdef EXTRA_DELAY
305			`reg [2:0] rd_input_p, rd_valid_p, r_spd_p;`
306	9	dgisselq	`always @(posedge i_clk)`
307	11	dgisselq	`rd_input_p <= { rd_input_p[1:0], rd_input };`
308			`always @(posedge i_clk)`
309			`rd_valid_p <= { rd_valid_p[1:0], rd_valid };`
310			`always @(posedge i_clk)`
311			`r_spd_p <= { r_spd_p[1:0], r_spd };`
312
313			`assign rd_input_N = rd_input_p[2];`
314			`assign rd_valid_N = rd_valid_p[2];`
315			`assign r_spd_N = r_spd_p[2];`
316			`else
317			`assign rd_input_N = rd_input;`
318			`assign rd_valid_N = rd_valid;`
319			`assign r_spd_N = rd_spd;`
320			`endif
321
322
323			`always @(posedge i_clk)`
324	9	dgisselq	`begin`
325	11	dgisselq	// if ((state == `EQSPI_IDLE)\|\|(rd_valid_N))
326			`if (o_valid)`
327	9	dgisselq	`r_input <= 31'h00;`
328	11	dgisselq	`if ((rd_input_N)&&(r_spd_N))`
329	9	dgisselq	`r_input <= { r_input[26:0], i_dat };`
330	11	dgisselq	`else if (rd_input_N)`
331	9	dgisselq	`r_input <= { r_input[29:0], i_miso };`
332
333	11	dgisselq	`if ((rd_valid_N)&&(r_spd_N))`
334	9	dgisselq	`o_word <= { r_input[27:0], i_dat };`
335	11	dgisselq	`else if (rd_valid_N)`
336	9	dgisselq	`o_word <= { r_input[30:0], i_miso };`
337	11	dgisselq	`o_valid <= rd_valid_N;`
338	9	dgisselq	`end`
339
340			`endmodule`
341

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