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[/] [qspiflash/] [trunk/] [rtl/] [lleqspi.v] - Blame information for rev 23

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1 16 dgisselq
////////////////////////////////////////////////////////////////////////////////
2 9 dgisselq
//
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// Filename:    lleqspi.v
4 9 dgisselq
//
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// Project:     Wishbone Controlled Quad SPI Flash Controller
6
//
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// Purpose:     Reads/writes a word (user selectable number of bytes) of data
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//              to/from a Quad SPI port.  The port is understood to be 
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//              a normal SPI port unless the driver requests four bit mode.
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//              When not in use, unlike our previous SPI work, no bits will
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//              toggle.
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//
13 16 dgisselq
// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
17 9 dgisselq
//
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
19 9 dgisselq
//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
31 16 dgisselq
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
32 9 dgisselq
// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
42 10 dgisselq
`define EQSPI_IDLE      3'h0
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`define EQSPI_START     3'h1
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`define EQSPI_BITS      3'h2
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`define EQSPI_READY     3'h3
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`define EQSPI_HOLDING   3'h4
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`define EQSPI_STOP      3'h5
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`define EQSPI_STOP_B    3'h6
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`define EQSPI_RECYCLE   3'h7
50 9 dgisselq
 
51
// Modes
52 10 dgisselq
`define EQSPI_MOD_SPI   2'b00
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`define EQSPI_MOD_QOUT  2'b10   // Write
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`define EQSPI_MOD_QIN   2'b11   // Read
55 9 dgisselq
 
56 10 dgisselq
module  lleqspi(i_clk,
57 9 dgisselq
                // Module interface
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                i_wr, i_hold, i_word, i_len, i_spd, i_dir, i_recycle,
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                        o_word, o_valid, o_busy,
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                // QSPI interface
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                o_sck, o_cs_n, o_mod, o_dat, i_dat);
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        input                   i_clk;
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        // Chip interface
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        //      Can send info
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        //              i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,
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        //                      i_word = { 1'b0, 32'info to send },
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        //                      i_len = # of bytes in word-1
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        input                   i_wr, i_hold;
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        input           [31:0]   i_word;
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        input           [1:0]    i_len;  // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits
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        input                   i_spd; // 0 -> normal QPI, 1 -> QSPI
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        input                   i_dir; // 0 -> read, 1 -> write to SPI
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        input                   i_recycle; // 0 = 20ns, 1 = 50ns
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        output  reg     [31:0]   o_word;
75 11 dgisselq
        output  reg             o_valid;
76 9 dgisselq
        output  reg             o_busy;
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        // Interface with the QSPI lines
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        output  reg             o_sck;
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        output  reg             o_cs_n;
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        output  reg     [1:0]    o_mod;
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        output  reg     [3:0]    o_dat;
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        input           [3:0]    i_dat;
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84
        // output       wire    [22:0]  o_dbg;
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        // assign       o_dbg = { state, spi_len,
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                // o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };
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88
        wire    i_miso;
89
        assign  i_miso = i_dat[1];
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91
        // These are used in creating a delayed input.
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        reg             rd_input, rd_spd, rd_valid;
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94
        reg             r_spd, r_dir;
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        reg     [3:0]    r_recycle;
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        reg     [5:0]    spi_len;
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        reg     [31:0]   r_word;
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        reg     [30:0]   r_input;
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        reg     [2:0]    state;
100 10 dgisselq
        initial state = `EQSPI_IDLE;
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        initial o_sck   = 1'b1;
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        initial o_cs_n  = 1'b1;
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        initial o_dat   = 4'hd;
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        initial rd_valid = 1'b0;
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        initial o_busy  = 1'b0;
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        initial r_input = 31'h000;
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        initial rd_valid = 1'b0;
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        always @(posedge i_clk)
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        begin
110
                rd_input <= 1'b0;
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                rd_spd   <= r_spd;
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                rd_valid <= 1'b0;
113
 
114 10 dgisselq
                if ((state == `EQSPI_IDLE)&&(o_sck))
115 9 dgisselq
                begin
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                        o_cs_n <= 1'b1;
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                        o_busy  <= 1'b0;
118 10 dgisselq
                        o_mod <= `EQSPI_MOD_SPI;
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                        r_word <= i_word;
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                        r_spd <= i_spd;
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                        r_dir <= i_dir;
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                        o_dat <= 4'hc;
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                        r_recycle <= (i_recycle)? 4'h8 : 4'h2; // 4'ha : 4'h4
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                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
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                        o_sck <= 1'b1;
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                        if (i_wr)
127
                        begin
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                                state <= `EQSPI_START;
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                                o_cs_n <= 1'b0;
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                                o_busy <= 1'b1;
131
                        end
132 10 dgisselq
                end else if (state == `EQSPI_START)
133 9 dgisselq
                begin // We come in here with sck high, stay here 'til sck is low
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                        o_sck <= 1'b0;
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                        if (o_sck == 1'b0)
136
                        begin
137 10 dgisselq
                                state <= `EQSPI_BITS;
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                                spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );
139
                                if (r_spd)
140
                                        r_word <= { r_word[27:0], 4'h0 };
141
                                else
142
                                        r_word <= { r_word[30:0], 1'b0 };
143
                        end
144 10 dgisselq
                        o_mod <= (r_spd) ? { 1'b1, r_dir } : `EQSPI_MOD_SPI;
145 9 dgisselq
                        o_cs_n <= 1'b0;
146
                        o_busy <= 1'b1;
147
                        if (r_spd)
148
                                o_dat <= r_word[31:28];
149
                        else
150
                                o_dat <= { 3'b110, r_word[31] };
151
                end else if (~o_sck)
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                begin
153
                        o_sck <= 1'b1;
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                        o_busy <= ((state != `EQSPI_READY)||(~i_wr));
155
                end else if (state == `EQSPI_BITS)
156 9 dgisselq
                begin
157
                        // Should enter into here with at least a spi_len
158
                        // of one, perhaps more
159
                        o_sck <= 1'b0;
160
                        o_busy <= 1'b1;
161
                        if (r_spd)
162
                        begin
163
                                o_dat <= r_word[31:28];
164
                                r_word <= { r_word[27:0], 4'h0 };
165
                                spi_len <= spi_len - 6'h4;
166
                                if (spi_len == 6'h4)
167 10 dgisselq
                                        state <= `EQSPI_READY;
168 9 dgisselq
                        end else begin
169
                                o_dat <= { 3'b110, r_word[31] };
170
                                r_word <= { r_word[30:0], 1'b0 };
171
                                spi_len <= spi_len - 6'h1;
172
                                if (spi_len == 6'h1)
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                                        state <= `EQSPI_READY;
174 9 dgisselq
                        end
175
 
176
                        rd_input <= 1'b1;
177 10 dgisselq
                end else if (state == `EQSPI_READY)
178 9 dgisselq
                begin
179
                        o_cs_n <= 1'b0;
180
                        o_busy <= 1'b1;
181
                        // This is the state on the last clock (both low and
182
                        // high clocks) of the data.  Data is valid during
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                        // this state.  Here we chose to either STOP or
184
                        // continue and transmit more.
185
                        o_sck <= (i_hold); // No clocks while holding
186
                        if((~o_busy)&&(i_wr))// Acknowledge a new request
187
                        begin
188 10 dgisselq
                                state <= `EQSPI_BITS;
189 9 dgisselq
                                o_busy <= 1'b1;
190
                                o_sck <= 1'b0;
191
 
192
                                // Read the new request off the bus
193
                                r_spd <= i_spd;
194
                                r_dir <= i_dir;
195
                                // Set up the first bits on the bus
196 10 dgisselq
                                o_mod <= (i_spd) ? { 1'b1, i_dir } : `EQSPI_MOD_SPI;
197 9 dgisselq
                                if (i_spd)
198
                                begin
199
                                        o_dat <= i_word[31:28];
200
                                        r_word <= { i_word[27:0], 4'h0 };
201
                                        // spi_len <= spi_len - 4;
202
                                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
203
                                                - 6'h4;
204
                                end else begin
205
                                        o_dat <= { 3'b110, i_word[31] };
206
                                        r_word <= { i_word[30:0], 1'b0 };
207
                                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
208
                                                - 6'h1;
209
                                end
210
 
211
                                // Read a bit upon any transition
212
                                rd_input <= 1'b1;
213
                                rd_valid <= 1'b1;
214
                        end else begin
215
                                o_sck <= 1'b1;
216 10 dgisselq
                                state <= (i_hold)?`EQSPI_HOLDING : `EQSPI_STOP;
217 9 dgisselq
                                o_busy <= (~i_hold);
218
 
219
                                // Read a bit upon any transition
220
                                rd_valid <= 1'b1;
221
                                rd_input <= 1'b1;
222
                        end
223 10 dgisselq
                end else if (state == `EQSPI_HOLDING)
224 9 dgisselq
                begin
225
                        // We need this state so that the o_valid signal
226
                        // can get strobed with our last result.  Otherwise
227
                        // we could just sit in READY waiting for a new command.
228
                        //
229
                        // Incidentally, the change producing this state was
230
                        // the result of a nasty race condition.  See the
231
                        // commends in wbqspiflash for more details.
232
                        //
233
                        rd_valid <= 1'b0;
234
                        o_cs_n <= 1'b0;
235
                        o_busy <= 1'b0;
236
                        if((~o_busy)&&(i_wr))// Acknowledge a new request
237
                        begin
238 10 dgisselq
                                state  <= `EQSPI_BITS;
239 9 dgisselq
                                o_busy <= 1'b1;
240
                                o_sck  <= 1'b0;
241
 
242
                                // Read the new request off the bus
243
                                r_spd <= i_spd;
244
                                r_dir <= i_dir;
245
                                // Set up the first bits on the bus
246 10 dgisselq
                                o_mod<=(i_spd)?{ 1'b1, i_dir } : `EQSPI_MOD_SPI;
247 9 dgisselq
                                if (i_spd)
248
                                begin
249
                                        o_dat <= i_word[31:28];
250
                                        r_word <= { i_word[27:0], 4'h0 };
251
                                        spi_len<= { 1'b0, i_len, 3'b100 };
252
                                end else begin
253
                                        o_dat <= { 3'b110, i_word[31] };
254
                                        r_word <= { i_word[30:0], 1'b0 };
255
                                        spi_len<= { 1'b0, i_len, 3'b111 };
256
                                end
257
                        end else begin
258
                                o_sck <= 1'b1;
259 10 dgisselq
                                state <= (i_hold)?`EQSPI_HOLDING : `EQSPI_STOP;
260 9 dgisselq
                                o_busy <= (~i_hold);
261
                        end
262 10 dgisselq
                end else if (state == `EQSPI_STOP)
263 9 dgisselq
                begin
264
                        o_sck   <= 1'b1; // Stop the clock
265
                        rd_valid <= 1'b0; // Output may have just been valid, but no more
266
                        o_busy  <= 1'b1; // Still busy till port is clear
267 10 dgisselq
                        state <= `EQSPI_STOP_B;
268
                        // Can't change modes for at least one cycle
269
                        // o_mod <= `EQSPI_MOD_SPI;
270
                end else if (state == `EQSPI_STOP_B)
271 9 dgisselq
                begin
272
                        o_cs_n <= 1'b1;
273
                        o_sck <= 1'b1;
274
                        // Do I need this????
275
                        // spi_len <= 3; // Minimum CS high time before next cmd
276 10 dgisselq
                        state <= `EQSPI_RECYCLE;
277 9 dgisselq
                        o_busy <= 1'b1;
278 10 dgisselq
                        o_mod <= `EQSPI_MOD_SPI;
279 9 dgisselq
                end else begin // Recycle state
280
                        r_recycle <= r_recycle - 1'b1;
281
                        o_cs_n <= 1'b1;
282
                        o_sck <= 1'b1;
283
                        o_busy <= 1'b1;
284 10 dgisselq
                        o_mod <= `EQSPI_MOD_SPI;
285 9 dgisselq
                        o_dat <= 4'hc;
286
                        if (r_recycle[3:1] == 3'h0)
287 10 dgisselq
                                state <= `EQSPI_IDLE;
288 9 dgisselq
                end
289
                /*
290
                end else begin // Invalid states, should never get here
291 10 dgisselq
                        state   <= `EQSPI_STOP;
292 9 dgisselq
                        o_valid <= 1'b0;
293
                        o_busy  <= 1'b1;
294
                        o_cs_n  <= 1'b1;
295
                        o_sck   <= 1'b1;
296 10 dgisselq
                        o_mod   <= `EQSPI_MOD_SPI;
297 9 dgisselq
                        o_dat   <= 4'hd;
298
                end
299
                */
300
        end
301
 
302 11 dgisselq
`define EXTRA_DELAY
303
        wire    rd_input_N, rd_valid_N, r_spd_N;
304
`ifdef EXTRA_DELAY
305
        reg     [2:0]    rd_input_p, rd_valid_p, r_spd_p;
306 9 dgisselq
        always @(posedge i_clk)
307 11 dgisselq
                rd_input_p <= { rd_input_p[1:0], rd_input };
308
        always @(posedge i_clk)
309
                rd_valid_p <= { rd_valid_p[1:0], rd_valid };
310
        always @(posedge i_clk)
311
                r_spd_p <= { r_spd_p[1:0], r_spd };
312
 
313
        assign  rd_input_N = rd_input_p[2];
314
        assign  rd_valid_N = rd_valid_p[2];
315
        assign  r_spd_N = r_spd_p[2];
316
`else
317
        assign  rd_input_N = rd_input;
318
        assign  rd_valid_N = rd_valid;
319
        assign  r_spd_N    = rd_spd;
320
`endif
321
 
322
 
323
        always @(posedge i_clk)
324 9 dgisselq
        begin
325 11 dgisselq
                // if ((state == `EQSPI_IDLE)||(rd_valid_N))
326
                if (o_valid)
327 9 dgisselq
                        r_input <= 31'h00;
328 11 dgisselq
                if ((rd_input_N)&&(r_spd_N))
329 9 dgisselq
                        r_input <= { r_input[26:0], i_dat };
330 11 dgisselq
                else if (rd_input_N)
331 9 dgisselq
                        r_input <= { r_input[29:0], i_miso };
332
 
333 11 dgisselq
                if ((rd_valid_N)&&(r_spd_N))
334 9 dgisselq
                        o_word  <= { r_input[27:0], i_dat };
335 11 dgisselq
                else if (rd_valid_N)
336 9 dgisselq
                        o_word  <= { r_input[30:0], i_miso };
337 11 dgisselq
                o_valid <= rd_valid_N;
338 9 dgisselq
        end
339
 
340
endmodule
341
 

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