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1 9 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    llqspi.v
4
//
5
// Project:     Wishbone Controlled Quad SPI Flash Controller
6
//
7
// Purpose:     Reads/writes a word (user selectable number of bytes) of data
8
//              to/from a Quad SPI port.  The port is understood to be 
9
//              a normal SPI port unless the driver requests four bit mode.
10
//              When not in use, unlike our previous SPI work, no bits will
11
//              toggle.
12
//
13
// Creator:     Dan Gisselquist
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//              Gisselquist Technology, LLC
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//
16
///////////////////////////////////////////////////////////////////////////
17
//
18
// Copyright (C) 2015, Gisselquist Technology, LLC
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//
20
// This program is free software (firmware): you can redistribute it and/or
21
// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
30
// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
38
//
39
///////////////////////////////////////////////////////////////////////////
40
`define QSPI_IDLE       3'h0
41
`define QSPI_START      3'h1
42
`define QSPI_BITS       3'h2
43
`define QSPI_READY      3'h3
44
`define QSPI_HOLDING    3'h4
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`define QSPI_STOP       3'h5
46
`define QSPI_STOP_B     3'h6
47
`define QSPI_RECYCLE    3'h7
48
 
49
// Modes
50
`define QSPI_MOD_SPI    2'b00
51
`define QSPI_MOD_QOUT   2'b10   // Write
52
`define QSPI_MOD_QIN    2'b11   // Read
53
 
54
module  llqspi(i_clk,
55
                // Module interface
56
                i_wr, i_hold, i_word, i_len, i_spd, i_dir, i_recycle,
57
                        o_word, o_valid, o_busy,
58
                // QSPI interface
59
                o_sck, o_cs_n, o_mod, o_dat, i_dat);
60
        input                   i_clk;
61
        // Chip interface
62
        //      Can send info
63
        //              i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,
64
        //                      i_word = { 1'b0, 32'info to send },
65
        //                      i_len = # of bytes in word-1
66
        input                   i_wr, i_hold;
67
        input           [31:0]   i_word;
68
        input           [1:0]    i_len;  // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits
69
        input                   i_spd; // 0 -> normal QPI, 1 -> QSPI
70
        input                   i_dir; // 0 -> read, 1 -> write to SPI
71
        input                   i_recycle; // 0 = 20ns, 1 = 50ns
72
        output  reg     [31:0]   o_word;
73
        output  wire            o_valid;
74
        output  reg             o_busy;
75
        // Interface with the QSPI lines
76
        output  reg             o_sck;
77
        output  reg             o_cs_n;
78
        output  reg     [1:0]    o_mod;
79
        output  reg     [3:0]    o_dat;
80
        input           [3:0]    i_dat;
81
 
82
        // output       wire    [22:0]  o_dbg;
83
        // assign       o_dbg = { state, spi_len,
84
                // o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };
85
 
86
        // Timing:
87
        //
88
        //      Tick    Clk     BSY/WR  CS_n    BIT/MO  STATE
89
        //       0      1       0/0     1        -      
90
        //       1      1       0/1     1        -
91
        //       2      1       1/0     0         -      QSPI_START
92
        //       3      0        1/0     0         -      QSPI_START
93
        //       4      0        1/0     0         0      QSPI_BITS
94
        //       5      1       1/0     0         0      QSPI_BITS
95
        //       6      0        1/0     0         1      QSPI_BITS
96
        //       7      1       1/0     0         1      QSPI_BITS
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        //       8      0        1/0     0         2      QSPI_BITS
98
        //       9      1       1/0     0         2      QSPI_BITS
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        //      10      0        1/0     0         3      QSPI_BITS
100
        //      11      1       1/0     0         3      QSPI_BITS
101
        //      12      0        1/0     0         4      QSPI_BITS
102
        //      13      1       1/0     0         4      QSPI_BITS
103
        //      14      0        1/0     0         5      QSPI_BITS
104
        //      15      1       1/0     0         5      QSPI_BITS
105
        //      16      0        1/0     0         6      QSPI_BITS
106
        //      17      1       1/1     0         6      QSPI_BITS
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        //      18      0        1/1     0         7      QSPI_READY
108
        //      19      1       0/1     0         7      QSPI_READY
109
        //      20      0        1/0/V   0         8      QSPI_BITS
110
        //      21      1       1/0     0         8      QSPI_BITS
111
        //      22      0        1/0     0         9      QSPI_BITS
112
        //      23      1       1/0     0         9      QSPI_BITS
113
        //      24      0        1/0     0        10      QSPI_BITS
114
        //      25      1       1/0     0        10      QSPI_BITS
115
        //      26      0        1/0     0        11      QSPI_BITS
116
        //      27      1       1/0     0        11      QSPI_BITS
117
        //      28      0        1/0     0        12      QSPI_BITS
118
        //      29      1       1/0     0        12      QSPI_BITS
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        //      30      0        1/0     0        13      QSPI_BITS
120
        //      31      1       1/0     0        13      QSPI_BITS
121
        //      32      0        1/0     0        14      QSPI_BITS
122
        //      33      1       1/0     0        14      QSPI_BITS
123
        //      34      0        1/0     0        15      QSPI_READY
124
        //      35      1       1/0     0        15      QSPI_READY
125
        //      36      1       1/0/V   0         -      QSPI_STOP
126
        //      37      1       1/0     0         -      QSPI_STOPB
127
        //      38      1       1/0     1        -      QSPI_IDLE
128
        //      39      1       0/0     1        -
129
        // Now, let's switch from single bit to quad mode
130
        //      40      1       0/0     1        -      QSPI_IDLE
131
        //      41      1       0/1     1        -      QSPI_IDLE
132
        //      42      1       1/0     0         -      QSPI_START
133
        //      43      0        1/0     0         -      QSPI_START
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        //      44      0        1/0     0         0      QSPI_BITS
135
        //      45      1       1/0     0         0      QSPI_BITS
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        //      46      0        1/0     0         1      QSPI_BITS
137
        //      47      1       1/0     0         1      QSPI_BITS
138
        //      48      0        1/0     0         2      QSPI_BITS
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        //      49      1       1/0     0         2      QSPI_BITS
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        //      50      0        1/0     0         3      QSPI_BITS
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        //      51      1       1/0     0         3      QSPI_BITS
142
        //      52      0        1/0     0         4      QSPI_BITS
143
        //      53      1       1/0     0         4      QSPI_BITS
144
        //      54      0        1/0     0         5      QSPI_BITS
145
        //      55      1       1/0     0         5      QSPI_BITS
146
        //      56      0        1/0     0         6      QSPI_BITS
147
        //      57      1       1/1/QR  0         6      QSPI_BITS
148
        //      58      0        1/1/QR  0         7      QSPI_READY
149
        //      59      1       0/1/QR  0         7      QSPI_READY
150
        //      60      0        1/0/?/V 0         8-11   QSPI_BITS
151
        //      61      1       1/0/?   0         8-11   QSPI_BITS
152
        //      62      0        1/0/?   0         12-15  QSPI_BITS
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        //      63      1       1/0/?   0         12-15  QSPI_BITS
154
        //      64      1       1/0/?/V 0        -       QSPI_STOP
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        //      65      1       1/0/?   0        -       QSPI_STOPB
156
        //      66      1       1/0/?   1       -       QSPI_IDLE
157
        //      67      1       0/0     1       -       QSPI_IDLE
158
        // Now let's try something entirely in Quad read mode, from the
159
        // beginning
160
        //      68      1       0/1/QR  1       -       QSPI_IDLE
161
        //      69      1       1/0     0        -       QSPI_START
162
        //      70      0        1/0     0        -       QSPI_START
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        //      71      0        1/0     0        0-3     QSPI_BITS
164
        //      72      1       1/0     0        0-3     QSPI_BITS
165
        //      73      0        1/1/QR  0        4-7     QSPI_BITS
166
        //      74      1       0/1/QR  0        4-7     QSPI_BITS
167
        //      75      0        1/?/?/V 0        8-11    QSPI_BITS
168
        //      76      1       1/?/?   0        8-11    QSPI_BITS
169
        //      77      0        1/1/QR  0        12-15   QSPI_BITS
170
        //      78      1       0/1/QR  0        12-15   QSPI_BITS
171
        //      79      0        1/?/?/V 0        16-19   QSPI_BITS
172
        //      80      1       1/0     0        16-19   QSPI_BITS
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        //      81      0        1/0     0        20-23   QSPI_BITS
174
        //      82      1       1/0     0        20-23   QSPI_BITS
175
        //      83      1       1/0/V   0        -       QSPI_STOP
176
        //      84      1       1/0     0        -       QSPI_STOPB
177
        //      85      1       1/0     1       -       QSPI_IDLE
178
        //      86      1       0/0     1       -       QSPI_IDLE
179
 
180
        wire    i_miso;
181
        assign  i_miso = i_dat[1];
182
 
183
        // These are used in creating a delayed input.
184
        reg             rd_input, rd_spd, rd_valid;
185
 
186
        reg             r_spd, r_dir;
187
        reg     [3:0]    r_recycle;
188
        reg     [5:0]    spi_len;
189
        reg     [31:0]   r_word;
190
        reg     [30:0]   r_input;
191
        reg     [2:0]    state;
192
        initial state = `QSPI_IDLE;
193
        initial o_sck   = 1'b1;
194
        initial o_cs_n  = 1'b1;
195
        initial o_dat   = 4'hd;
196
        initial rd_valid = 1'b0;
197
        initial o_busy  = 1'b0;
198
        initial r_input = 31'h000;
199
        initial rd_valid = 1'b0;
200
        always @(posedge i_clk)
201
        begin
202
                rd_input <= 1'b0;
203
                rd_spd   <= r_spd;
204
                rd_valid <= 1'b0;
205
 
206
                if ((state == `QSPI_IDLE)&&(o_sck))
207
                begin
208
                        o_cs_n <= 1'b1;
209
                        o_busy  <= 1'b0;
210
                        o_mod <= `QSPI_MOD_SPI;
211
                        r_word <= i_word;
212
                        r_spd <= i_spd;
213
                        r_dir <= i_dir;
214
                        o_dat <= 4'hc;
215
                        r_recycle <= (i_recycle)? 4'h8 : 4'h2; // 4'ha : 4'h4
216
                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
217
                        o_sck <= 1'b1;
218
                        if (i_wr)
219
                        begin
220
                                state <= `QSPI_START;
221
                                o_cs_n <= 1'b0;
222
                                o_busy <= 1'b1;
223
                        end
224
                end else if (state == `QSPI_START)
225
                begin // We come in here with sck high, stay here 'til sck is low
226
                        o_sck <= 1'b0;
227
                        if (o_sck == 1'b0)
228
                        begin
229
                                state <= `QSPI_BITS;
230
                                spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );
231
                                if (r_spd)
232
                                        r_word <= { r_word[27:0], 4'h0 };
233
                                else
234
                                        r_word <= { r_word[30:0], 1'b0 };
235
                        end
236
                        o_mod <= (r_spd) ? { 1'b1, r_dir } : `QSPI_MOD_SPI;
237
                        o_cs_n <= 1'b0;
238
                        o_busy <= 1'b1;
239
                        if (r_spd)
240
                                o_dat <= r_word[31:28];
241
                        else
242
                                o_dat <= { 3'b110, r_word[31] };
243
                end else if (~o_sck)
244
                begin
245
                        o_sck <= 1'b1;
246
                        o_busy <= ((state != `QSPI_READY)||(~i_wr));
247
                end else if (state == `QSPI_BITS)
248
                begin
249
                        // Should enter into here with at least a spi_len
250
                        // of one, perhaps more
251
                        o_sck <= 1'b0;
252
                        o_busy <= 1'b1;
253
                        if (r_spd)
254
                        begin
255
                                o_dat <= r_word[31:28];
256
                                r_word <= { r_word[27:0], 4'h0 };
257
                                spi_len <= spi_len - 6'h4;
258
                                if (spi_len == 6'h4)
259
                                        state <= `QSPI_READY;
260
                        end else begin
261
                                o_dat <= { 3'b110, r_word[31] };
262
                                r_word <= { r_word[30:0], 1'b0 };
263
                                spi_len <= spi_len - 6'h1;
264
                                if (spi_len == 6'h1)
265
                                        state <= `QSPI_READY;
266
                        end
267
 
268
                        rd_input <= 1'b1;
269
                end else if (state == `QSPI_READY)
270
                begin
271
                        o_cs_n <= 1'b0;
272
                        o_busy <= 1'b1;
273
                        // This is the state on the last clock (both low and
274
                        // high clocks) of the data.  Data is valid during
275
                        // this state.  Here we chose to either STOP or
276
                        // continue and transmit more.
277
                        o_sck <= (i_hold); // No clocks while holding
278
                        if((~o_busy)&&(i_wr))// Acknowledge a new request
279
                        begin
280
                                state <= `QSPI_BITS;
281
                                o_busy <= 1'b1;
282
                                o_sck <= 1'b0;
283
 
284
                                // Read the new request off the bus
285
                                r_spd <= i_spd;
286
                                r_dir <= i_dir;
287
                                // Set up the first bits on the bus
288
                                o_mod <= (i_spd) ? { 1'b1, i_dir } : `QSPI_MOD_SPI;
289
                                if (i_spd)
290
                                begin
291
                                        o_dat <= i_word[31:28];
292
                                        r_word <= { i_word[27:0], 4'h0 };
293
                                        // spi_len <= spi_len - 4;
294
                                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
295
                                                - 6'h4;
296
                                end else begin
297
                                        o_dat <= { 3'b110, i_word[31] };
298
                                        r_word <= { i_word[30:0], 1'b0 };
299
                                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
300
                                                - 6'h1;
301
                                end
302
 
303
                                // Read a bit upon any transition
304
                                rd_input <= 1'b1;
305
                                rd_valid <= 1'b1;
306
                        end else begin
307
                                o_sck <= 1'b1;
308
                                state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
309
                                o_busy <= (~i_hold);
310
 
311
                                // Read a bit upon any transition
312
                                rd_valid <= 1'b1;
313
                                rd_input <= 1'b1;
314
                        end
315
                end else if (state == `QSPI_HOLDING)
316
                begin
317
                        // We need this state so that the o_valid signal
318
                        // can get strobed with our last result.  Otherwise
319
                        // we could just sit in READY waiting for a new command.
320
                        //
321
                        // Incidentally, the change producing this state was
322
                        // the result of a nasty race condition.  See the
323
                        // commends in wbqspiflash for more details.
324
                        //
325
                        rd_valid <= 1'b0;
326
                        o_cs_n <= 1'b0;
327
                        o_busy <= 1'b0;
328
                        if((~o_busy)&&(i_wr))// Acknowledge a new request
329
                        begin
330
                                state  <= `QSPI_BITS;
331
                                o_busy <= 1'b1;
332
                                o_sck  <= 1'b0;
333
 
334
                                // Read the new request off the bus
335
                                r_spd <= i_spd;
336
                                r_dir <= i_dir;
337
                                // Set up the first bits on the bus
338
                                o_mod<=(i_spd)?{ 1'b1, i_dir } : `QSPI_MOD_SPI;
339
                                if (i_spd)
340
                                begin
341
                                        o_dat <= i_word[31:28];
342
                                        r_word <= { i_word[27:0], 4'h0 };
343
                                        spi_len<= { 1'b0, i_len, 3'b100 };
344
                                end else begin
345
                                        o_dat <= { 3'b110, i_word[31] };
346
                                        r_word <= { i_word[30:0], 1'b0 };
347
                                        spi_len<= { 1'b0, i_len, 3'b111 };
348
                                end
349
                        end else begin
350
                                o_sck <= 1'b1;
351
                                state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
352
                                o_busy <= (~i_hold);
353
                        end
354
                end else if (state == `QSPI_STOP)
355
                begin
356
                        o_sck   <= 1'b1; // Stop the clock
357
                        rd_valid <= 1'b0; // Output may have just been valid, but no more
358
                        o_busy  <= 1'b1; // Still busy till port is clear
359
                        state <= `QSPI_STOP_B;
360
                        o_mod <= `QSPI_MOD_SPI;
361
                end else if (state == `QSPI_STOP_B)
362
                begin
363
                        o_cs_n <= 1'b1;
364
                        o_sck <= 1'b1;
365
                        // Do I need this????
366
                        // spi_len <= 3; // Minimum CS high time before next cmd
367
                        state <= `QSPI_RECYCLE;
368
                        o_busy <= 1'b1;
369
                        o_mod <= `QSPI_MOD_SPI;
370
                end else begin // Recycle state
371
                        r_recycle <= r_recycle - 1'b1;
372
                        o_cs_n <= 1'b1;
373
                        o_sck <= 1'b1;
374
                        o_busy <= 1'b1;
375
                        o_mod <= `QSPI_MOD_SPI;
376
                        o_dat <= 4'hc;
377
                        if (r_recycle[3:1] == 3'h0)
378
                                state <= `QSPI_IDLE;
379
                end
380
                /*
381
                end else begin // Invalid states, should never get here
382
                        state   <= `QSPI_STOP;
383
                        o_valid <= 1'b0;
384
                        o_busy  <= 1'b1;
385
                        o_cs_n  <= 1'b1;
386
                        o_sck   <= 1'b1;
387
                        o_mod   <= `QSPI_MOD_SPI;
388
                        o_dat   <= 4'hd;
389
                end
390
                */
391
        end
392
 
393
        always @(posedge i_clk)
394
        begin
395
                if ((state == `QSPI_IDLE)||(rd_valid))
396
                        r_input <= 31'h00;
397
                else if ((rd_input)&&(r_spd))
398
                        r_input <= { r_input[26:0], i_dat };
399
                else if (rd_input)
400
                        r_input <= { r_input[29:0], i_miso };
401
 
402
                if ((rd_valid)&&(r_spd))
403
                        o_word  <= { r_input[27:0], i_dat };
404
                else if (rd_valid)
405
                        o_word  <= { r_input[30:0], i_miso };
406
        end
407
 
408
        assign  o_valid = rd_valid;
409
 
410
endmodule
411
 

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