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[/] [qspiflash/] [trunk/] [rtl/] [llqspi.v] - Blame information for rev 14

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1 3 dgisselq
///////////////////////////////////////////////////////////////////////////
2 2 dgisselq
//
3
// Filename:    llqspi.v
4
//
5 3 dgisselq
// Project:     Wishbone Controlled Quad SPI Flash Controller
6 2 dgisselq
//
7
// Purpose:     Reads/writes a word (user selectable number of bytes) of data
8
//              to/from a Quad SPI port.  The port is understood to be 
9
//              a normal SPI port unless the driver requests four bit mode.
10
//              When not in use, unlike our previous SPI work, no bits will
11
//              toggle.
12
//
13
// Creator:     Dan Gisselquist
14 8 dgisselq
//              Gisselquist Technology, LLC
15 2 dgisselq
//
16 3 dgisselq
///////////////////////////////////////////////////////////////////////////
17 2 dgisselq
//
18 3 dgisselq
// Copyright (C) 2015, Gisselquist Technology, LLC
19 2 dgisselq
//
20 3 dgisselq
// This program is free software (firmware): you can redistribute it and/or
21
// modify it under the terms of  the GNU General Public License as published
22
// by the Free Software Foundation, either version 3 of the License, or (at
23
// your option) any later version.
24
//
25
// This program is distributed in the hope that it will be useful, but WITHOUT
26
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
27
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
28
// for more details.
29
//
30
// You should have received a copy of the GNU General Public License along
31
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
32
// target there if the PDF file isn't present.)  If not, see
33
// <http://www.gnu.org/licenses/> for a copy.
34
//
35
// License:     GPL, v3, as defined and found on www.gnu.org,
36
//              http://www.gnu.org/licenses/gpl.html
37
//
38
//
39
///////////////////////////////////////////////////////////////////////////
40 14 dgisselq
//
41
//
42
`default_nettype        none
43
//
44 4 dgisselq
`define QSPI_IDLE       3'h0
45
`define QSPI_START      3'h1
46
`define QSPI_BITS       3'h2
47
`define QSPI_READY      3'h3
48
`define QSPI_HOLDING    3'h4
49
`define QSPI_STOP       3'h5
50
`define QSPI_STOP_B     3'h6
51 2 dgisselq
 
52
// Modes
53
`define QSPI_MOD_SPI    2'b00
54
`define QSPI_MOD_QOUT   2'b10
55
`define QSPI_MOD_QIN    2'b11
56
 
57
module  llqspi(i_clk,
58
                // Module interface
59
                i_wr, i_hold, i_word, i_len, i_spd, i_dir,
60
                        o_word, o_valid, o_busy,
61
                // QSPI interface
62 3 dgisselq
                o_sck, o_cs_n, o_mod, o_dat, i_dat);
63 14 dgisselq
        input   wire            i_clk;
64 2 dgisselq
        // Chip interface
65
        //      Can send info
66
        //              i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,
67
        //                      i_word = { 1'b0, 32'info to send },
68
        //                      i_len = # of bytes in word-1
69 14 dgisselq
        input   wire            i_wr, i_hold;
70
        input   wire    [31:0]   i_word;
71
        input   wire    [1:0]    i_len;  // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits
72
        input   wire            i_spd; // 0 -> normal QPI, 1 -> QSPI
73
        input   wire            i_dir; // 0 -> read, 1 -> write to SPI
74 2 dgisselq
        output  reg     [31:0]   o_word;
75
        output  reg             o_valid, o_busy;
76
        // Interface with the QSPI lines
77
        output  reg             o_sck;
78
        output  reg             o_cs_n;
79
        output  reg     [1:0]    o_mod;
80
        output  reg     [3:0]    o_dat;
81
        input           [3:0]    i_dat;
82
 
83 7 dgisselq
        // output       wire    [22:0]  o_dbg;
84
        // assign       o_dbg = { state, spi_len,
85
                // o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };
86
 
87 2 dgisselq
        // Timing:
88
        //
89
        //      Tick    Clk     BSY/WR  CS_n    BIT/MO  STATE
90
        //       0      1       0/0     1        -      
91
        //       1      1       0/1     1        -
92
        //       2      1       1/0     0         -      QSPI_START
93
        //       3      0        1/0     0         -      QSPI_START
94
        //       4      0        1/0     0         0      QSPI_BITS
95
        //       5      1       1/0     0         0      QSPI_BITS
96
        //       6      0        1/0     0         1      QSPI_BITS
97
        //       7      1       1/0     0         1      QSPI_BITS
98
        //       8      0        1/0     0         2      QSPI_BITS
99
        //       9      1       1/0     0         2      QSPI_BITS
100
        //      10      0        1/0     0         3      QSPI_BITS
101
        //      11      1       1/0     0         3      QSPI_BITS
102
        //      12      0        1/0     0         4      QSPI_BITS
103
        //      13      1       1/0     0         4      QSPI_BITS
104
        //      14      0        1/0     0         5      QSPI_BITS
105
        //      15      1       1/0     0         5      QSPI_BITS
106
        //      16      0        1/0     0         6      QSPI_BITS
107
        //      17      1       1/1     0         6      QSPI_BITS
108
        //      18      0        1/1     0         7      QSPI_READY
109
        //      19      1       0/1     0         7      QSPI_READY
110
        //      20      0        1/0/V   0         8      QSPI_BITS
111
        //      21      1       1/0     0         8      QSPI_BITS
112
        //      22      0        1/0     0         9      QSPI_BITS
113
        //      23      1       1/0     0         9      QSPI_BITS
114
        //      24      0        1/0     0        10      QSPI_BITS
115
        //      25      1       1/0     0        10      QSPI_BITS
116
        //      26      0        1/0     0        11      QSPI_BITS
117
        //      27      1       1/0     0        11      QSPI_BITS
118
        //      28      0        1/0     0        12      QSPI_BITS
119
        //      29      1       1/0     0        12      QSPI_BITS
120
        //      30      0        1/0     0        13      QSPI_BITS
121
        //      31      1       1/0     0        13      QSPI_BITS
122
        //      32      0        1/0     0        14      QSPI_BITS
123
        //      33      1       1/0     0        14      QSPI_BITS
124
        //      34      0        1/0     0        15      QSPI_READY
125
        //      35      1       1/0     0        15      QSPI_READY
126
        //      36      1       1/0/V   0         -      QSPI_STOP
127
        //      37      1       1/0     0         -      QSPI_STOPB
128
        //      38      1       1/0     1        -      QSPI_IDLE
129
        //      39      1       0/0     1        -
130
        // Now, let's switch from single bit to quad mode
131
        //      40      1       0/0     1        -      QSPI_IDLE
132
        //      41      1       0/1     1        -      QSPI_IDLE
133
        //      42      1       1/0     0         -      QSPI_START
134
        //      43      0        1/0     0         -      QSPI_START
135
        //      44      0        1/0     0         0      QSPI_BITS
136
        //      45      1       1/0     0         0      QSPI_BITS
137
        //      46      0        1/0     0         1      QSPI_BITS
138
        //      47      1       1/0     0         1      QSPI_BITS
139
        //      48      0        1/0     0         2      QSPI_BITS
140
        //      49      1       1/0     0         2      QSPI_BITS
141
        //      50      0        1/0     0         3      QSPI_BITS
142
        //      51      1       1/0     0         3      QSPI_BITS
143
        //      52      0        1/0     0         4      QSPI_BITS
144
        //      53      1       1/0     0         4      QSPI_BITS
145
        //      54      0        1/0     0         5      QSPI_BITS
146
        //      55      1       1/0     0         5      QSPI_BITS
147
        //      56      0        1/0     0         6      QSPI_BITS
148
        //      57      1       1/1/QR  0         6      QSPI_BITS
149
        //      58      0        1/1/QR  0         7      QSPI_READY
150
        //      59      1       0/1/QR  0         7      QSPI_READY
151
        //      60      0        1/0/?/V 0         8-11   QSPI_BITS
152
        //      61      1       1/0/?   0         8-11   QSPI_BITS
153
        //      62      0        1/0/?   0         12-15  QSPI_BITS
154
        //      63      1       1/0/?   0         12-15  QSPI_BITS
155
        //      64      1       1/0/?/V 0        -       QSPI_STOP
156
        //      65      1       1/0/?   0        -       QSPI_STOPB
157
        //      66      1       1/0/?   1       -       QSPI_IDLE
158
        //      67      1       0/0     1       -       QSPI_IDLE
159
        // Now let's try something entirely in Quad read mode, from the
160
        // beginning
161
        //      68      1       0/1/QR  1       -       QSPI_IDLE
162
        //      69      1       1/0     0        -       QSPI_START
163
        //      70      0        1/0     0        -       QSPI_START
164
        //      71      0        1/0     0        0-3     QSPI_BITS
165
        //      72      1       1/0     0        0-3     QSPI_BITS
166
        //      73      0        1/1/QR  0        4-7     QSPI_BITS
167
        //      74      1       0/1/QR  0        4-7     QSPI_BITS
168
        //      75      0        1/?/?/V 0        8-11    QSPI_BITS
169
        //      76      1       1/?/?   0        8-11    QSPI_BITS
170
        //      77      0        1/1/QR  0        12-15   QSPI_BITS
171
        //      78      1       0/1/QR  0        12-15   QSPI_BITS
172
        //      79      0        1/?/?/V 0        16-19   QSPI_BITS
173
        //      80      1       1/0     0        16-19   QSPI_BITS
174
        //      81      0        1/0     0        20-23   QSPI_BITS
175
        //      82      1       1/0     0        20-23   QSPI_BITS
176
        //      83      1       1/0/V   0        -       QSPI_STOP
177
        //      84      1       1/0     0        -       QSPI_STOPB
178
        //      85      1       1/0     1       -       QSPI_IDLE
179
        //      86      1       0/0     1       -       QSPI_IDLE
180
 
181
        wire    i_miso;
182
        assign  i_miso = i_dat[1];
183
 
184
        reg             r_spd, r_dir;
185
        reg     [5:0]    spi_len;
186
        reg     [31:0]   r_word;
187
        reg     [30:0]   r_input;
188
        reg     [2:0]    state;
189
        initial state = `QSPI_IDLE;
190
        initial o_sck   = 1'b1;
191
        initial o_cs_n  = 1'b1;
192
        initial o_dat   = 4'hd;
193
        initial o_valid = 1'b0;
194
        initial o_busy  = 1'b0;
195
        initial r_input = 31'h000;
196
        always @(posedge i_clk)
197
                if ((state == `QSPI_IDLE)&&(o_sck))
198
                begin
199
                        o_cs_n <= 1'b1;
200
                        o_valid <= 1'b0;
201
                        o_busy  <= 1'b0;
202
                        o_mod <= `QSPI_MOD_SPI;
203
                        if (i_wr)
204
                        begin
205
                                r_word <= i_word;
206
                                state <= `QSPI_START;
207
                                r_spd <= i_spd;
208
                                r_dir <= i_dir;
209
                                spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
210
                                o_cs_n <= 1'b0;
211
                                o_busy <= 1'b1;
212
                                o_sck <= 1'b1;
213
                        end
214
                end else if (state == `QSPI_START)
215
                begin // We come in here with sck high, stay here 'til sck is low
216
                        o_sck <= 1'b0;
217
                        if (o_sck == 1'b0)
218
                        begin
219
                                state <= `QSPI_BITS;
220
                                spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );
221
                                if (r_spd)
222
                                        r_word <= { r_word[27:0], 4'h0 };
223
                                else
224
                                        r_word <= { r_word[30:0], 1'b0 };
225
                        end
226
                        o_mod <= (r_spd) ? { 1'b1, r_dir } : `QSPI_MOD_SPI;
227
                        o_cs_n <= 1'b0;
228
                        o_busy <= 1'b1;
229
                        o_valid <= 1'b0;
230
                        if (r_spd)
231
                        begin
232
                                o_dat <= r_word[31:28];
233
                                // r_word <= { r_word[27:0], 4'h0 };
234
                        end else begin
235
                                o_dat <= { 3'b110, r_word[31] };
236
                                // r_word <= { r_word[30:0], 1'b0 };
237
                        end
238
                end else if (~o_sck)
239
                begin
240
                        o_sck <= 1'b1;
241
                        o_busy <= ((state != `QSPI_READY)||(~i_wr));
242
                        o_valid <= 1'b0;
243
                end else if (state == `QSPI_BITS)
244
                begin
245
                        // Should enter into here with at least a spi_len
246
                        // of one, perhaps more
247
                        o_sck <= 1'b0;
248
                        o_busy <= 1'b1;
249
                        if (r_spd)
250
                        begin
251
                                o_dat <= r_word[31:28];
252
                                r_word <= { r_word[27:0], 4'h0 };
253
                                spi_len <= spi_len - 6'h4;
254
                                if (spi_len == 6'h4)
255
                                        state <= `QSPI_READY;
256
                        end else begin
257
                                o_dat <= { 3'b110, r_word[31] };
258
                                r_word <= { r_word[30:0], 1'b0 };
259
                                spi_len <= spi_len - 6'h1;
260
                                if (spi_len == 6'h1)
261
                                        state <= `QSPI_READY;
262
                        end
263
 
264
                        o_valid <= 1'b0;
265
                        if (~o_mod[1])
266
                                r_input <= { r_input[29:0], i_miso };
267
                        else if (o_mod[1])
268
                                r_input <= { r_input[26:0], i_dat };
269
                end else if (state == `QSPI_READY)
270
                begin
271
                        o_valid <= 1'b0;
272
                        o_cs_n <= 1'b0;
273
                        o_busy <= 1'b1;
274
                        // This is the state on the last clock (both low and
275
                        // high clocks) of the data.  Data is valid during
276
                        // this state.  Here we chose to either STOP or
277
                        // continue and transmit more.
278 4 dgisselq
                        o_sck <= (i_hold); // No clocks while holding
279 2 dgisselq
                        if((~o_busy)&&(i_wr))// Acknowledge a new request
280
                        begin
281
                                state <= `QSPI_BITS;
282
                                o_busy <= 1'b1;
283
                                o_sck <= 1'b0;
284
 
285
                                // Read the new request off the bus
286
                                r_spd <= i_spd;
287
                                r_dir <= i_dir;
288
                                // Set up the first bits on the bus
289
                                o_mod <= (i_spd) ? { 1'b1, i_dir } : `QSPI_MOD_SPI;
290
                                if (i_spd)
291
                                begin
292
                                        o_dat <= i_word[31:28];
293
                                        r_word <= { i_word[27:0], 4'h0 };
294
                                        // spi_len <= spi_len - 4;
295
                                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
296
                                                - 6'h4;
297
                                end else begin
298
                                        o_dat <= { 3'b110, i_word[31] };
299
                                        r_word <= { i_word[30:0], 1'b0 };
300
                                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
301
                                                - 6'h1;
302
                                end
303
 
304
                                // Read a bit upon any transition
305
                                o_valid <= 1'b1;
306
                                if (~o_mod[1])
307
                                begin
308
                                        r_input <= { r_input[29:0], i_miso };
309
                                        o_word  <= { r_input[30:0], i_miso };
310
                                end else if (o_mod[1])
311
                                begin
312
                                        r_input <= { r_input[26:0], i_dat };
313
                                        o_word  <= { r_input[27:0], i_dat };
314
                                end
315
                        end else begin
316
                                o_sck <= 1'b1;
317 4 dgisselq
                                state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
318
                                o_busy <= (~i_hold);
319 2 dgisselq
 
320
                                // Read a bit upon any transition
321
                                o_valid <= 1'b1;
322
                                if (~o_mod[1])
323
                                begin
324
                                        r_input <= { r_input[29:0], i_miso };
325
                                        o_word  <= { r_input[30:0], i_miso };
326
                                end else if (o_mod[1])
327
                                begin
328
                                        r_input <= { r_input[26:0], i_dat };
329
                                        o_word  <= { r_input[27:0], i_dat };
330
                                end
331
                        end
332 4 dgisselq
                end else if (state == `QSPI_HOLDING)
333
                begin
334
                        // We need this state so that the o_valid signal
335
                        // can get strobed with our last result.  Otherwise
336
                        // we could just sit in READY waiting for a new command.
337
                        //
338
                        // Incidentally, the change producing this state was
339
                        // the result of a nasty race condition.  See the
340
                        // commends in wbqspiflash for more details.
341
                        //
342
                        o_valid <= 1'b0;
343
                        o_cs_n <= 1'b0;
344
                        o_busy <= 1'b0;
345
                        if((~o_busy)&&(i_wr))// Acknowledge a new request
346
                        begin
347
                                state  <= `QSPI_BITS;
348
                                o_busy <= 1'b1;
349
                                o_sck  <= 1'b0;
350
 
351
                                // Read the new request off the bus
352
                                r_spd <= i_spd;
353
                                r_dir <= i_dir;
354
                                // Set up the first bits on the bus
355
                                o_mod<=(i_spd)?{ 1'b1, i_dir } : `QSPI_MOD_SPI;
356
                                if (i_spd)
357
                                begin
358
                                        o_dat <= i_word[31:28];
359
                                        r_word <= { i_word[27:0], 4'h0 };
360
                                        spi_len<= { 1'b0, i_len, 3'b100 };
361
                                end else begin
362
                                        o_dat <= { 3'b110, i_word[31] };
363
                                        r_word <= { i_word[30:0], 1'b0 };
364
                                        spi_len<= { 1'b0, i_len, 3'b111 };
365
                                end
366
                        end else begin
367
                                o_sck <= 1'b1;
368
                                state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
369
                                o_busy <= (~i_hold);
370
                        end
371 2 dgisselq
                end else if (state == `QSPI_STOP)
372
                begin
373
                        o_sck   <= 1'b1; // Stop the clock
374
                        o_valid <= 1'b0; // Output may have just been valid, but no more
375
                        o_busy  <= 1'b1; // Still busy till port is clear
376
                        state <= `QSPI_STOP_B;
377
                        o_mod <= `QSPI_MOD_SPI;
378
                end else if (state == `QSPI_STOP_B)
379
                begin
380
                        o_cs_n <= 1'b1;
381
                        o_sck <= 1'b1;
382
                        // Do I need this????
383
                        // spi_len <= 3; // Minimum CS high time before next cmd
384
                        state <= `QSPI_IDLE;
385
                        o_valid <= 1'b0;
386
                        o_busy <= 1'b1;
387
                        o_mod <= `QSPI_MOD_SPI;
388
                end else begin // Invalid states, should never get here
389
                        state   <= `QSPI_STOP;
390
                        o_valid <= 1'b0;
391
                        o_busy  <= 1'b1;
392
                        o_cs_n  <= 1'b1;
393
                        o_sck   <= 1'b1;
394
                        o_mod   <= `QSPI_MOD_SPI;
395
                        o_dat   <= 4'hd;
396
                end
397
 
398
endmodule
399
 

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