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[/] [qspiflash/] [trunk/] [rtl/] [llqspi.v] - Blame information for rev 2

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1 2 dgisselq
//
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//
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// Filename:    llqspi.v
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//
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// Project:     FPGA library development (Basys-3 development board)
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//
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// Purpose:     Reads/writes a word (user selectable number of bytes) of data
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//              to/from a Quad SPI port.  The port is understood to be 
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//              a normal SPI port unless the driver requests four bit mode.
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//              When not in use, unlike our previous SPI work, no bits will
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//              toggle.
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//
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// Creator:     Dan Gisselquist
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//              Gisselquist Tecnology, LLC
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//
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// Copyright:   2015
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//
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//
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`define QSPI_IDLE       0
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`define QSPI_START      1
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`define QSPI_BITS       2
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`define QSPI_READY      3
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`define QSPI_STOP       4
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`define QSPI_STOP_B     5
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// Modes
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`define QSPI_MOD_SPI    2'b00
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`define QSPI_MOD_QOUT   2'b10
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`define QSPI_MOD_QIN    2'b11
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module  llqspi(i_clk,
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                // Module interface
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                i_wr, i_hold, i_word, i_len, i_spd, i_dir,
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                        o_word, o_valid, o_busy,
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                // QSPI interface
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                o_sck, o_cs_n, o_mod, o_dat, i_dat,
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                // Wbscope interface
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                o_dbg);
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        input                   i_clk;
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        // Chip interface
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        //      Can send info
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        //              i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,
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        //                      i_word = { 1'b0, 32'info to send },
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        //                      i_len = # of bytes in word-1
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        input                   i_wr, i_hold;
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        input           [31:0]   i_word;
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        input           [1:0]    i_len;  // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits
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        input                   i_spd; // 0 -> normal QPI, 1 -> QSPI
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        input                   i_dir; // 0 -> read, 1 -> write to SPI
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        output  reg     [31:0]   o_word;
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        output  reg             o_valid, o_busy;
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        // Interface with the QSPI lines
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        output  reg             o_sck;
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        output  reg             o_cs_n;
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        output  reg     [1:0]    o_mod;
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        output  reg     [3:0]    o_dat;
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        input           [3:0]    i_dat;
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        output  wire    [22:0]   o_dbg;
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        assign o_dbg = { state, spi_len, // 3+6+ 14
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                        o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };
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        // Timing:
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        //
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        //      Tick    Clk     BSY/WR  CS_n    BIT/MO  STATE
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        //       0      1       0/0     1        -      
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        //       1      1       0/1     1        -
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        //       2      1       1/0     0         -      QSPI_START
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        //       3      0        1/0     0         -      QSPI_START
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        //       4      0        1/0     0         0      QSPI_BITS
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        //       5      1       1/0     0         0      QSPI_BITS
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        //       6      0        1/0     0         1      QSPI_BITS
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        //       7      1       1/0     0         1      QSPI_BITS
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        //       8      0        1/0     0         2      QSPI_BITS
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        //       9      1       1/0     0         2      QSPI_BITS
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        //      10      0        1/0     0         3      QSPI_BITS
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        //      11      1       1/0     0         3      QSPI_BITS
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        //      12      0        1/0     0         4      QSPI_BITS
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        //      13      1       1/0     0         4      QSPI_BITS
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        //      14      0        1/0     0         5      QSPI_BITS
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        //      15      1       1/0     0         5      QSPI_BITS
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        //      16      0        1/0     0         6      QSPI_BITS
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        //      17      1       1/1     0         6      QSPI_BITS
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        //      18      0        1/1     0         7      QSPI_READY
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        //      19      1       0/1     0         7      QSPI_READY
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        //      20      0        1/0/V   0         8      QSPI_BITS
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        //      21      1       1/0     0         8      QSPI_BITS
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        //      22      0        1/0     0         9      QSPI_BITS
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        //      23      1       1/0     0         9      QSPI_BITS
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        //      24      0        1/0     0        10      QSPI_BITS
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        //      25      1       1/0     0        10      QSPI_BITS
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        //      26      0        1/0     0        11      QSPI_BITS
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        //      27      1       1/0     0        11      QSPI_BITS
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        //      28      0        1/0     0        12      QSPI_BITS
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        //      29      1       1/0     0        12      QSPI_BITS
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        //      30      0        1/0     0        13      QSPI_BITS
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        //      31      1       1/0     0        13      QSPI_BITS
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        //      32      0        1/0     0        14      QSPI_BITS
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        //      33      1       1/0     0        14      QSPI_BITS
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        //      34      0        1/0     0        15      QSPI_READY
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        //      35      1       1/0     0        15      QSPI_READY
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        //      36      1       1/0/V   0         -      QSPI_STOP
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        //      37      1       1/0     0         -      QSPI_STOPB
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        //      38      1       1/0     1        -      QSPI_IDLE
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        //      39      1       0/0     1        -
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        // Now, let's switch from single bit to quad mode
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        //      40      1       0/0     1        -      QSPI_IDLE
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        //      41      1       0/1     1        -      QSPI_IDLE
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        //      42      1       1/0     0         -      QSPI_START
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        //      43      0        1/0     0         -      QSPI_START
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        //      44      0        1/0     0         0      QSPI_BITS
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        //      45      1       1/0     0         0      QSPI_BITS
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        //      46      0        1/0     0         1      QSPI_BITS
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        //      47      1       1/0     0         1      QSPI_BITS
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        //      48      0        1/0     0         2      QSPI_BITS
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        //      49      1       1/0     0         2      QSPI_BITS
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        //      50      0        1/0     0         3      QSPI_BITS
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        //      51      1       1/0     0         3      QSPI_BITS
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        //      52      0        1/0     0         4      QSPI_BITS
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        //      53      1       1/0     0         4      QSPI_BITS
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        //      54      0        1/0     0         5      QSPI_BITS
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        //      55      1       1/0     0         5      QSPI_BITS
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        //      56      0        1/0     0         6      QSPI_BITS
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        //      57      1       1/1/QR  0         6      QSPI_BITS
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        //      58      0        1/1/QR  0         7      QSPI_READY
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        //      59      1       0/1/QR  0         7      QSPI_READY
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        //      60      0        1/0/?/V 0         8-11   QSPI_BITS
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        //      61      1       1/0/?   0         8-11   QSPI_BITS
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        //      62      0        1/0/?   0         12-15  QSPI_BITS
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        //      63      1       1/0/?   0         12-15  QSPI_BITS
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        //      64      1       1/0/?/V 0        -       QSPI_STOP
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        //      65      1       1/0/?   0        -       QSPI_STOPB
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        //      66      1       1/0/?   1       -       QSPI_IDLE
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        //      67      1       0/0     1       -       QSPI_IDLE
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        // Now let's try something entirely in Quad read mode, from the
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        // beginning
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        //      68      1       0/1/QR  1       -       QSPI_IDLE
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        //      69      1       1/0     0        -       QSPI_START
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        //      70      0        1/0     0        -       QSPI_START
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        //      71      0        1/0     0        0-3     QSPI_BITS
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        //      72      1       1/0     0        0-3     QSPI_BITS
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        //      73      0        1/1/QR  0        4-7     QSPI_BITS
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        //      74      1       0/1/QR  0        4-7     QSPI_BITS
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        //      75      0        1/?/?/V 0        8-11    QSPI_BITS
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        //      76      1       1/?/?   0        8-11    QSPI_BITS
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        //      77      0        1/1/QR  0        12-15   QSPI_BITS
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        //      78      1       0/1/QR  0        12-15   QSPI_BITS
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        //      79      0        1/?/?/V 0        16-19   QSPI_BITS
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        //      80      1       1/0     0        16-19   QSPI_BITS
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        //      81      0        1/0     0        20-23   QSPI_BITS
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        //      82      1       1/0     0        20-23   QSPI_BITS
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        //      83      1       1/0/V   0        -       QSPI_STOP
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        //      84      1       1/0     0        -       QSPI_STOPB
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        //      85      1       1/0     1       -       QSPI_IDLE
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        //      86      1       0/0     1       -       QSPI_IDLE
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        wire    i_miso;
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        assign  i_miso = i_dat[1];
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        reg             r_spd, r_dir;
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        reg     [5:0]    spi_len;
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        reg     [31:0]   r_word;
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        reg     [30:0]   r_input;
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        reg     [2:0]    state;
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        initial state = `QSPI_IDLE;
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        initial o_sck   = 1'b1;
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        initial o_cs_n  = 1'b1;
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        initial o_dat   = 4'hd;
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        initial o_valid = 1'b0;
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        initial o_busy  = 1'b0;
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        initial r_input = 31'h000;
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        always @(posedge i_clk)
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                if ((state == `QSPI_IDLE)&&(o_sck))
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                begin
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                        o_cs_n <= 1'b1;
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                        o_valid <= 1'b0;
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                        o_busy  <= 1'b0;
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                        o_mod <= `QSPI_MOD_SPI;
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                        if (i_wr)
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                        begin
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                                r_word <= i_word;
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                                state <= `QSPI_START;
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                                r_spd <= i_spd;
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                                r_dir <= i_dir;
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                                spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
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                                o_cs_n <= 1'b0;
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                                o_busy <= 1'b1;
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                                o_sck <= 1'b1;
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                        end
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                end else if (state == `QSPI_START)
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                begin // We come in here with sck high, stay here 'til sck is low
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                        o_sck <= 1'b0;
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                        if (o_sck == 1'b0)
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                        begin
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                                state <= `QSPI_BITS;
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                                spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );
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                                if (r_spd)
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                                        r_word <= { r_word[27:0], 4'h0 };
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                                else
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                                        r_word <= { r_word[30:0], 1'b0 };
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                        end
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                        o_mod <= (r_spd) ? { 1'b1, r_dir } : `QSPI_MOD_SPI;
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                        o_cs_n <= 1'b0;
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                        o_busy <= 1'b1;
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                        o_valid <= 1'b0;
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                        if (r_spd)
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                        begin
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                                o_dat <= r_word[31:28];
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                                // r_word <= { r_word[27:0], 4'h0 };
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                        end else begin
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                                o_dat <= { 3'b110, r_word[31] };
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                                // r_word <= { r_word[30:0], 1'b0 };
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                        end
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                end else if (~o_sck)
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                begin
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                        o_sck <= 1'b1;
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                        o_busy <= ((state != `QSPI_READY)||(~i_wr));
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                        o_valid <= 1'b0;
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                end else if (state == `QSPI_BITS)
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                begin
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                        // Should enter into here with at least a spi_len
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                        // of one, perhaps more
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                        o_sck <= 1'b0;
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                        o_busy <= 1'b1;
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                        if (r_spd)
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                        begin
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                                o_dat <= r_word[31:28];
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                                r_word <= { r_word[27:0], 4'h0 };
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                                spi_len <= spi_len - 6'h4;
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                                if (spi_len == 6'h4)
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                                        state <= `QSPI_READY;
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                        end else begin
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                                o_dat <= { 3'b110, r_word[31] };
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                                r_word <= { r_word[30:0], 1'b0 };
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                                spi_len <= spi_len - 6'h1;
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                                if (spi_len == 6'h1)
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                                        state <= `QSPI_READY;
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                        end
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                        o_valid <= 1'b0;
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                        if (~o_mod[1])
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                                r_input <= { r_input[29:0], i_miso };
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                        else if (o_mod[1])
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                                r_input <= { r_input[26:0], i_dat };
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                end else if (state == `QSPI_READY)
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                begin
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                        o_valid <= 1'b0;
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                        o_cs_n <= 1'b0;
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                        o_busy <= 1'b1;
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                        // This is the state on the last clock (both low and
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                        // high clocks) of the data.  Data is valid during
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                        // this state.  Here we chose to either STOP or
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                        // continue and transmit more.
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                        o_sck <= (i_hold); // Stay here on hold, no clocks
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                        if((~o_busy)&&(i_wr))// Acknowledge a new request
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                        begin
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                                state <= `QSPI_BITS;
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                                o_busy <= 1'b1;
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                                o_sck <= 1'b0;
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                                // Read the new request off the bus
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                                r_spd <= i_spd;
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                                r_dir <= i_dir;
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                                // Set up the first bits on the bus
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                                o_mod <= (i_spd) ? { 1'b1, i_dir } : `QSPI_MOD_SPI;
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                                if (i_spd)
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                                begin
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                                        o_dat <= i_word[31:28];
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                                        r_word <= { i_word[27:0], 4'h0 };
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                                        // spi_len <= spi_len - 4;
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                                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
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                                                - 6'h4;
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                                end else begin
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                                        o_dat <= { 3'b110, i_word[31] };
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                                        r_word <= { i_word[30:0], 1'b0 };
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                                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
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                                                - 6'h1;
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                                end
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                                // Read a bit upon any transition
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                                o_valid <= 1'b1;
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                                if (~o_mod[1])
283
                                begin
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                                        r_input <= { r_input[29:0], i_miso };
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                                        o_word  <= { r_input[30:0], i_miso };
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                                end else if (o_mod[1])
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                                begin
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                                        r_input <= { r_input[26:0], i_dat };
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                                        o_word  <= { r_input[27:0], i_dat };
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                                end
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                        end else if (i_hold)
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                        begin // Stay here, holding the clock high, if the user
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                                // has more data, but it isn't ready yet.
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                                o_busy <= 1'b0;
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                        end else begin
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                                o_sck <= 1'b1;
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                                state <= `QSPI_STOP;
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299
                                // Read a bit upon any transition
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                                o_valid <= 1'b1;
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                                if (~o_mod[1])
302
                                begin
303
                                        r_input <= { r_input[29:0], i_miso };
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                                        o_word  <= { r_input[30:0], i_miso };
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                                end else if (o_mod[1])
306
                                begin
307
                                        r_input <= { r_input[26:0], i_dat };
308
                                        o_word  <= { r_input[27:0], i_dat };
309
                                end
310
                        end
311
                end else if (state == `QSPI_STOP)
312
                begin
313
                        o_sck   <= 1'b1; // Stop the clock
314
                        o_valid <= 1'b0; // Output may have just been valid, but no more
315
                        o_busy  <= 1'b1; // Still busy till port is clear
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                        state <= `QSPI_STOP_B;
317
                        o_mod <= `QSPI_MOD_SPI;
318
                end else if (state == `QSPI_STOP_B)
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                begin
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                        o_cs_n <= 1'b1;
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                        o_sck <= 1'b1;
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                        // Do I need this????
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                        // spi_len <= 3; // Minimum CS high time before next cmd
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                        state <= `QSPI_IDLE;
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                        o_valid <= 1'b0;
326
                        o_busy <= 1'b1;
327
                        o_mod <= `QSPI_MOD_SPI;
328
                end else begin // Invalid states, should never get here
329
                        state   <= `QSPI_STOP;
330
                        o_valid <= 1'b0;
331
                        o_busy  <= 1'b1;
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                        o_cs_n  <= 1'b1;
333
                        o_sck   <= 1'b1;
334
                        o_mod   <= `QSPI_MOD_SPI;
335
                        o_dat   <= 4'hd;
336
                end
337
 
338
endmodule
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