URL https://opencores.org/ocsvn/qspiflash/qspiflash/trunk

Subversion Repositories qspiflash

[/] [qspiflash/] [trunk/] [rtl/] [llqspi.v] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log


//
//
// Filename:    llqspi.v
//
// Project:     FPGA library development (Basys-3 development board)
//
// Purpose:     Reads/writes a word (user selectable number of bytes) of data
//              to/from a Quad SPI port.  The port is understood to be 
//              a normal SPI port unless the driver requests four bit mode.
//              When not in use, unlike our previous SPI work, no bits will
//              toggle.
//
// Creator:     Dan Gisselquist
//              Gisselquist Tecnology, LLC
//
// Copyright:   2015
//
//
`define QSPI_IDLE       0
`define QSPI_START      1
`define QSPI_BITS       2
`define QSPI_READY      3
`define QSPI_STOP       4
`define QSPI_STOP_B     5
 
// Modes
`define QSPI_MOD_SPI    2'b00
`define QSPI_MOD_QOUT   2'b10
`define QSPI_MOD_QIN    2'b11
 
module  llqspi(i_clk,
                // Module interface
                i_wr, i_hold, i_word, i_len, i_spd, i_dir,
                        o_word, o_valid, o_busy,
                // QSPI interface
                o_sck, o_cs_n, o_mod, o_dat, i_dat,
                // Wbscope interface
                o_dbg);
        input                   i_clk;
        // Chip interface
        //      Can send info
        //              i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,
        //                      i_word = { 1'b0, 32'info to send },
        //                      i_len = # of bytes in word-1
        input                   i_wr, i_hold;
        input           [31:0]   i_word;
        input           [1:0]    i_len;  // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits
        input                   i_spd; // 0 -> normal QPI, 1 -> QSPI
        input                   i_dir; // 0 -> read, 1 -> write to SPI
        output  reg     [31:0]   o_word;
        output  reg             o_valid, o_busy;
        // Interface with the QSPI lines
        output  reg             o_sck;
        output  reg             o_cs_n;
        output  reg     [1:0]    o_mod;
        output  reg     [3:0]    o_dat;
        input           [3:0]    i_dat;
        output  wire    [22:0]   o_dbg;
 
        assign o_dbg = { state, spi_len, // 3+6+ 14
                        o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };
 
        // Timing:
        //
        //      Tick    Clk     BSY/WR  CS_n    BIT/MO  STATE
        //       0      1       0/0     1        -      
        //       1      1       0/1     1        -
        //       2      1       1/0     0         -      QSPI_START
        //       3      0        1/0     0         -      QSPI_START
        //       4      0        1/0     0         0      QSPI_BITS
        //       5      1       1/0     0         0      QSPI_BITS
        //       6      0        1/0     0         1      QSPI_BITS
        //       7      1       1/0     0         1      QSPI_BITS
        //       8      0        1/0     0         2      QSPI_BITS
        //       9      1       1/0     0         2      QSPI_BITS
        //      10      0        1/0     0         3      QSPI_BITS
        //      11      1       1/0     0         3      QSPI_BITS
        //      12      0        1/0     0         4      QSPI_BITS
        //      13      1       1/0     0         4      QSPI_BITS
        //      14      0        1/0     0         5      QSPI_BITS
        //      15      1       1/0     0         5      QSPI_BITS
        //      16      0        1/0     0         6      QSPI_BITS
        //      17      1       1/1     0         6      QSPI_BITS
        //      18      0        1/1     0         7      QSPI_READY
        //      19      1       0/1     0         7      QSPI_READY
        //      20      0        1/0/V   0         8      QSPI_BITS
        //      21      1       1/0     0         8      QSPI_BITS
        //      22      0        1/0     0         9      QSPI_BITS
        //      23      1       1/0     0         9      QSPI_BITS
        //      24      0        1/0     0        10      QSPI_BITS
        //      25      1       1/0     0        10      QSPI_BITS
        //      26      0        1/0     0        11      QSPI_BITS
        //      27      1       1/0     0        11      QSPI_BITS
        //      28      0        1/0     0        12      QSPI_BITS
        //      29      1       1/0     0        12      QSPI_BITS
        //      30      0        1/0     0        13      QSPI_BITS
        //      31      1       1/0     0        13      QSPI_BITS
        //      32      0        1/0     0        14      QSPI_BITS
        //      33      1       1/0     0        14      QSPI_BITS
        //      34      0        1/0     0        15      QSPI_READY
        //      35      1       1/0     0        15      QSPI_READY
        //      36      1       1/0/V   0         -      QSPI_STOP
        //      37      1       1/0     0         -      QSPI_STOPB
        //      38      1       1/0     1        -      QSPI_IDLE
        //      39      1       0/0     1        -
        // Now, let's switch from single bit to quad mode
        //      40      1       0/0     1        -      QSPI_IDLE
        //      41      1       0/1     1        -      QSPI_IDLE
        //      42      1       1/0     0         -      QSPI_START
        //      43      0        1/0     0         -      QSPI_START
        //      44      0        1/0     0         0      QSPI_BITS
        //      45      1       1/0     0         0      QSPI_BITS
        //      46      0        1/0     0         1      QSPI_BITS
        //      47      1       1/0     0         1      QSPI_BITS
        //      48      0        1/0     0         2      QSPI_BITS
        //      49      1       1/0     0         2      QSPI_BITS
        //      50      0        1/0     0         3      QSPI_BITS
        //      51      1       1/0     0         3      QSPI_BITS
        //      52      0        1/0     0         4      QSPI_BITS
        //      53      1       1/0     0         4      QSPI_BITS
        //      54      0        1/0     0         5      QSPI_BITS
        //      55      1       1/0     0         5      QSPI_BITS
        //      56      0        1/0     0         6      QSPI_BITS
        //      57      1       1/1/QR  0         6      QSPI_BITS
        //      58      0        1/1/QR  0         7      QSPI_READY
        //      59      1       0/1/QR  0         7      QSPI_READY
        //      60      0        1/0/?/V 0         8-11   QSPI_BITS
        //      61      1       1/0/?   0         8-11   QSPI_BITS
        //      62      0        1/0/?   0         12-15  QSPI_BITS
        //      63      1       1/0/?   0         12-15  QSPI_BITS
        //      64      1       1/0/?/V 0        -       QSPI_STOP
        //      65      1       1/0/?   0        -       QSPI_STOPB
        //      66      1       1/0/?   1       -       QSPI_IDLE
        //      67      1       0/0     1       -       QSPI_IDLE
        // Now let's try something entirely in Quad read mode, from the
        // beginning
        //      68      1       0/1/QR  1       -       QSPI_IDLE
        //      69      1       1/0     0        -       QSPI_START
        //      70      0        1/0     0        -       QSPI_START
        //      71      0        1/0     0        0-3     QSPI_BITS
        //      72      1       1/0     0        0-3     QSPI_BITS
        //      73      0        1/1/QR  0        4-7     QSPI_BITS
        //      74      1       0/1/QR  0        4-7     QSPI_BITS
        //      75      0        1/?/?/V 0        8-11    QSPI_BITS
        //      76      1       1/?/?   0        8-11    QSPI_BITS
        //      77      0        1/1/QR  0        12-15   QSPI_BITS
        //      78      1       0/1/QR  0        12-15   QSPI_BITS
        //      79      0        1/?/?/V 0        16-19   QSPI_BITS
        //      80      1       1/0     0        16-19   QSPI_BITS
        //      81      0        1/0     0        20-23   QSPI_BITS
        //      82      1       1/0     0        20-23   QSPI_BITS
        //      83      1       1/0/V   0        -       QSPI_STOP
        //      84      1       1/0     0        -       QSPI_STOPB
        //      85      1       1/0     1       -       QSPI_IDLE
        //      86      1       0/0     1       -       QSPI_IDLE
 
        wire    i_miso;
        assign  i_miso = i_dat[1];
 
        reg             r_spd, r_dir;
        reg     [5:0]    spi_len;
        reg     [31:0]   r_word;
        reg     [30:0]   r_input;
        reg     [2:0]    state;
        initial state = `QSPI_IDLE;
        initial o_sck   = 1'b1;
        initial o_cs_n  = 1'b1;
        initial o_dat   = 4'hd;
        initial o_valid = 1'b0;
        initial o_busy  = 1'b0;
        initial r_input = 31'h000;
        always @(posedge i_clk)
                if ((state == `QSPI_IDLE)&&(o_sck))
                begin
                        o_cs_n <= 1'b1;
                        o_valid <= 1'b0;
                        o_busy  <= 1'b0;
                        o_mod <= `QSPI_MOD_SPI;
                        if (i_wr)
                        begin
                                r_word <= i_word;
                                state <= `QSPI_START;
                                r_spd <= i_spd;
                                r_dir <= i_dir;
                                spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
                                o_cs_n <= 1'b0;
                                o_busy <= 1'b1;
                                o_sck <= 1'b1;
                        end
                end else if (state == `QSPI_START)
                begin // We come in here with sck high, stay here 'til sck is low
                        o_sck <= 1'b0;
                        if (o_sck == 1'b0)
                        begin
                                state <= `QSPI_BITS;
                                spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );
                                if (r_spd)
                                        r_word <= { r_word[27:0], 4'h0 };
                                else
                                        r_word <= { r_word[30:0], 1'b0 };
                        end
                        o_mod <= (r_spd) ? { 1'b1, r_dir } : `QSPI_MOD_SPI;
                        o_cs_n <= 1'b0;
                        o_busy <= 1'b1;
                        o_valid <= 1'b0;
                        if (r_spd)
                        begin
                                o_dat <= r_word[31:28];
                                // r_word <= { r_word[27:0], 4'h0 };
                        end else begin
                                o_dat <= { 3'b110, r_word[31] };
                                // r_word <= { r_word[30:0], 1'b0 };
                        end
                end else if (~o_sck)
                begin
                        o_sck <= 1'b1;
                        o_busy <= ((state != `QSPI_READY)||(~i_wr));
                        o_valid <= 1'b0;
                end else if (state == `QSPI_BITS)
                begin
                        // Should enter into here with at least a spi_len
                        // of one, perhaps more
                        o_sck <= 1'b0;
                        o_busy <= 1'b1;
                        if (r_spd)
                        begin
                                o_dat <= r_word[31:28];
                                r_word <= { r_word[27:0], 4'h0 };
                                spi_len <= spi_len - 6'h4;
                                if (spi_len == 6'h4)
                                        state <= `QSPI_READY;
                        end else begin
                                o_dat <= { 3'b110, r_word[31] };
                                r_word <= { r_word[30:0], 1'b0 };
                                spi_len <= spi_len - 6'h1;
                                if (spi_len == 6'h1)
                                        state <= `QSPI_READY;
                        end
 
                        o_valid <= 1'b0;
                        if (~o_mod[1])
                                r_input <= { r_input[29:0], i_miso };
                        else if (o_mod[1])
                                r_input <= { r_input[26:0], i_dat };
                end else if (state == `QSPI_READY)
                begin
                        o_valid <= 1'b0;
                        o_cs_n <= 1'b0;
                        o_busy <= 1'b1;
                        // This is the state on the last clock (both low and
                        // high clocks) of the data.  Data is valid during
                        // this state.  Here we chose to either STOP or
                        // continue and transmit more.
                        o_sck <= (i_hold); // Stay here on hold, no clocks
                        if((~o_busy)&&(i_wr))// Acknowledge a new request
                        begin
                                state <= `QSPI_BITS;
                                o_busy <= 1'b1;
                                o_sck <= 1'b0;
 
                                // Read the new request off the bus
                                r_spd <= i_spd;
                                r_dir <= i_dir;
                                // Set up the first bits on the bus
                                o_mod <= (i_spd) ? { 1'b1, i_dir } : `QSPI_MOD_SPI;
                                if (i_spd)
                                begin
                                        o_dat <= i_word[31:28];
                                        r_word <= { i_word[27:0], 4'h0 };
                                        // spi_len <= spi_len - 4;
                                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
                                                - 6'h4;
                                end else begin
                                        o_dat <= { 3'b110, i_word[31] };
                                        r_word <= { i_word[30:0], 1'b0 };
                                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
                                                - 6'h1;
                                end
 
                                // Read a bit upon any transition
                                o_valid <= 1'b1;
                                if (~o_mod[1])
                                begin
                                        r_input <= { r_input[29:0], i_miso };
                                        o_word  <= { r_input[30:0], i_miso };
                                end else if (o_mod[1])
                                begin
                                        r_input <= { r_input[26:0], i_dat };
                                        o_word  <= { r_input[27:0], i_dat };
                                end
                        end else if (i_hold)
                        begin // Stay here, holding the clock high, if the user
                                // has more data, but it isn't ready yet.
                                o_busy <= 1'b0;
                        end else begin
                                o_sck <= 1'b1;
                                state <= `QSPI_STOP;
 
                                // Read a bit upon any transition
                                o_valid <= 1'b1;
                                if (~o_mod[1])
                                begin
                                        r_input <= { r_input[29:0], i_miso };
                                        o_word  <= { r_input[30:0], i_miso };
                                end else if (o_mod[1])
                                begin
                                        r_input <= { r_input[26:0], i_dat };
                                        o_word  <= { r_input[27:0], i_dat };
                                end
                        end
                end else if (state == `QSPI_STOP)
                begin
                        o_sck   <= 1'b1; // Stop the clock
                        o_valid <= 1'b0; // Output may have just been valid, but no more
                        o_busy  <= 1'b1; // Still busy till port is clear
                        state <= `QSPI_STOP_B;
                        o_mod <= `QSPI_MOD_SPI;
                end else if (state == `QSPI_STOP_B)
                begin
                        o_cs_n <= 1'b1;
                        o_sck <= 1'b1;
                        // Do I need this????
                        // spi_len <= 3; // Minimum CS high time before next cmd
                        state <= `QSPI_IDLE;
                        o_valid <= 1'b0;
                        o_busy <= 1'b1;
                        o_mod <= `QSPI_MOD_SPI;
                end else begin // Invalid states, should never get here
                        state   <= `QSPI_STOP;
                        o_valid <= 1'b0;
                        o_busy  <= 1'b1;
                        o_cs_n  <= 1'b1;
                        o_sck   <= 1'b1;
                        o_mod   <= `QSPI_MOD_SPI;
                        o_dat   <= 4'hd;
                end
 
endmodule
 

Browse

Tools

Subversion Repositories qspiflash

[/] [qspiflash/] [trunk/] [rtl/] [llqspi.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dgisselq	`//`
2			`//`
3			`// Filename: llqspi.v`
4			`//`
5			`// Project: FPGA library development (Basys-3 development board)`
6			`//`
7			`// Purpose: Reads/writes a word (user selectable number of bytes) of data`
8			`// to/from a Quad SPI port. The port is understood to be`
9			`// a normal SPI port unless the driver requests four bit mode.`
10			`// When not in use, unlike our previous SPI work, no bits will`
11			`// toggle.`
12			`//`
13			`// Creator: Dan Gisselquist`
14			`// Gisselquist Tecnology, LLC`
15			`//`
16			`// Copyright: 2015`
17			`//`
18			`//`
19			`define QSPI_IDLE 0
20			`define QSPI_START 1
21			`define QSPI_BITS 2
22			`define QSPI_READY 3
23			`define QSPI_STOP 4
24			`define QSPI_STOP_B 5
25
26			`// Modes`
27			`define QSPI_MOD_SPI 2'b00
28			`define QSPI_MOD_QOUT 2'b10
29			`define QSPI_MOD_QIN 2'b11
30
31			`module llqspi(i_clk,`
32			`// Module interface`
33			`i_wr, i_hold, i_word, i_len, i_spd, i_dir,`
34			`o_word, o_valid, o_busy,`
35			`// QSPI interface`
36			`o_sck, o_cs_n, o_mod, o_dat, i_dat,`
37			`// Wbscope interface`
38			`o_dbg);`
39			`input i_clk;`
40			`// Chip interface`
41			`// Can send info`
42			`// i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,`
43			`// i_word = { 1'b0, 32'info to send },`
44			`// i_len = # of bytes in word-1`
45			`input i_wr, i_hold;`
46			`input [31:0] i_word;`
47			`input [1:0] i_len; // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits`
48			`input i_spd; // 0 -> normal QPI, 1 -> QSPI`
49			`input i_dir; // 0 -> read, 1 -> write to SPI`
50			`output reg [31:0] o_word;`
51			`output reg o_valid, o_busy;`
52			`// Interface with the QSPI lines`
53			`output reg o_sck;`
54			`output reg o_cs_n;`
55			`output reg [1:0] o_mod;`
56			`output reg [3:0] o_dat;`
57			`input [3:0] i_dat;`
58			`output wire [22:0] o_dbg;`
59
60			`assign o_dbg = { state, spi_len, // 3+6+ 14`
61			`o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };`
62
63			`// Timing:`
64			`//`
65			`// Tick Clk BSY/WR CS_n BIT/MO STATE`
66			`// 0 1 0/0 1 -`
67			`// 1 1 0/1 1 -`
68			`// 2 1 1/0 0 - QSPI_START`
69			`// 3 0 1/0 0 - QSPI_START`
70			`// 4 0 1/0 0 0 QSPI_BITS`
71			`// 5 1 1/0 0 0 QSPI_BITS`
72			`// 6 0 1/0 0 1 QSPI_BITS`
73			`// 7 1 1/0 0 1 QSPI_BITS`
74			`// 8 0 1/0 0 2 QSPI_BITS`
75			`// 9 1 1/0 0 2 QSPI_BITS`
76			`// 10 0 1/0 0 3 QSPI_BITS`
77			`// 11 1 1/0 0 3 QSPI_BITS`
78			`// 12 0 1/0 0 4 QSPI_BITS`
79			`// 13 1 1/0 0 4 QSPI_BITS`
80			`// 14 0 1/0 0 5 QSPI_BITS`
81			`// 15 1 1/0 0 5 QSPI_BITS`
82			`// 16 0 1/0 0 6 QSPI_BITS`
83			`// 17 1 1/1 0 6 QSPI_BITS`
84			`// 18 0 1/1 0 7 QSPI_READY`
85			`// 19 1 0/1 0 7 QSPI_READY`
86			`// 20 0 1/0/V 0 8 QSPI_BITS`
87			`// 21 1 1/0 0 8 QSPI_BITS`
88			`// 22 0 1/0 0 9 QSPI_BITS`
89			`// 23 1 1/0 0 9 QSPI_BITS`
90			`// 24 0 1/0 0 10 QSPI_BITS`
91			`// 25 1 1/0 0 10 QSPI_BITS`
92			`// 26 0 1/0 0 11 QSPI_BITS`
93			`// 27 1 1/0 0 11 QSPI_BITS`
94			`// 28 0 1/0 0 12 QSPI_BITS`
95			`// 29 1 1/0 0 12 QSPI_BITS`
96			`// 30 0 1/0 0 13 QSPI_BITS`
97			`// 31 1 1/0 0 13 QSPI_BITS`
98			`// 32 0 1/0 0 14 QSPI_BITS`
99			`// 33 1 1/0 0 14 QSPI_BITS`
100			`// 34 0 1/0 0 15 QSPI_READY`
101			`// 35 1 1/0 0 15 QSPI_READY`
102			`// 36 1 1/0/V 0 - QSPI_STOP`
103			`// 37 1 1/0 0 - QSPI_STOPB`
104			`// 38 1 1/0 1 - QSPI_IDLE`
105			`// 39 1 0/0 1 -`
106			`// Now, let's switch from single bit to quad mode`
107			`// 40 1 0/0 1 - QSPI_IDLE`
108			`// 41 1 0/1 1 - QSPI_IDLE`
109			`// 42 1 1/0 0 - QSPI_START`
110			`// 43 0 1/0 0 - QSPI_START`
111			`// 44 0 1/0 0 0 QSPI_BITS`
112			`// 45 1 1/0 0 0 QSPI_BITS`
113			`// 46 0 1/0 0 1 QSPI_BITS`
114			`// 47 1 1/0 0 1 QSPI_BITS`
115			`// 48 0 1/0 0 2 QSPI_BITS`
116			`// 49 1 1/0 0 2 QSPI_BITS`
117			`// 50 0 1/0 0 3 QSPI_BITS`
118			`// 51 1 1/0 0 3 QSPI_BITS`
119			`// 52 0 1/0 0 4 QSPI_BITS`
120			`// 53 1 1/0 0 4 QSPI_BITS`
121			`// 54 0 1/0 0 5 QSPI_BITS`
122			`// 55 1 1/0 0 5 QSPI_BITS`
123			`// 56 0 1/0 0 6 QSPI_BITS`
124			`// 57 1 1/1/QR 0 6 QSPI_BITS`
125			`// 58 0 1/1/QR 0 7 QSPI_READY`
126			`// 59 1 0/1/QR 0 7 QSPI_READY`
127			`// 60 0 1/0/?/V 0 8-11 QSPI_BITS`
128			`// 61 1 1/0/? 0 8-11 QSPI_BITS`
129			`// 62 0 1/0/? 0 12-15 QSPI_BITS`
130			`// 63 1 1/0/? 0 12-15 QSPI_BITS`
131			`// 64 1 1/0/?/V 0 - QSPI_STOP`
132			`// 65 1 1/0/? 0 - QSPI_STOPB`
133			`// 66 1 1/0/? 1 - QSPI_IDLE`
134			`// 67 1 0/0 1 - QSPI_IDLE`
135			`// Now let's try something entirely in Quad read mode, from the`
136			`// beginning`
137			`// 68 1 0/1/QR 1 - QSPI_IDLE`
138			`// 69 1 1/0 0 - QSPI_START`
139			`// 70 0 1/0 0 - QSPI_START`
140			`// 71 0 1/0 0 0-3 QSPI_BITS`
141			`// 72 1 1/0 0 0-3 QSPI_BITS`
142			`// 73 0 1/1/QR 0 4-7 QSPI_BITS`
143			`// 74 1 0/1/QR 0 4-7 QSPI_BITS`
144			`// 75 0 1/?/?/V 0 8-11 QSPI_BITS`
145			`// 76 1 1/?/? 0 8-11 QSPI_BITS`
146			`// 77 0 1/1/QR 0 12-15 QSPI_BITS`
147			`// 78 1 0/1/QR 0 12-15 QSPI_BITS`
148			`// 79 0 1/?/?/V 0 16-19 QSPI_BITS`
149			`// 80 1 1/0 0 16-19 QSPI_BITS`
150			`// 81 0 1/0 0 20-23 QSPI_BITS`
151			`// 82 1 1/0 0 20-23 QSPI_BITS`
152			`// 83 1 1/0/V 0 - QSPI_STOP`
153			`// 84 1 1/0 0 - QSPI_STOPB`
154			`// 85 1 1/0 1 - QSPI_IDLE`
155			`// 86 1 0/0 1 - QSPI_IDLE`
156
157			`wire i_miso;`
158			`assign i_miso = i_dat[1];`
159
160			`reg r_spd, r_dir;`
161			`reg [5:0] spi_len;`
162			`reg [31:0] r_word;`
163			`reg [30:0] r_input;`
164			`reg [2:0] state;`
165			initial state = `QSPI_IDLE;
166			`initial o_sck = 1'b1;`
167			`initial o_cs_n = 1'b1;`
168			`initial o_dat = 4'hd;`
169			`initial o_valid = 1'b0;`
170			`initial o_busy = 1'b0;`
171			`initial r_input = 31'h000;`
172			`always @(posedge i_clk)`
173			if ((state == `QSPI_IDLE)&&(o_sck))
174			`begin`
175			`o_cs_n <= 1'b1;`
176			`o_valid <= 1'b0;`
177			`o_busy <= 1'b0;`
178			o_mod <= `QSPI_MOD_SPI;
179			`if (i_wr)`
180			`begin`
181			`r_word <= i_word;`
182			state <= `QSPI_START;
183			`r_spd <= i_spd;`
184			`r_dir <= i_dir;`
185			`spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;`
186			`o_cs_n <= 1'b0;`
187			`o_busy <= 1'b1;`
188			`o_sck <= 1'b1;`
189			`end`
190			end else if (state == `QSPI_START)
191			`begin // We come in here with sck high, stay here 'til sck is low`
192			`o_sck <= 1'b0;`
193			`if (o_sck == 1'b0)`
194			`begin`
195			state <= `QSPI_BITS;
196			`spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );`
197			`if (r_spd)`
198			`r_word <= { r_word[27:0], 4'h0 };`
199			`else`
200			`r_word <= { r_word[30:0], 1'b0 };`
201			`end`
202			o_mod <= (r_spd) ? { 1'b1, r_dir } : `QSPI_MOD_SPI;
203			`o_cs_n <= 1'b0;`
204			`o_busy <= 1'b1;`
205			`o_valid <= 1'b0;`
206			`if (r_spd)`
207			`begin`
208			`o_dat <= r_word[31:28];`
209			`// r_word <= { r_word[27:0], 4'h0 };`
210			`end else begin`
211			`o_dat <= { 3'b110, r_word[31] };`
212			`// r_word <= { r_word[30:0], 1'b0 };`
213			`end`
214			`end else if (~o_sck)`
215			`begin`
216			`o_sck <= 1'b1;`
217			o_busy <= ((state != `QSPI_READY)\|\|(~i_wr));
218			`o_valid <= 1'b0;`
219			end else if (state == `QSPI_BITS)
220			`begin`
221			`// Should enter into here with at least a spi_len`
222			`// of one, perhaps more`
223			`o_sck <= 1'b0;`
224			`o_busy <= 1'b1;`
225			`if (r_spd)`
226			`begin`
227			`o_dat <= r_word[31:28];`
228			`r_word <= { r_word[27:0], 4'h0 };`
229			`spi_len <= spi_len - 6'h4;`
230			`if (spi_len == 6'h4)`
231			state <= `QSPI_READY;
232			`end else begin`
233			`o_dat <= { 3'b110, r_word[31] };`
234			`r_word <= { r_word[30:0], 1'b0 };`
235			`spi_len <= spi_len - 6'h1;`
236			`if (spi_len == 6'h1)`
237			state <= `QSPI_READY;
238			`end`
239
240			`o_valid <= 1'b0;`
241			`if (~o_mod[1])`
242			`r_input <= { r_input[29:0], i_miso };`
243			`else if (o_mod[1])`
244			`r_input <= { r_input[26:0], i_dat };`
245			end else if (state == `QSPI_READY)
246			`begin`
247			`o_valid <= 1'b0;`
248			`o_cs_n <= 1'b0;`
249			`o_busy <= 1'b1;`
250			`// This is the state on the last clock (both low and`
251			`// high clocks) of the data. Data is valid during`
252			`// this state. Here we chose to either STOP or`
253			`// continue and transmit more.`
254			`o_sck <= (i_hold); // Stay here on hold, no clocks`
255			`if((~o_busy)&&(i_wr))// Acknowledge a new request`
256			`begin`
257			state <= `QSPI_BITS;
258			`o_busy <= 1'b1;`
259			`o_sck <= 1'b0;`
260
261			`// Read the new request off the bus`
262			`r_spd <= i_spd;`
263			`r_dir <= i_dir;`
264			`// Set up the first bits on the bus`
265			o_mod <= (i_spd) ? { 1'b1, i_dir } : `QSPI_MOD_SPI;
266			`if (i_spd)`
267			`begin`
268			`o_dat <= i_word[31:28];`
269			`r_word <= { i_word[27:0], 4'h0 };`
270			`// spi_len <= spi_len - 4;`
271			`spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8`
272			`- 6'h4;`
273			`end else begin`
274			`o_dat <= { 3'b110, i_word[31] };`
275			`r_word <= { i_word[30:0], 1'b0 };`
276			`spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8`
277			`- 6'h1;`
278			`end`
279
280			`// Read a bit upon any transition`
281			`o_valid <= 1'b1;`
282			`if (~o_mod[1])`
283			`begin`
284			`r_input <= { r_input[29:0], i_miso };`
285			`o_word <= { r_input[30:0], i_miso };`
286			`end else if (o_mod[1])`
287			`begin`
288			`r_input <= { r_input[26:0], i_dat };`
289			`o_word <= { r_input[27:0], i_dat };`
290			`end`
291			`end else if (i_hold)`
292			`begin // Stay here, holding the clock high, if the user`
293			`// has more data, but it isn't ready yet.`
294			`o_busy <= 1'b0;`
295			`end else begin`
296			`o_sck <= 1'b1;`
297			state <= `QSPI_STOP;
298
299			`// Read a bit upon any transition`
300			`o_valid <= 1'b1;`
301			`if (~o_mod[1])`
302			`begin`
303			`r_input <= { r_input[29:0], i_miso };`
304			`o_word <= { r_input[30:0], i_miso };`
305			`end else if (o_mod[1])`
306			`begin`
307			`r_input <= { r_input[26:0], i_dat };`
308			`o_word <= { r_input[27:0], i_dat };`
309			`end`
310			`end`
311			end else if (state == `QSPI_STOP)
312			`begin`
313			`o_sck <= 1'b1; // Stop the clock`
314			`o_valid <= 1'b0; // Output may have just been valid, but no more`
315			`o_busy <= 1'b1; // Still busy till port is clear`
316			state <= `QSPI_STOP_B;
317			o_mod <= `QSPI_MOD_SPI;
318			end else if (state == `QSPI_STOP_B)
319			`begin`
320			`o_cs_n <= 1'b1;`
321			`o_sck <= 1'b1;`
322			`// Do I need this????`
323			`// spi_len <= 3; // Minimum CS high time before next cmd`
324			state <= `QSPI_IDLE;
325			`o_valid <= 1'b0;`
326			`o_busy <= 1'b1;`
327			o_mod <= `QSPI_MOD_SPI;
328			`end else begin // Invalid states, should never get here`
329			state <= `QSPI_STOP;
330			`o_valid <= 1'b0;`
331			`o_busy <= 1'b1;`
332			`o_cs_n <= 1'b1;`
333			`o_sck <= 1'b1;`
334			o_mod <= `QSPI_MOD_SPI;
335			`o_dat <= 4'hd;`
336			`end`
337
338			`endmodule`
339