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///////////////////////////////////////////////////////////////////////////
//
// Filename:    llqspi.v
//
// Project:     Wishbone Controlled Quad SPI Flash Controller
//
// Purpose:     Reads/writes a word (user selectable number of bytes) of data
//              to/from a Quad SPI port.  The port is understood to be 
//              a normal SPI port unless the driver requests four bit mode.
//              When not in use, unlike our previous SPI work, no bits will
//              toggle.
//
// Creator:     Dan Gisselquist
//              Gisselquist Tecnology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////
`define QSPI_IDLE       0
`define QSPI_START      1
`define QSPI_BITS       2
`define QSPI_READY      3
`define QSPI_STOP       4
`define QSPI_STOP_B     5
 
// Modes
`define QSPI_MOD_SPI    2'b00
`define QSPI_MOD_QOUT   2'b10
`define QSPI_MOD_QIN    2'b11
 
module  llqspi(i_clk,
                // Module interface
                i_wr, i_hold, i_word, i_len, i_spd, i_dir,
                        o_word, o_valid, o_busy,
                // QSPI interface
                o_sck, o_cs_n, o_mod, o_dat, i_dat);
        input                   i_clk;
        // Chip interface
        //      Can send info
        //              i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,
        //                      i_word = { 1'b0, 32'info to send },
        //                      i_len = # of bytes in word-1
        input                   i_wr, i_hold;
        input           [31:0]   i_word;
        input           [1:0]    i_len;  // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits
        input                   i_spd; // 0 -> normal QPI, 1 -> QSPI
        input                   i_dir; // 0 -> read, 1 -> write to SPI
        output  reg     [31:0]   o_word;
        output  reg             o_valid, o_busy;
        // Interface with the QSPI lines
        output  reg             o_sck;
        output  reg             o_cs_n;
        output  reg     [1:0]    o_mod;
        output  reg     [3:0]    o_dat;
        input           [3:0]    i_dat;
 
        // Timing:
        //
        //      Tick    Clk     BSY/WR  CS_n    BIT/MO  STATE
        //       0      1       0/0     1        -      
        //       1      1       0/1     1        -
        //       2      1       1/0     0         -      QSPI_START
        //       3      0        1/0     0         -      QSPI_START
        //       4      0        1/0     0         0      QSPI_BITS
        //       5      1       1/0     0         0      QSPI_BITS
        //       6      0        1/0     0         1      QSPI_BITS
        //       7      1       1/0     0         1      QSPI_BITS
        //       8      0        1/0     0         2      QSPI_BITS
        //       9      1       1/0     0         2      QSPI_BITS
        //      10      0        1/0     0         3      QSPI_BITS
        //      11      1       1/0     0         3      QSPI_BITS
        //      12      0        1/0     0         4      QSPI_BITS
        //      13      1       1/0     0         4      QSPI_BITS
        //      14      0        1/0     0         5      QSPI_BITS
        //      15      1       1/0     0         5      QSPI_BITS
        //      16      0        1/0     0         6      QSPI_BITS
        //      17      1       1/1     0         6      QSPI_BITS
        //      18      0        1/1     0         7      QSPI_READY
        //      19      1       0/1     0         7      QSPI_READY
        //      20      0        1/0/V   0         8      QSPI_BITS
        //      21      1       1/0     0         8      QSPI_BITS
        //      22      0        1/0     0         9      QSPI_BITS
        //      23      1       1/0     0         9      QSPI_BITS
        //      24      0        1/0     0        10      QSPI_BITS
        //      25      1       1/0     0        10      QSPI_BITS
        //      26      0        1/0     0        11      QSPI_BITS
        //      27      1       1/0     0        11      QSPI_BITS
        //      28      0        1/0     0        12      QSPI_BITS
        //      29      1       1/0     0        12      QSPI_BITS
        //      30      0        1/0     0        13      QSPI_BITS
        //      31      1       1/0     0        13      QSPI_BITS
        //      32      0        1/0     0        14      QSPI_BITS
        //      33      1       1/0     0        14      QSPI_BITS
        //      34      0        1/0     0        15      QSPI_READY
        //      35      1       1/0     0        15      QSPI_READY
        //      36      1       1/0/V   0         -      QSPI_STOP
        //      37      1       1/0     0         -      QSPI_STOPB
        //      38      1       1/0     1        -      QSPI_IDLE
        //      39      1       0/0     1        -
        // Now, let's switch from single bit to quad mode
        //      40      1       0/0     1        -      QSPI_IDLE
        //      41      1       0/1     1        -      QSPI_IDLE
        //      42      1       1/0     0         -      QSPI_START
        //      43      0        1/0     0         -      QSPI_START
        //      44      0        1/0     0         0      QSPI_BITS
        //      45      1       1/0     0         0      QSPI_BITS
        //      46      0        1/0     0         1      QSPI_BITS
        //      47      1       1/0     0         1      QSPI_BITS
        //      48      0        1/0     0         2      QSPI_BITS
        //      49      1       1/0     0         2      QSPI_BITS
        //      50      0        1/0     0         3      QSPI_BITS
        //      51      1       1/0     0         3      QSPI_BITS
        //      52      0        1/0     0         4      QSPI_BITS
        //      53      1       1/0     0         4      QSPI_BITS
        //      54      0        1/0     0         5      QSPI_BITS
        //      55      1       1/0     0         5      QSPI_BITS
        //      56      0        1/0     0         6      QSPI_BITS
        //      57      1       1/1/QR  0         6      QSPI_BITS
        //      58      0        1/1/QR  0         7      QSPI_READY
        //      59      1       0/1/QR  0         7      QSPI_READY
        //      60      0        1/0/?/V 0         8-11   QSPI_BITS
        //      61      1       1/0/?   0         8-11   QSPI_BITS
        //      62      0        1/0/?   0         12-15  QSPI_BITS
        //      63      1       1/0/?   0         12-15  QSPI_BITS
        //      64      1       1/0/?/V 0        -       QSPI_STOP
        //      65      1       1/0/?   0        -       QSPI_STOPB
        //      66      1       1/0/?   1       -       QSPI_IDLE
        //      67      1       0/0     1       -       QSPI_IDLE
        // Now let's try something entirely in Quad read mode, from the
        // beginning
        //      68      1       0/1/QR  1       -       QSPI_IDLE
        //      69      1       1/0     0        -       QSPI_START
        //      70      0        1/0     0        -       QSPI_START
        //      71      0        1/0     0        0-3     QSPI_BITS
        //      72      1       1/0     0        0-3     QSPI_BITS
        //      73      0        1/1/QR  0        4-7     QSPI_BITS
        //      74      1       0/1/QR  0        4-7     QSPI_BITS
        //      75      0        1/?/?/V 0        8-11    QSPI_BITS
        //      76      1       1/?/?   0        8-11    QSPI_BITS
        //      77      0        1/1/QR  0        12-15   QSPI_BITS
        //      78      1       0/1/QR  0        12-15   QSPI_BITS
        //      79      0        1/?/?/V 0        16-19   QSPI_BITS
        //      80      1       1/0     0        16-19   QSPI_BITS
        //      81      0        1/0     0        20-23   QSPI_BITS
        //      82      1       1/0     0        20-23   QSPI_BITS
        //      83      1       1/0/V   0        -       QSPI_STOP
        //      84      1       1/0     0        -       QSPI_STOPB
        //      85      1       1/0     1       -       QSPI_IDLE
        //      86      1       0/0     1       -       QSPI_IDLE
 
        wire    i_miso;
        assign  i_miso = i_dat[1];
 
        reg             r_spd, r_dir;
        reg     [5:0]    spi_len;
        reg     [31:0]   r_word;
        reg     [30:0]   r_input;
        reg     [2:0]    state;
        initial state = `QSPI_IDLE;
        initial o_sck   = 1'b1;
        initial o_cs_n  = 1'b1;
        initial o_dat   = 4'hd;
        initial o_valid = 1'b0;
        initial o_busy  = 1'b0;
        initial r_input = 31'h000;
        always @(posedge i_clk)
                if ((state == `QSPI_IDLE)&&(o_sck))
                begin
                        o_cs_n <= 1'b1;
                        o_valid <= 1'b0;
                        o_busy  <= 1'b0;
                        o_mod <= `QSPI_MOD_SPI;
                        if (i_wr)
                        begin
                                r_word <= i_word;
                                state <= `QSPI_START;
                                r_spd <= i_spd;
                                r_dir <= i_dir;
                                spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
                                o_cs_n <= 1'b0;
                                o_busy <= 1'b1;
                                o_sck <= 1'b1;
                        end
                end else if (state == `QSPI_START)
                begin // We come in here with sck high, stay here 'til sck is low
                        o_sck <= 1'b0;
                        if (o_sck == 1'b0)
                        begin
                                state <= `QSPI_BITS;
                                spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );
                                if (r_spd)
                                        r_word <= { r_word[27:0], 4'h0 };
                                else
                                        r_word <= { r_word[30:0], 1'b0 };
                        end
                        o_mod <= (r_spd) ? { 1'b1, r_dir } : `QSPI_MOD_SPI;
                        o_cs_n <= 1'b0;
                        o_busy <= 1'b1;
                        o_valid <= 1'b0;
                        if (r_spd)
                        begin
                                o_dat <= r_word[31:28];
                                // r_word <= { r_word[27:0], 4'h0 };
                        end else begin
                                o_dat <= { 3'b110, r_word[31] };
                                // r_word <= { r_word[30:0], 1'b0 };
                        end
                end else if (~o_sck)
                begin
                        o_sck <= 1'b1;
                        o_busy <= ((state != `QSPI_READY)||(~i_wr));
                        o_valid <= 1'b0;
                end else if (state == `QSPI_BITS)
                begin
                        // Should enter into here with at least a spi_len
                        // of one, perhaps more
                        o_sck <= 1'b0;
                        o_busy <= 1'b1;
                        if (r_spd)
                        begin
                                o_dat <= r_word[31:28];
                                r_word <= { r_word[27:0], 4'h0 };
                                spi_len <= spi_len - 6'h4;
                                if (spi_len == 6'h4)
                                        state <= `QSPI_READY;
                        end else begin
                                o_dat <= { 3'b110, r_word[31] };
                                r_word <= { r_word[30:0], 1'b0 };
                                spi_len <= spi_len - 6'h1;
                                if (spi_len == 6'h1)
                                        state <= `QSPI_READY;
                        end
 
                        o_valid <= 1'b0;
                        if (~o_mod[1])
                                r_input <= { r_input[29:0], i_miso };
                        else if (o_mod[1])
                                r_input <= { r_input[26:0], i_dat };
                end else if (state == `QSPI_READY)
                begin
                        o_valid <= 1'b0;
                        o_cs_n <= 1'b0;
                        o_busy <= 1'b1;
                        // This is the state on the last clock (both low and
                        // high clocks) of the data.  Data is valid during
                        // this state.  Here we chose to either STOP or
                        // continue and transmit more.
                        o_sck <= (i_hold); // Stay here on hold, no clocks
                        if((~o_busy)&&(i_wr))// Acknowledge a new request
                        begin
                                state <= `QSPI_BITS;
                                o_busy <= 1'b1;
                                o_sck <= 1'b0;
 
                                // Read the new request off the bus
                                r_spd <= i_spd;
                                r_dir <= i_dir;
                                // Set up the first bits on the bus
                                o_mod <= (i_spd) ? { 1'b1, i_dir } : `QSPI_MOD_SPI;
                                if (i_spd)
                                begin
                                        o_dat <= i_word[31:28];
                                        r_word <= { i_word[27:0], 4'h0 };
                                        // spi_len <= spi_len - 4;
                                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
                                                - 6'h4;
                                end else begin
                                        o_dat <= { 3'b110, i_word[31] };
                                        r_word <= { i_word[30:0], 1'b0 };
                                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
                                                - 6'h1;
                                end
 
                                // Read a bit upon any transition
                                o_valid <= 1'b1;
                                if (~o_mod[1])
                                begin
                                        r_input <= { r_input[29:0], i_miso };
                                        o_word  <= { r_input[30:0], i_miso };
                                end else if (o_mod[1])
                                begin
                                        r_input <= { r_input[26:0], i_dat };
                                        o_word  <= { r_input[27:0], i_dat };
                                end
                        end else if (i_hold)
                        begin // Stay here, holding the clock high, if the user
                                // has more data, but it isn't ready yet.
                                o_busy <= 1'b0;
                        end else begin
                                o_sck <= 1'b1;
                                state <= `QSPI_STOP;
 
                                // Read a bit upon any transition
                                o_valid <= 1'b1;
                                if (~o_mod[1])
                                begin
                                        r_input <= { r_input[29:0], i_miso };
                                        o_word  <= { r_input[30:0], i_miso };
                                end else if (o_mod[1])
                                begin
                                        r_input <= { r_input[26:0], i_dat };
                                        o_word  <= { r_input[27:0], i_dat };
                                end
                        end
                end else if (state == `QSPI_STOP)
                begin
                        o_sck   <= 1'b1; // Stop the clock
                        o_valid <= 1'b0; // Output may have just been valid, but no more
                        o_busy  <= 1'b1; // Still busy till port is clear
                        state <= `QSPI_STOP_B;
                        o_mod <= `QSPI_MOD_SPI;
                end else if (state == `QSPI_STOP_B)
                begin
                        o_cs_n <= 1'b1;
                        o_sck <= 1'b1;
                        // Do I need this????
                        // spi_len <= 3; // Minimum CS high time before next cmd
                        state <= `QSPI_IDLE;
                        o_valid <= 1'b0;
                        o_busy <= 1'b1;
                        o_mod <= `QSPI_MOD_SPI;
                end else begin // Invalid states, should never get here
                        state   <= `QSPI_STOP;
                        o_valid <= 1'b0;
                        o_busy  <= 1'b1;
                        o_cs_n  <= 1'b1;
                        o_sck   <= 1'b1;
                        o_mod   <= `QSPI_MOD_SPI;
                        o_dat   <= 4'hd;
                end
 
endmodule
 

Line No.	Rev	Author	Line
1	3	dgisselq	`///////////////////////////////////////////////////////////////////////////`
2	2	dgisselq	`//`
3			`// Filename: llqspi.v`
4			`//`
5	3	dgisselq	`// Project: Wishbone Controlled Quad SPI Flash Controller`
6	2	dgisselq	`//`
7			`// Purpose: Reads/writes a word (user selectable number of bytes) of data`
8			`// to/from a Quad SPI port. The port is understood to be`
9			`// a normal SPI port unless the driver requests four bit mode.`
10			`// When not in use, unlike our previous SPI work, no bits will`
11			`// toggle.`
12			`//`
13			`// Creator: Dan Gisselquist`
14			`// Gisselquist Tecnology, LLC`
15			`//`
16	3	dgisselq	`///////////////////////////////////////////////////////////////////////////`
17	2	dgisselq	`//`
18	3	dgisselq	`// Copyright (C) 2015, Gisselquist Technology, LLC`
19	2	dgisselq	`//`
20	3	dgisselq	`// This program is free software (firmware): you can redistribute it and/or`
21			`// modify it under the terms of the GNU General Public License as published`
22			`// by the Free Software Foundation, either version 3 of the License, or (at`
23			`// your option) any later version.`
24			`//`
25			`// This program is distributed in the hope that it will be useful, but WITHOUT`
26			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
27			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
28			`// for more details.`
29			`//`
30			`// You should have received a copy of the GNU General Public License along`
31			`// with this program. (It's in the $(ROOT)/doc directory, run make with no`
32			`// target there if the PDF file isn't present.) If not, see`
33			`// <http://www.gnu.org/licenses/> for a copy.`
34			`//`
35			`// License: GPL, v3, as defined and found on www.gnu.org,`
36			`// http://www.gnu.org/licenses/gpl.html`
37			`//`
38			`//`
39			`///////////////////////////////////////////////////////////////////////////`
40	2	dgisselq	`define QSPI_IDLE 0
41			`define QSPI_START 1
42			`define QSPI_BITS 2
43			`define QSPI_READY 3
44			`define QSPI_STOP 4
45			`define QSPI_STOP_B 5
46
47			`// Modes`
48			`define QSPI_MOD_SPI 2'b00
49			`define QSPI_MOD_QOUT 2'b10
50			`define QSPI_MOD_QIN 2'b11
51
52			`module llqspi(i_clk,`
53			`// Module interface`
54			`i_wr, i_hold, i_word, i_len, i_spd, i_dir,`
55			`o_word, o_valid, o_busy,`
56			`// QSPI interface`
57	3	dgisselq	`o_sck, o_cs_n, o_mod, o_dat, i_dat);`
58	2	dgisselq	`input i_clk;`
59			`// Chip interface`
60			`// Can send info`
61			`// i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,`
62			`// i_word = { 1'b0, 32'info to send },`
63			`// i_len = # of bytes in word-1`
64			`input i_wr, i_hold;`
65			`input [31:0] i_word;`
66			`input [1:0] i_len; // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits`
67			`input i_spd; // 0 -> normal QPI, 1 -> QSPI`
68			`input i_dir; // 0 -> read, 1 -> write to SPI`
69			`output reg [31:0] o_word;`
70			`output reg o_valid, o_busy;`
71			`// Interface with the QSPI lines`
72			`output reg o_sck;`
73			`output reg o_cs_n;`
74			`output reg [1:0] o_mod;`
75			`output reg [3:0] o_dat;`
76			`input [3:0] i_dat;`
77
78			`// Timing:`
79			`//`
80			`// Tick Clk BSY/WR CS_n BIT/MO STATE`
81			`// 0 1 0/0 1 -`
82			`// 1 1 0/1 1 -`
83			`// 2 1 1/0 0 - QSPI_START`
84			`// 3 0 1/0 0 - QSPI_START`
85			`// 4 0 1/0 0 0 QSPI_BITS`
86			`// 5 1 1/0 0 0 QSPI_BITS`
87			`// 6 0 1/0 0 1 QSPI_BITS`
88			`// 7 1 1/0 0 1 QSPI_BITS`
89			`// 8 0 1/0 0 2 QSPI_BITS`
90			`// 9 1 1/0 0 2 QSPI_BITS`
91			`// 10 0 1/0 0 3 QSPI_BITS`
92			`// 11 1 1/0 0 3 QSPI_BITS`
93			`// 12 0 1/0 0 4 QSPI_BITS`
94			`// 13 1 1/0 0 4 QSPI_BITS`
95			`// 14 0 1/0 0 5 QSPI_BITS`
96			`// 15 1 1/0 0 5 QSPI_BITS`
97			`// 16 0 1/0 0 6 QSPI_BITS`
98			`// 17 1 1/1 0 6 QSPI_BITS`
99			`// 18 0 1/1 0 7 QSPI_READY`
100			`// 19 1 0/1 0 7 QSPI_READY`
101			`// 20 0 1/0/V 0 8 QSPI_BITS`
102			`// 21 1 1/0 0 8 QSPI_BITS`
103			`// 22 0 1/0 0 9 QSPI_BITS`
104			`// 23 1 1/0 0 9 QSPI_BITS`
105			`// 24 0 1/0 0 10 QSPI_BITS`
106			`// 25 1 1/0 0 10 QSPI_BITS`
107			`// 26 0 1/0 0 11 QSPI_BITS`
108			`// 27 1 1/0 0 11 QSPI_BITS`
109			`// 28 0 1/0 0 12 QSPI_BITS`
110			`// 29 1 1/0 0 12 QSPI_BITS`
111			`// 30 0 1/0 0 13 QSPI_BITS`
112			`// 31 1 1/0 0 13 QSPI_BITS`
113			`// 32 0 1/0 0 14 QSPI_BITS`
114			`// 33 1 1/0 0 14 QSPI_BITS`
115			`// 34 0 1/0 0 15 QSPI_READY`
116			`// 35 1 1/0 0 15 QSPI_READY`
117			`// 36 1 1/0/V 0 - QSPI_STOP`
118			`// 37 1 1/0 0 - QSPI_STOPB`
119			`// 38 1 1/0 1 - QSPI_IDLE`
120			`// 39 1 0/0 1 -`
121			`// Now, let's switch from single bit to quad mode`
122			`// 40 1 0/0 1 - QSPI_IDLE`
123			`// 41 1 0/1 1 - QSPI_IDLE`
124			`// 42 1 1/0 0 - QSPI_START`
125			`// 43 0 1/0 0 - QSPI_START`
126			`// 44 0 1/0 0 0 QSPI_BITS`
127			`// 45 1 1/0 0 0 QSPI_BITS`
128			`// 46 0 1/0 0 1 QSPI_BITS`
129			`// 47 1 1/0 0 1 QSPI_BITS`
130			`// 48 0 1/0 0 2 QSPI_BITS`
131			`// 49 1 1/0 0 2 QSPI_BITS`
132			`// 50 0 1/0 0 3 QSPI_BITS`
133			`// 51 1 1/0 0 3 QSPI_BITS`
134			`// 52 0 1/0 0 4 QSPI_BITS`
135			`// 53 1 1/0 0 4 QSPI_BITS`
136			`// 54 0 1/0 0 5 QSPI_BITS`
137			`// 55 1 1/0 0 5 QSPI_BITS`
138			`// 56 0 1/0 0 6 QSPI_BITS`
139			`// 57 1 1/1/QR 0 6 QSPI_BITS`
140			`// 58 0 1/1/QR 0 7 QSPI_READY`
141			`// 59 1 0/1/QR 0 7 QSPI_READY`
142			`// 60 0 1/0/?/V 0 8-11 QSPI_BITS`
143			`// 61 1 1/0/? 0 8-11 QSPI_BITS`
144			`// 62 0 1/0/? 0 12-15 QSPI_BITS`
145			`// 63 1 1/0/? 0 12-15 QSPI_BITS`
146			`// 64 1 1/0/?/V 0 - QSPI_STOP`
147			`// 65 1 1/0/? 0 - QSPI_STOPB`
148			`// 66 1 1/0/? 1 - QSPI_IDLE`
149			`// 67 1 0/0 1 - QSPI_IDLE`
150			`// Now let's try something entirely in Quad read mode, from the`
151			`// beginning`
152			`// 68 1 0/1/QR 1 - QSPI_IDLE`
153			`// 69 1 1/0 0 - QSPI_START`
154			`// 70 0 1/0 0 - QSPI_START`
155			`// 71 0 1/0 0 0-3 QSPI_BITS`
156			`// 72 1 1/0 0 0-3 QSPI_BITS`
157			`// 73 0 1/1/QR 0 4-7 QSPI_BITS`
158			`// 74 1 0/1/QR 0 4-7 QSPI_BITS`
159			`// 75 0 1/?/?/V 0 8-11 QSPI_BITS`
160			`// 76 1 1/?/? 0 8-11 QSPI_BITS`
161			`// 77 0 1/1/QR 0 12-15 QSPI_BITS`
162			`// 78 1 0/1/QR 0 12-15 QSPI_BITS`
163			`// 79 0 1/?/?/V 0 16-19 QSPI_BITS`
164			`// 80 1 1/0 0 16-19 QSPI_BITS`
165			`// 81 0 1/0 0 20-23 QSPI_BITS`
166			`// 82 1 1/0 0 20-23 QSPI_BITS`
167			`// 83 1 1/0/V 0 - QSPI_STOP`
168			`// 84 1 1/0 0 - QSPI_STOPB`
169			`// 85 1 1/0 1 - QSPI_IDLE`
170			`// 86 1 0/0 1 - QSPI_IDLE`
171
172			`wire i_miso;`
173			`assign i_miso = i_dat[1];`
174
175			`reg r_spd, r_dir;`
176			`reg [5:0] spi_len;`
177			`reg [31:0] r_word;`
178			`reg [30:0] r_input;`
179			`reg [2:0] state;`
180			initial state = `QSPI_IDLE;
181			`initial o_sck = 1'b1;`
182			`initial o_cs_n = 1'b1;`
183			`initial o_dat = 4'hd;`
184			`initial o_valid = 1'b0;`
185			`initial o_busy = 1'b0;`
186			`initial r_input = 31'h000;`
187			`always @(posedge i_clk)`
188			if ((state == `QSPI_IDLE)&&(o_sck))
189			`begin`
190			`o_cs_n <= 1'b1;`
191			`o_valid <= 1'b0;`
192			`o_busy <= 1'b0;`
193			o_mod <= `QSPI_MOD_SPI;
194			`if (i_wr)`
195			`begin`
196			`r_word <= i_word;`
197			state <= `QSPI_START;
198			`r_spd <= i_spd;`
199			`r_dir <= i_dir;`
200			`spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;`
201			`o_cs_n <= 1'b0;`
202			`o_busy <= 1'b1;`
203			`o_sck <= 1'b1;`
204			`end`
205			end else if (state == `QSPI_START)
206			`begin // We come in here with sck high, stay here 'til sck is low`
207			`o_sck <= 1'b0;`
208			`if (o_sck == 1'b0)`
209			`begin`
210			state <= `QSPI_BITS;
211			`spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );`
212			`if (r_spd)`
213			`r_word <= { r_word[27:0], 4'h0 };`
214			`else`
215			`r_word <= { r_word[30:0], 1'b0 };`
216			`end`
217			o_mod <= (r_spd) ? { 1'b1, r_dir } : `QSPI_MOD_SPI;
218			`o_cs_n <= 1'b0;`
219			`o_busy <= 1'b1;`
220			`o_valid <= 1'b0;`
221			`if (r_spd)`
222			`begin`
223			`o_dat <= r_word[31:28];`
224			`// r_word <= { r_word[27:0], 4'h0 };`
225			`end else begin`
226			`o_dat <= { 3'b110, r_word[31] };`
227			`// r_word <= { r_word[30:0], 1'b0 };`
228			`end`
229			`end else if (~o_sck)`
230			`begin`
231			`o_sck <= 1'b1;`
232			o_busy <= ((state != `QSPI_READY)\|\|(~i_wr));
233			`o_valid <= 1'b0;`
234			end else if (state == `QSPI_BITS)
235			`begin`
236			`// Should enter into here with at least a spi_len`
237			`// of one, perhaps more`
238			`o_sck <= 1'b0;`
239			`o_busy <= 1'b1;`
240			`if (r_spd)`
241			`begin`
242			`o_dat <= r_word[31:28];`
243			`r_word <= { r_word[27:0], 4'h0 };`
244			`spi_len <= spi_len - 6'h4;`
245			`if (spi_len == 6'h4)`
246			state <= `QSPI_READY;
247			`end else begin`
248			`o_dat <= { 3'b110, r_word[31] };`
249			`r_word <= { r_word[30:0], 1'b0 };`
250			`spi_len <= spi_len - 6'h1;`
251			`if (spi_len == 6'h1)`
252			state <= `QSPI_READY;
253			`end`
254
255			`o_valid <= 1'b0;`
256			`if (~o_mod[1])`
257			`r_input <= { r_input[29:0], i_miso };`
258			`else if (o_mod[1])`
259			`r_input <= { r_input[26:0], i_dat };`
260			end else if (state == `QSPI_READY)
261			`begin`
262			`o_valid <= 1'b0;`
263			`o_cs_n <= 1'b0;`
264			`o_busy <= 1'b1;`
265			`// This is the state on the last clock (both low and`
266			`// high clocks) of the data. Data is valid during`
267			`// this state. Here we chose to either STOP or`
268			`// continue and transmit more.`
269			`o_sck <= (i_hold); // Stay here on hold, no clocks`
270			`if((~o_busy)&&(i_wr))// Acknowledge a new request`
271			`begin`
272			state <= `QSPI_BITS;
273			`o_busy <= 1'b1;`
274			`o_sck <= 1'b0;`
275
276			`// Read the new request off the bus`
277			`r_spd <= i_spd;`
278			`r_dir <= i_dir;`
279			`// Set up the first bits on the bus`
280			o_mod <= (i_spd) ? { 1'b1, i_dir } : `QSPI_MOD_SPI;
281			`if (i_spd)`
282			`begin`
283			`o_dat <= i_word[31:28];`
284			`r_word <= { i_word[27:0], 4'h0 };`
285			`// spi_len <= spi_len - 4;`
286			`spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8`
287			`- 6'h4;`
288			`end else begin`
289			`o_dat <= { 3'b110, i_word[31] };`
290			`r_word <= { i_word[30:0], 1'b0 };`
291			`spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8`
292			`- 6'h1;`
293			`end`
294
295			`// Read a bit upon any transition`
296			`o_valid <= 1'b1;`
297			`if (~o_mod[1])`
298			`begin`
299			`r_input <= { r_input[29:0], i_miso };`
300			`o_word <= { r_input[30:0], i_miso };`
301			`end else if (o_mod[1])`
302			`begin`
303			`r_input <= { r_input[26:0], i_dat };`
304			`o_word <= { r_input[27:0], i_dat };`
305			`end`
306			`end else if (i_hold)`
307			`begin // Stay here, holding the clock high, if the user`
308			`// has more data, but it isn't ready yet.`
309			`o_busy <= 1'b0;`
310			`end else begin`
311			`o_sck <= 1'b1;`
312			state <= `QSPI_STOP;
313
314			`// Read a bit upon any transition`
315			`o_valid <= 1'b1;`
316			`if (~o_mod[1])`
317			`begin`
318			`r_input <= { r_input[29:0], i_miso };`
319			`o_word <= { r_input[30:0], i_miso };`
320			`end else if (o_mod[1])`
321			`begin`
322			`r_input <= { r_input[26:0], i_dat };`
323			`o_word <= { r_input[27:0], i_dat };`
324			`end`
325			`end`
326			end else if (state == `QSPI_STOP)
327			`begin`
328			`o_sck <= 1'b1; // Stop the clock`
329			`o_valid <= 1'b0; // Output may have just been valid, but no more`
330			`o_busy <= 1'b1; // Still busy till port is clear`
331			state <= `QSPI_STOP_B;
332			o_mod <= `QSPI_MOD_SPI;
333			end else if (state == `QSPI_STOP_B)
334			`begin`
335			`o_cs_n <= 1'b1;`
336			`o_sck <= 1'b1;`
337			`// Do I need this????`
338			`// spi_len <= 3; // Minimum CS high time before next cmd`
339			state <= `QSPI_IDLE;
340			`o_valid <= 1'b0;`
341			`o_busy <= 1'b1;`
342			o_mod <= `QSPI_MOD_SPI;
343			`end else begin // Invalid states, should never get here`
344			state <= `QSPI_STOP;
345			`o_valid <= 1'b0;`
346			`o_busy <= 1'b1;`
347			`o_cs_n <= 1'b1;`
348			`o_sck <= 1'b1;`
349			o_mod <= `QSPI_MOD_SPI;
350			`o_dat <= 4'hd;`
351			`end`
352
353			`endmodule`
354

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