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[/] [qspiflash/] [trunk/] [rtl/] [wbqspiflash.v] - Blame information for rev 14

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1 14 dgisselq
////////////////////////////////////////////////////////////////////////////////
2 2 dgisselq
//
3
// Filename:    wbspiflash.v
4
//
5 3 dgisselq
// Project:     Wishbone Controlled Quad SPI Flash Controller
6 2 dgisselq
//
7
// Purpose:     Access a Quad SPI flash via a WISHBONE interface.  This
8
//              includes both read and write (and erase) commands to the SPI
9
//              flash.  All read/write commands are accomplished using the
10
//              high speed (4-bit) interface.  Further, the device will be
11
//              left/kept in the 4-bit read interface mode between accesses,
12
//              for a minimum read latency.
13
//
14 3 dgisselq
//      Wishbone Registers (See spec sheet for more detail):
15 2 dgisselq
//      0: local config(r) / erase commands(w) / deep power down cmds / etc.
16
//      R: (Write in Progress), (dirty-block), (spi_port_busy), 1'b0, 9'h00,
17
//              { last_erased_sector, 14'h00 } if (WIP)
18
//              else { current_sector_being_erased, 14'h00 }
19
//              current if write in progress, last if written
20
//      W: (1'b1 to erase), (12'h ignored), next_erased_block, 14'h ignored)
21 3 dgisselq
//      1: Configuration register
22
//      2: Status register (R/w)
23
//      3: Read ID (read only)
24 2 dgisselq
//      (19 bits): Data (R/w, but expect writes to take a while)
25
//              
26
//
27 14 dgisselq
// Creator:     Dan Gisselquist, Ph.D.
28 8 dgisselq
//              Gisselquist Technology, LLC
29 2 dgisselq
//
30 14 dgisselq
////////////////////////////////////////////////////////////////////////////////
31 2 dgisselq
//
32 14 dgisselq
// Copyright (C) 2015,2017, Gisselquist Technology, LLC
33 2 dgisselq
//
34 3 dgisselq
// This program is free software (firmware): you can redistribute it and/or
35
// modify it under the terms of  the GNU General Public License as published
36
// by the Free Software Foundation, either version 3 of the License, or (at
37
// your option) any later version.
38
//
39
// This program is distributed in the hope that it will be useful, but WITHOUT
40
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
41
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
42
// for more details.
43
//
44
// You should have received a copy of the GNU General Public License along
45 14 dgisselq
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
46 3 dgisselq
// target there if the PDF file isn't present.)  If not, see
47
// <http://www.gnu.org/licenses/> for a copy.
48
//
49
// License:     GPL, v3, as defined and found on www.gnu.org,
50
//              http://www.gnu.org/licenses/gpl.html
51
//
52
//
53 14 dgisselq
////////////////////////////////////////////////////////////////////////////////
54 7 dgisselq
//
55
`include "flash_config.v"
56 14 dgisselq
`default_nettype        none
57 7 dgisselq
//
58 14 dgisselq
`define WBQSPI_RESET            5'h0
59
`define WBQSPI_RESET_QUADMODE   5'h1
60
`define WBQSPI_IDLE             5'h2
61
`define WBQSPI_RDIDLE           5'h3    // Idle, but in fast read mode
62
`define WBQSPI_WBDECODE         5'h4
63
`define WBQSPI_RD_DUMMY         5'h5
64
`define WBQSPI_QRD_ADDRESS      5'h6
65
`define WBQSPI_QRD_DUMMY        5'h7
66
`define WBQSPI_READ_CMD         5'h8
67
`define WBQSPI_READ_DATA        5'h9
68
`define WBQSPI_WAIT_TIL_RDIDLE  5'h10
69
`define WBQSPI_READ_ID_CMD      5'h11
70
`define WBQSPI_READ_ID          5'h12
71
`define WBQSPI_READ_STATUS      5'h13
72
`define WBQSPI_READ_CONFIG      5'h14
73
`define WBQSPI_WAIT_TIL_IDLE    5'h15
74 7 dgisselq
//
75
//
76
`ifndef READ_ONLY
77
//
78 14 dgisselq
`define WBQSPI_WAIT_WIP_CLEAR   5'h16
79
`define WBQSPI_CHECK_WIP_CLEAR  5'h17
80
`define WBQSPI_CHECK_WIP_DONE   5'h18
81
`define WBQSPI_WEN              5'h19
82
`define WBQSPI_PP               5'h20   // Program page
83
`define WBQSPI_QPP              5'h21   // Program page, 4 bit mode
84
`define WBQSPI_WR_DATA          5'h22
85
`define WBQSPI_WR_BUS_CYCLE     5'h23
86
`define WBQSPI_WRITE_STATUS     5'h24
87
`define WBQSPI_WRITE_CONFIG     5'h25
88
`define WBQSPI_ERASE_WEN        5'h26
89
`define WBQSPI_ERASE_CMD        5'h27
90
`define WBQSPI_ERASE_BLOCK      5'h28
91
`define WBQSPI_CLEAR_STATUS     5'h29
92
`define WBQSPI_IDLE_CHECK_WIP   5'h30
93 7 dgisselq
//
94
`endif
95 2 dgisselq
 
96
module  wbqspiflash(i_clk_100mhz,
97
                // Internal wishbone connections
98
                i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,
99
                i_wb_addr, i_wb_data,
100
                // Wishbone return values
101
                o_wb_ack, o_wb_stall, o_wb_data,
102
                // Quad Spi connections to the external device
103
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
104 3 dgisselq
                o_interrupt);
105 7 dgisselq
        parameter       ADDRESS_WIDTH=22;
106 14 dgisselq
        input   wire            i_clk_100mhz;
107 2 dgisselq
        // Wishbone, inputs first
108 14 dgisselq
        input   wire            i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
109
        input   wire    [(ADDRESS_WIDTH-3):0]    i_wb_addr;
110
        input   wire    [31:0]   i_wb_data;
111 2 dgisselq
        // then outputs
112
        output  reg             o_wb_ack;
113
        output  reg             o_wb_stall;
114
        output  reg     [31:0]   o_wb_data;
115
        // Quad SPI control wires
116
        output  wire            o_qspi_sck, o_qspi_cs_n;
117
        output  wire    [1:0]    o_qspi_mod;
118
        output  wire    [3:0]    o_qspi_dat;
119 14 dgisselq
        input   wire    [3:0]    i_qspi_dat;
120 2 dgisselq
        // Interrupt line
121
        output  reg             o_interrupt;
122 7 dgisselq
        // output       wire    [31:0]  o_debug;
123 2 dgisselq
 
124
        reg             spi_wr, spi_hold, spi_spd, spi_dir;
125
        reg     [31:0]   spi_in;
126
        reg     [1:0]    spi_len;
127
        wire    [31:0]   spi_out;
128
        wire            spi_valid, spi_busy;
129 4 dgisselq
        wire            w_qspi_sck, w_qspi_cs_n;
130
        wire    [3:0]    w_qspi_dat;
131
        wire    [1:0]    w_qspi_mod;
132 7 dgisselq
        // wire [22:0]  spi_dbg;
133 2 dgisselq
        llqspi  lldriver(i_clk_100mhz,
134
                        spi_wr, spi_hold, spi_in, spi_len, spi_spd, spi_dir,
135
                                spi_out, spi_valid, spi_busy,
136 4 dgisselq
                        w_qspi_sck, w_qspi_cs_n, w_qspi_mod, w_qspi_dat,
137 3 dgisselq
                                i_qspi_dat);
138 2 dgisselq
 
139
        // Erase status tracking
140
        reg             write_in_progress, write_protect;
141 7 dgisselq
        reg     [(ADDRESS_WIDTH-17):0]   erased_sector;
142 2 dgisselq
        reg             dirty_sector;
143
        initial begin
144
                write_in_progress = 1'b0;
145 7 dgisselq
                erased_sector = 0;
146 2 dgisselq
                dirty_sector  = 1'b1;
147
                write_protect = 1'b1;
148
        end
149
 
150 14 dgisselq
        wire    [23:0]   w_wb_addr;
151
        generate
152
        if (ADDRESS_WIDTH>=24)
153
                assign w_wb_addr = { i_wb_addr[21:0], 2'b00 };
154
        else
155
                assign w_wb_addr = { {(24-ADDRESS_WIDTH){1'b0}}, i_wb_addr, 2'b00 };
156
        endgenerate
157
 
158
        // Repeat for spif_addr
159
        reg     [(ADDRESS_WIDTH-3):0]    spif_addr;
160
        wire    [23:0]   w_spif_addr;
161
        generate
162
        if (ADDRESS_WIDTH>=24)
163
                assign w_spif_addr = { spif_addr[21:0], 2'b00 };
164
        else
165
                assign w_spif_addr = { {(24-ADDRESS_WIDTH){1'b0}}, spif_addr, 2'b00 };
166
        endgenerate
167
 
168 2 dgisselq
        reg     [7:0]    last_status;
169
        reg             quad_mode_enabled;
170 4 dgisselq
        reg             spif_cmd, spif_override;
171 2 dgisselq
        reg     [31:0]   spif_data;
172 14 dgisselq
        reg     [4:0]    state;
173 2 dgisselq
        reg             spif_ctrl, spif_req;
174 7 dgisselq
        wire    [(ADDRESS_WIDTH-17):0]   spif_sector;
175
        assign  spif_sector = spif_addr[(ADDRESS_WIDTH-3):14];
176 2 dgisselq
 
177 7 dgisselq
        // assign       o_debug = { spi_wr, spi_spd, spi_hold, state, spi_dbg };
178
 
179 2 dgisselq
        initial state = `WBQSPI_RESET;
180
        initial o_wb_ack   = 1'b0;
181
        initial o_wb_stall = 1'b1;
182
        initial spi_wr     = 1'b0;
183
        initial spi_len    = 2'b00;
184
        initial quad_mode_enabled = 1'b0;
185
        initial o_interrupt = 1'b0;
186
        always @(posedge i_clk_100mhz)
187 4 dgisselq
        begin
188
        spif_override <= 1'b0;
189 2 dgisselq
        if (state == `WBQSPI_RESET)
190
        begin
191
                // From a reset, we should
192
                //      Enable the Quad I/O mode
193
                //      Disable the Write protection bits in the status register
194
                //      Chip should already be up and running, so we can start
195
                //      immediately ....
196
                o_wb_ack <= 1'b0;
197
                o_wb_stall <= 1'b1;
198 4 dgisselq
                spi_wr   <= 1'b0;
199 2 dgisselq
                spi_hold <= 1'b0;
200
                spi_spd  <= 1'b0;
201
                spi_dir  <= 1'b0;
202
                last_status <= 8'h00;
203 4 dgisselq
                state <= `WBQSPI_RESET_QUADMODE;
204 2 dgisselq
                spif_req <= 1'b0;
205 4 dgisselq
                spif_override <= 1'b1;
206
                last_status <= 8'hfc; //
207
                        // This guarantees that we aren't starting in quad
208
                        // I/O mode, where the FPGA configuration scripts may
209
                        // have left us.
210
        end else if (state == `WBQSPI_RESET_QUADMODE)
211 2 dgisselq
        begin
212 4 dgisselq
                // Okay, so here's the problem: we don't know whether or not
213
                // the Xilinx loader started us up in Quad Read I/O idle mode.
214 14 dgisselq
                // So, thus we need to toggle the clock and CS_n, with fewer
215
                // clocks than are necessary to transmit a word.
216
                //
217 4 dgisselq
                // Not ready to handle the bus yet, so stall any requests
218
                o_wb_ack   <= 1'b0;
219
                o_wb_stall <= 1'b1;
220
 
221
                // Do something ...
222
                if (last_status == 8'h00)
223 2 dgisselq
                begin
224 4 dgisselq
                        spif_override <= 1'b0;
225
                        state <= `WBQSPI_IDLE;
226
                end else begin
227
                        last_status <= last_status - 8'h1;
228
                        spif_override <= 1'b1;
229
                        spif_cmd  <= last_status[3]; // Toggle CS_n
230
                        spif_ctrl <= last_status[0]; // Toggle clock too
231 2 dgisselq
                end
232
        end else if (state == `WBQSPI_IDLE)
233
        begin
234
                o_interrupt <= 1'b0;
235
                o_wb_stall <= 1'b0;
236
                o_wb_ack <= 1'b0;
237
                spif_cmd   <= i_wb_we;
238
                spif_addr  <= i_wb_addr;
239
                spif_data  <= i_wb_data;
240
                spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
241
                spif_req   <= (i_wb_ctrl_stb)||(i_wb_data_stb);
242
                spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
243
                spi_hold <= 1'b0;
244
                spi_spd  <= 1'b0;
245
                spi_dir <= 1'b0; // Write (for now, 'cause of cmd)
246
                // Data register access
247 14 dgisselq
                if (i_wb_data_stb)
248 2 dgisselq
                begin
249
 
250
                        if (i_wb_we) // Request to write a page
251
                        begin
252 7 dgisselq
`ifdef  READ_ONLY
253
                                o_wb_ack <= 1'b1;
254
                                o_wb_stall <= 1'b0;
255
                        end else
256
`else
257 2 dgisselq
                                if((~write_protect)&&(~write_in_progress))
258
                                begin // 00
259
                                        spi_wr <= 1'b1;
260
                                        spi_len <= 2'b00; // 8 bits
261
                                        // Send a write enable command
262
                                        spi_in <= { 8'h06, 24'h00 };
263
                                        state <= `WBQSPI_WEN;
264
 
265
                                        o_wb_ack <= 1'b0;
266
                                        o_wb_stall <= 1'b1;
267
                                end else if (write_protect)
268
                                begin // whether or not write-in_progress ...
269
                                        // Do nothing on a write protect
270
                                        // violation
271
                                        //
272
                                        o_wb_ack <= 1'b1;
273
                                        o_wb_stall <= 1'b0;
274
                                end else begin // write is in progress, wait
275
                                        // for it to complete
276
                                        state <= `WBQSPI_WAIT_WIP_CLEAR;
277
                                        o_wb_ack <= 1'b0;
278
                                        o_wb_stall <= 1'b1;
279
                                end
280
                        end else if (~write_in_progress)
281 7 dgisselq
`endif
282 2 dgisselq
                        begin // Read access, normal mode(s)
283
                                o_wb_ack   <= 1'b0;
284
                                o_wb_stall <= 1'b1;
285
                                spi_wr     <= 1'b1;     // Write cmd to device
286
                                if (quad_mode_enabled)
287
                                begin
288 14 dgisselq
                                        spi_in <= { 8'heb, w_wb_addr };
289 2 dgisselq
                                        state <= `WBQSPI_QRD_ADDRESS;
290
                                        spi_len    <= 2'b00; // single byte, cmd only
291
                                end else begin
292 14 dgisselq
                                        spi_in <= { 8'h0b, w_wb_addr };
293 2 dgisselq
                                        state <= `WBQSPI_RD_DUMMY;
294
                                        spi_len    <= 2'b11; // cmd+addr,32bits
295
                                end
296 7 dgisselq
`ifndef READ_ONLY
297 2 dgisselq
                        end else begin
298
                                // A write is in progress ... need to stall
299
                                // the bus until the write is complete.
300
                                state <= `WBQSPI_WAIT_WIP_CLEAR;
301
                                o_wb_ack   <= 1'b0;
302
                                o_wb_stall <= 1'b1;
303 7 dgisselq
`endif
304 2 dgisselq
                        end
305 14 dgisselq
                end else if ((i_wb_ctrl_stb)&&(i_wb_we))
306 2 dgisselq
                begin
307 7 dgisselq
`ifdef  READ_ONLY
308
                        o_wb_ack   <= 1'b1;
309
                        o_wb_stall <= 1'b0;
310
`else
311 2 dgisselq
                        o_wb_stall <= 1'b1;
312
                        case(i_wb_addr[1:0])
313
                        2'b00: begin // Erase command register
314
                                write_protect <= ~i_wb_data[28];
315
                                o_wb_stall <= 1'b0;
316
 
317
                                if((i_wb_data[31])&&(~write_in_progress))
318
                                begin
319
                                        // Command an erase--ack it immediately
320
 
321
                                        o_wb_ack <= 1'b1;
322
                                        o_wb_stall <= 1'b0;
323
 
324
                                        if ((i_wb_data[31])&&(~write_protect))
325
                                        begin
326
                                                spi_wr <= 1'b1;
327
                                                spi_len <= 2'b00;
328
                                                // Send a write enable command
329
                                                spi_in <= { 8'h06, 24'h00 };
330
                                                state <= `WBQSPI_ERASE_CMD;
331
                                                o_wb_stall <= 1'b1;
332
                                        end
333
                                end else if (i_wb_data[31])
334
                                begin
335
                                        state <= `WBQSPI_WAIT_WIP_CLEAR;
336
                                        o_wb_ack   <= 1'b1;
337
                                        o_wb_stall <= 1'b1;
338
                                end else
339
                                        o_wb_ack   <= 1'b1;
340
                                        o_wb_stall <= 1'b0;
341
                                end
342
                        2'b01: begin
343
                                // Write the configuration register
344
                                o_wb_ack <= 1'b1;
345
                                o_wb_stall <= 1'b1;
346
 
347
                                // Need to send a write enable command first
348
                                spi_wr <= 1'b1;
349
                                spi_len <= 2'b00; // 8 bits
350
                                // Send a write enable command
351
                                spi_in <= { 8'h06, 24'h00 };
352
                                state <= `WBQSPI_WRITE_CONFIG;
353
                                end
354
                        2'b10: begin
355
                                // Write the status register
356
                                o_wb_ack <= 1'b1; // Ack immediately
357
                                o_wb_stall <= 1'b1; // Stall other cmds
358
                                // Need to send a write enable command first
359
                                spi_wr <= 1'b1;
360
                                spi_len <= 2'b00; // 8 bits
361
                                // Send a write enable command
362
                                spi_in <= { 8'h06, 24'h00 };
363
                                state <= `WBQSPI_WRITE_STATUS;
364
                                end
365
                        2'b11: begin // Write the ID register??? makes no sense
366
                                o_wb_ack <= 1'b1;
367
                                o_wb_stall <= 1'b0;
368
                                end
369
                        endcase
370 7 dgisselq
`endif
371 14 dgisselq
                end else if (i_wb_ctrl_stb) // &&(~i_wb_we))
372 2 dgisselq
                begin
373
                        case(i_wb_addr[1:0])
374
                        2'b00: begin // Read local register
375
                                if (write_in_progress) // Read status
376
                                begin// register, is write still in progress?
377
                                        state <= `WBQSPI_READ_STATUS;
378
                                        spi_wr <= 1'b1;
379
                                        spi_len <= 2'b01;// 8 bits out, 8 bits in
380
                                        spi_in <= { 8'h05, 24'h00};
381
 
382
                                        o_wb_ack <= 1'b0;
383
                                        o_wb_stall <= 1'b1;
384
                                end else begin // Return w/o talking to device
385
                                        o_wb_ack <= 1'b1;
386
                                        o_wb_stall <= 1'b0;
387
                                        o_wb_data <= { write_in_progress,
388
                                                dirty_sector, spi_busy,
389
                                                ~write_protect,
390
                                                quad_mode_enabled,
391 7 dgisselq
                                                {(29-ADDRESS_WIDTH){1'b0}},
392 2 dgisselq
                                                erased_sector, 14'h000 };
393
                                end end
394
                        2'b01: begin // Read configuration register
395
                                state <= `WBQSPI_READ_CONFIG;
396
                                spi_wr <= 1'b1;
397
                                spi_len <= 2'b01;
398
                                spi_in <= { 8'h35, 24'h00};
399
 
400
                                o_wb_ack <= 1'b0;
401
                                o_wb_stall <= 1'b1;
402
                                end
403
                        2'b10: begin // Read status register
404
                                state <= `WBQSPI_READ_STATUS;
405
                                spi_wr <= 1'b1;
406
                                spi_len <= 2'b01; // 8 bits out, 8 bits in
407
                                spi_in <= { 8'h05, 24'h00};
408
 
409
                                o_wb_ack <= 1'b0;
410
                                o_wb_stall <= 1'b1;
411
                                end
412
                        2'b11: begin // Read ID register
413
                                state <= `WBQSPI_READ_ID_CMD;
414
                                spi_wr <= 1'b1;
415
                                spi_len <= 2'b00;
416
                                spi_in <= { 8'h9f, 24'h00};
417
 
418
                                o_wb_ack <= 1'b0;
419
                                o_wb_stall <= 1'b1;
420
                                end
421
                        endcase
422 7 dgisselq
`ifndef READ_ONLY
423 2 dgisselq
                end else if ((~i_wb_cyc)&&(write_in_progress))
424
                begin
425
                        state <= `WBQSPI_IDLE_CHECK_WIP;
426
                        spi_wr <= 1'b1;
427
                        spi_len <= 2'b01; // 8 bits out, 8 bits in
428
                        spi_in <= { 8'h05, 24'h00};
429
 
430
                        o_wb_ack <= 1'b0;
431
                        o_wb_stall <= 1'b1;
432 7 dgisselq
`endif
433 2 dgisselq
                end
434
        end else if (state == `WBQSPI_RDIDLE)
435
        begin
436
                spi_wr <= 1'b0;
437
                o_wb_stall <= 1'b0;
438
                o_wb_ack <= 1'b0;
439
                spif_cmd   <= i_wb_we;
440
                spif_addr  <= i_wb_addr;
441
                spif_data  <= i_wb_data;
442
                spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
443
                spif_req   <= (i_wb_ctrl_stb)||(i_wb_data_stb);
444
                spi_hold <= 1'b0;
445
                spi_spd<= 1'b1;
446
                spi_dir <= 1'b0; // Write (for now)
447 14 dgisselq
                if ((i_wb_data_stb)&&(~i_wb_we))
448 2 dgisselq
                begin // Continue our read ... send the new address / mode
449
                        o_wb_stall <= 1'b1;
450
                        spi_wr <= 1'b1;
451 4 dgisselq
                        spi_len <= 2'b10; // Write address, but not mode byte
452 14 dgisselq
                        spi_in <= { w_wb_addr, 8'ha0 };
453 2 dgisselq
                        state <= `WBQSPI_QRD_DUMMY;
454 14 dgisselq
                end else if((i_wb_ctrl_stb)&&(~i_wb_we)&&(i_wb_addr[1:0] == 2'b00))
455 2 dgisselq
                begin
456
                        // A local read that doesn't touch the device, so leave
457
                        // the device in its current state
458
                        o_wb_stall <= 1'b0;
459
                        o_wb_ack <= 1'b1;
460
                        o_wb_data <= { write_in_progress,
461
                                        dirty_sector, spi_busy,
462
                                        ~write_protect,
463
                                        quad_mode_enabled,
464 7 dgisselq
                                        {(29-ADDRESS_WIDTH){1'b0}},
465 2 dgisselq
                                        erased_sector, 14'h000 };
466 14 dgisselq
                end else if(((i_wb_ctrl_stb)||(i_wb_data_stb)))
467 2 dgisselq
                begin // Need to release the device from quad mode for all else
468
                        o_wb_ack   <= 1'b0;
469
                        o_wb_stall <= 1'b1;
470
                        spi_wr <= 1'b1;
471
                        spi_len <= 2'b11;
472
                        spi_in <= 32'h00;
473
                        state <= `WBQSPI_WBDECODE;
474
                end
475
        end else if (state == `WBQSPI_WBDECODE)
476
        begin
477
                // We were in quad SPI read mode, and had to get out.
478
                // Now we've got a command (not data read) to read and
479
                // execute.  Accomplish what we would've done while in the
480
                // IDLE state here, save only that we don't have to worry
481
                // about data reads, and we need to operate on a stored
482
                // version of the bus command
483
                o_wb_stall <= 1'b1;
484
                o_wb_ack <= 1'b0;
485
                spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
486
                spi_hold <= 1'b0;
487
                spi_spd <= 1'b0;
488
                spi_dir <= 1'b0;
489
                spif_req<= (spif_req) && (i_wb_cyc);
490
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // only in full idle ...
491
                begin
492
                        // Data register access
493
                        if (~spif_ctrl)
494
                        begin
495
                                if (spif_cmd) // Request to write a page
496
                                begin
497 7 dgisselq
`ifdef  READ_ONLY
498
                                        o_wb_ack <= spif_req;
499
                                        o_wb_stall <= 1'b0;
500
                                        state <= `WBQSPI_IDLE;
501
`else
502 2 dgisselq
                                        if((~write_protect)&&(~write_in_progress))
503
                                        begin // 00
504
                                                spi_wr <= 1'b1;
505
                                                spi_len <= 2'b00; // 8 bits
506
                                                // Send a write enable command
507
                                                spi_in <= { 8'h06, 24'h00 };
508
                                                state <= `WBQSPI_WEN;
509
 
510
                                                o_wb_ack <= 1'b0;
511
                                                o_wb_stall <= 1'b1;
512
                                        end else if (write_protect)
513
                                        begin // whether or not write-in_progress ...
514
                                                // Do nothing on a write protect
515
                                                // violation
516
                                                //
517
                                                o_wb_ack <= spif_req;
518
                                                o_wb_stall <= 1'b0;
519
                                                state <= `WBQSPI_IDLE;
520
                                        end else begin // write is in progress, wait
521
                                                // for it to complete
522
                                                state <= `WBQSPI_WAIT_WIP_CLEAR;
523
                                                o_wb_ack <= 1'b0;
524
                                                o_wb_stall <= 1'b1;
525
                                        end
526
                                // end else if (~write_in_progress) // always true
527
                                // but ... we wouldn't get here on a normal read access
528 7 dgisselq
`endif
529 2 dgisselq
                                end else begin
530 7 dgisselq
                                        // Something's wrong, we should never
531
                                        //   get here
532 2 dgisselq
                                        // Attempt to go to idle to recover
533
                                        state <= `WBQSPI_IDLE;
534
                                end
535
                        end else if ((spif_ctrl)&&(spif_cmd))
536
                        begin
537 7 dgisselq
`ifdef  READ_ONLY
538
                                o_wb_ack   <= spif_req;
539
                                o_wb_stall <= 1'b0;
540
                                state <= `WBQSPI_IDLE;
541
`else
542 2 dgisselq
                                o_wb_stall <= 1'b1;
543
                                case(spif_addr[1:0])
544
                                2'b00: begin // Erase command register
545
                                        o_wb_ack   <= spif_req;
546
                                        o_wb_stall <= 1'b0;
547
                                        state <= `WBQSPI_IDLE;
548
                                        write_protect <= ~spif_data[28];
549
                                        // Are we commanding an erase?
550
                                        // We're in read mode, writes cannot
551
                                        // be in progress, so ...
552
                                        if (spif_data[31]) // Command an erase
553
                                        begin
554
                                                // Since we're not going back
555
                                                // to IDLE, we must stall the
556
                                                // bus here
557
                                                o_wb_stall <= 1'b1;
558
                                                spi_wr <= 1'b1;
559
                                                spi_len <= 2'b00;
560
                                                // Send a write enable command
561
                                                spi_in <= { 8'h06, 24'h00 };
562
                                                state <= `WBQSPI_ERASE_CMD;
563
                                        end end
564
                                2'b01: begin
565
                                        // Write the configuration register
566
                                        o_wb_ack <= spif_req;
567
                                        o_wb_stall <= 1'b1;
568
 
569
                                        // Need to send a write enable command first
570
                                        spi_wr <= 1'b1;
571
                                        spi_len <= 2'b00; // 8 bits
572
                                        // Send a write enable command
573
                                        spi_in <= { 8'h06, 24'h00 };
574
                                        state <= `WBQSPI_WRITE_CONFIG;
575
                                        end
576
                                2'b10: begin
577
                                        // Write the status register
578
                                        o_wb_ack <= spif_req; // Ack immediately
579
                                        o_wb_stall <= 1'b1; // Stall other cmds
580
                                        // Need to send a write enable command first
581
                                        spi_wr <= 1'b1;
582
                                        spi_len <= 2'b00; // 8 bits
583
                                        // Send a write enable command
584
                                        spi_in <= { 8'h06, 24'h00 };
585
                                        state <= `WBQSPI_WRITE_STATUS;
586
                                        end
587
                                2'b11: begin // Write the ID register??? makes no sense
588
                                        o_wb_ack <= spif_req;
589
                                        o_wb_stall <= 1'b0;
590
                                        state <= `WBQSPI_IDLE;
591
                                        end
592
                                endcase
593 7 dgisselq
`endif
594 2 dgisselq
                        end else begin // on (~spif_we)
595
                                case(spif_addr[1:0])
596
                                2'b00: begin // Read local register
597
                                        // Nonsense case--would've done this
598
                                        // already
599
                                        state <= `WBQSPI_IDLE;
600
                                        o_wb_ack <= spif_req;
601
                                        o_wb_stall <= 1'b0;
602
                                        end
603
                                2'b01: begin // Read configuration register
604
                                        state <= `WBQSPI_READ_CONFIG;
605
                                        spi_wr <= 1'b1;
606
                                        spi_len <= 2'b01;
607
                                        spi_in <= { 8'h35, 24'h00};
608
 
609
                                        o_wb_ack <= 1'b0;
610
                                        o_wb_stall <= 1'b1;
611
                                        end
612
                                2'b10: begin // Read status register
613
                                        state <= `WBQSPI_READ_STATUS;
614
                                        spi_wr <= 1'b1;
615
                                        spi_len <= 2'b01; // 8 bits out, 8 bits in
616
                                        spi_in <= { 8'h05, 24'h00};
617
 
618
                                        o_wb_ack <= 1'b0;
619
                                        o_wb_stall <= 1'b1;
620
                                        end
621
                                2'b11: begin // Read ID register
622
                                        state <= `WBQSPI_READ_ID_CMD;
623
                                        spi_wr <= 1'b1;
624
                                        spi_len <= 2'b00;
625
                                        spi_in <= { 8'h9f, 24'h00};
626
 
627
                                        o_wb_ack <= 1'b0;
628
                                        o_wb_stall <= 1'b1;
629
                                        end
630
                                endcase
631
                        end
632
                end
633 7 dgisselq
//
634
//
635
//      READ DATA section: for both data and commands
636
//
637 2 dgisselq
        end else if (state == `WBQSPI_RD_DUMMY)
638
        begin
639
                o_wb_ack   <= 1'b0;
640
                o_wb_stall <= 1'b1;
641
 
642
                spi_wr <= 1'b1; // Non-stop
643
                // Need to read one byte of dummy data,
644
                // just to consume 8 clocks
645
                spi_in <= { 8'h00, 24'h00 };
646
                spi_len <= 2'b00; // Read 8 bits
647
                spi_spd <= 1'b0;
648
                spi_hold <= 1'b0;
649
                spif_req<= (spif_req) && (i_wb_cyc);
650
 
651
                if ((~spi_busy)&&(~o_qspi_cs_n))
652
                        // Our command was accepted
653
                        state <= `WBQSPI_READ_CMD;
654
        end else if (state == `WBQSPI_QRD_ADDRESS)
655
        begin
656
                // We come in here immediately upon issuing a QRD read
657
                // command (8-bits), but we have to pause to give the
658
                // address (24-bits) and mode (8-bits) in quad speed.
659
                o_wb_ack   <= 1'b0;
660
                o_wb_stall <= 1'b1;
661
 
662
                spi_wr <= 1'b1; // Non-stop
663 14 dgisselq
                spi_in <= { w_spif_addr, 8'ha0 };
664 4 dgisselq
                spi_len <= 2'b10; // Write address, not mode byte
665 2 dgisselq
                spi_spd <= 1'b1;
666
                spi_dir <= 1'b0; // Still writing
667
                spi_hold <= 1'b0;
668
                spif_req<= (spif_req) && (i_wb_cyc);
669
 
670
                if ((~spi_busy)&&(spi_spd))
671
                        // Our command was accepted
672
                        state <= `WBQSPI_QRD_DUMMY;
673
        end else if (state == `WBQSPI_QRD_DUMMY)
674
        begin
675
                o_wb_ack   <= 1'b0;
676
                o_wb_stall <= 1'b1;
677
 
678
                spi_wr <= 1'b1; // Non-stop
679
                spi_in <= { 8'ha0, 24'h00 }; // Mode byte, then 2 bytes dummy
680 9 dgisselq
                spi_len <= 2'b10; // Write 24 bits
681 2 dgisselq
                spi_spd <= 1'b1;
682
                spi_dir <= 1'b0; // Still writing
683
                spi_hold <= 1'b0;
684
                spif_req<= (spif_req) && (i_wb_cyc);
685
 
686
                if ((~spi_busy)&&(spi_in[31:28] == 4'ha))
687
                        // Our command was accepted
688
                        state <= `WBQSPI_READ_CMD;
689
        end else if (state == `WBQSPI_READ_CMD)
690
        begin // Issue our first command to read 32 bits.
691
                o_wb_ack   <= 1'b0;
692
                o_wb_stall <= 1'b1;
693
 
694
                spi_wr <= 1'b1;
695
                spi_in <= { 8'hff, 24'h00 }; // Empty
696
                spi_len <= 2'b11; // Read 32 bits
697
                spi_dir <= 1'b1; // Now reading
698
                spi_hold <= 1'b0;
699
                spif_req<= (spif_req) && (i_wb_cyc);
700
                if ((spi_valid)&&(spi_len == 2'b11))
701
                        state <= `WBQSPI_READ_DATA;
702
        end else if (state == `WBQSPI_READ_DATA)
703
        begin
704
                // Pipelined read support
705 14 dgisselq
                spi_wr <=((i_wb_data_stb)&&(~i_wb_we)&&(i_wb_addr== (spif_addr+1)));
706 2 dgisselq
                spi_in <= 32'h00;
707
                spi_len <= 2'b11;
708
                // Don't adjust the speed here, it was set in the setup
709 4 dgisselq
                spi_dir <= 1'b1;        // Now we get to read
710
                // Don't let the device go to idle until the bus cycle ends.
711
                //      This actually prevents a *really* nasty race condition,
712
                //      where the strobe comes in after the lower level device
713
                //      has decided to stop waiting.  The write is then issued,
714
                //      but no one is listening.  By leaving the device open,
715
                //      the device is kept in a state where a valid strobe
716
                //      here will be useful.  Of course, we don't accept
717
                //      all commands, just reads.  Further, the strobe needs
718
                //      to be high for two clocks cycles without changing
719
                //      anything on the bus--one for us to notice it and pull
720
                //      our head out of the sand, and a second for whoever
721
                //      owns the bus to realize their command went through.
722
                spi_hold <= 1'b1;
723 2 dgisselq
                spif_req<= (spif_req) && (i_wb_cyc);
724
                if ((spi_valid)&&(~spi_in[31]))
725
                begin // Single pulse acknowledge and write data out
726
                        o_wb_ack <= spif_req;
727
                        o_wb_stall <= (~spi_wr);
728
                        // adjust endian-ness to match the PC
729 14 dgisselq
                        o_wb_data <= spi_out;
730 2 dgisselq
                        state <= (spi_wr)?`WBQSPI_READ_DATA
731
                                : ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
732
                        spif_req <= spi_wr;
733 4 dgisselq
                        spi_hold <= (~spi_wr);
734 2 dgisselq
                        if (spi_wr)
735
                                spif_addr <= i_wb_addr;
736 4 dgisselq
                end else if (~i_wb_cyc)
737
                begin // FAIL SAFE: If the bus cycle ends, forget why we're
738
                        // here, just go back to idle
739
                        state <= ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
740
                        spi_hold <= 1'b0;
741
                        o_wb_ack <= 1'b0;
742
                        o_wb_stall <= 1'b1;
743 2 dgisselq
                end else begin
744
                        o_wb_ack <= 1'b0;
745
                        o_wb_stall <= 1'b1;
746
                end
747
        end else if (state == `WBQSPI_WAIT_TIL_RDIDLE)
748
        begin // Wait 'til idle, but then go to fast read idle instead of full
749
                spi_wr     <= 1'b0;     // idle
750
                spi_hold   <= 1'b0;
751
                o_wb_stall <= 1'b1;
752
                o_wb_ack   <= 1'b0;
753
                spif_req   <= 1'b0;
754
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
755
                begin // clearing of the SPI port before moving on
756
                        state <= `WBQSPI_RDIDLE;
757
                        o_wb_stall <= 1'b0;
758
                        o_wb_ack   <= 1'b0;// Shouldn't be acking anything here
759
                end
760
        end else if (state == `WBQSPI_READ_ID_CMD)
761
        begin // We came into here immediately after issuing a 0x9f command
762
                // Now we need to read 32 bits of data.  Result should be
763
                // 0x0102154d (8'h manufacture ID, 16'h device ID, followed
764
                // by the number of extended bytes available 8'h4d).
765
                o_wb_ack <= 1'b0;
766
                o_wb_stall<= 1'b1;
767
 
768
                spi_wr <= 1'b1; // No data to send, but need four bytes, since
769
                spi_len <= 2'b11; // 32 bits of data are ... useful
770
                spi_in <= 32'h00; // Irrelevant
771
                spi_spd <= 1'b0; // Slow speed
772
                spi_dir <= 1'b1; // Reading
773
                spi_hold <= 1'b0;
774
                spif_req <= (spif_req) && (i_wb_cyc);
775
                if ((~spi_busy)&&(~o_qspi_cs_n)&&(spi_len == 2'b11))
776
                        // Our command was accepted, now go read the result
777
                        state <= `WBQSPI_READ_ID;
778
        end else if (state == `WBQSPI_READ_ID)
779
        begin
780
                o_wb_ack <= 1'b0; // Assuming we're still waiting
781
                o_wb_stall <= 1'b1;
782
 
783 4 dgisselq
                spi_wr <= 1'b0; // No more writes, we've already written the cmd
784 2 dgisselq
                spi_hold <= 1'b0;
785
                spif_req <= (spif_req) && (i_wb_cyc);
786
 
787
                // Here, we just wait until the result comes back
788
                // The problem is, the result may be the previous result.
789
                // So we use spi_len as an indicator
790
                spi_len <= 2'b00;
791
                if((spi_valid)&&(spi_len==2'b00))
792
                begin // Put the results out as soon as possible
793
                        o_wb_data <= spi_out[31:0];
794
                        o_wb_ack <= spif_req;
795
                        spif_req <= 1'b0;
796 4 dgisselq
                end else if ((~spi_busy)&&(o_qspi_cs_n))
797 2 dgisselq
                begin
798
                        state <= `WBQSPI_IDLE;
799
                        o_wb_stall <= 1'b0;
800
                end
801
        end else if (state == `WBQSPI_READ_STATUS)
802
        begin // We enter after the command has been given, for now just
803
                // read and return
804
                spi_wr <= 1'b0;
805
                o_wb_ack <= 1'b0;
806
                spi_hold <= 1'b0;
807
                spif_req <= (spif_req) && (i_wb_cyc);
808
                if (spi_valid)
809
                begin
810
                        o_wb_ack <= spif_req;
811
                        o_wb_stall <= 1'b1;
812
                        spif_req <= 1'b0;
813
                        last_status <= spi_out[7:0];
814
                        write_in_progress <= spi_out[0];
815
                        if (spif_addr[1:0] == 2'b00) // Local read, checking
816
                        begin // status, 'cause we're writing
817
                                o_wb_data <= { spi_out[0],
818
                                        dirty_sector, spi_busy,
819
                                        ~write_protect,
820
                                        quad_mode_enabled,
821 7 dgisselq
                                        {(29-ADDRESS_WIDTH){1'b0}},
822 2 dgisselq
                                        erased_sector, 14'h000 };
823
                        end else begin
824
                                o_wb_data <= { 24'h00, spi_out[7:0] };
825
                        end
826
                end
827
 
828
                if ((~spi_busy)&&(~spi_wr))
829
                        state <= `WBQSPI_IDLE;
830
        end else if (state == `WBQSPI_READ_CONFIG)
831
        begin // We enter after the command has been given, for now just
832
                // read and return
833
                spi_wr <= 1'b0;
834
                o_wb_ack <= 1'b0;
835
                o_wb_stall <= 1'b1;
836
                spi_hold <= 1'b0;
837
                spif_req <= (spif_req) && (i_wb_cyc);
838
 
839
                if (spi_valid)
840
                begin
841
                        o_wb_data <= { 24'h00, spi_out[7:0] };
842
                        quad_mode_enabled <= spi_out[1];
843
                end
844
 
845
                if ((~spi_busy)&&(~spi_wr))
846
                begin
847
                        state <= `WBQSPI_IDLE;
848
                        o_wb_ack   <= spif_req;
849
                        o_wb_stall <= 1'b0;
850
                        spif_req <= 1'b0;
851
                end
852 7 dgisselq
 
853
//
854
//
855
//      Write/erase data section
856
//
857
`ifndef READ_ONLY
858
        end else if (state == `WBQSPI_WAIT_WIP_CLEAR)
859
        begin
860
                o_wb_stall <= 1'b1;
861
                o_wb_ack   <= 1'b0;
862
                spi_wr <= 1'b0;
863
                spif_req<= (spif_req) && (i_wb_cyc);
864
                if (~spi_busy)
865
                begin
866
                        spi_wr   <= 1'b1;
867
                        spi_in   <= { 8'h05, 24'h0000 };
868
                        spi_hold <= 1'b1;
869
                        spi_len  <= 2'b01; // 16 bits write, so we can read 8
870
                        state <= `WBQSPI_CHECK_WIP_CLEAR;
871
                        spi_spd  <= 1'b0; // Slow speed
872
                        spi_dir  <= 1'b0;
873
                end
874
        end else if (state == `WBQSPI_CHECK_WIP_CLEAR)
875
        begin
876
                o_wb_stall <= 1'b1;
877
                o_wb_ack   <= 1'b0;
878
                // Repeat as often as necessary until we are clear
879
                spi_wr <= 1'b1;
880
                spi_in <= 32'h0000; // Values here are actually irrelevant
881
                spi_hold <= 1'b1;
882
                spi_len <= 2'b00; // One byte at a time
883
                spi_spd  <= 1'b0; // Slow speed
884
                spi_dir  <= 1'b0;
885
                spif_req<= (spif_req) && (i_wb_cyc);
886
                if ((spi_valid)&&(~spi_out[0]))
887
                begin
888
                        state <= `WBQSPI_CHECK_WIP_DONE;
889
                        spi_wr   <= 1'b0;
890
                        spi_hold <= 1'b0;
891
                        write_in_progress <= 1'b0;
892
                        last_status <= spi_out[7:0];
893
                end
894
        end else if (state == `WBQSPI_CHECK_WIP_DONE)
895
        begin
896
                o_wb_stall <= 1'b1;
897
                o_wb_ack   <= 1'b0;
898
                // Let's let the SPI port come back to a full idle,
899
                // and the chip select line go low before continuing
900
                spi_wr   <= 1'b0;
901
                spi_len  <= 2'b00;
902
                spi_hold <= 1'b0;
903
                spi_spd  <= 1'b0; // Slow speed
904
                spi_dir  <= 1'b0;
905
                spif_req<= (spif_req) && (i_wb_cyc);
906
                if ((o_qspi_cs_n)&&(~spi_busy)) // Chip select line is high, we can continue
907
                begin
908
                        spi_wr   <= 1'b0;
909
                        spi_hold <= 1'b0;
910
 
911
                        casez({ spif_cmd, spif_ctrl, spif_addr[1:0] })
912
                        4'b00??: begin // Read data from ... somewhere
913
                                spi_wr     <= 1'b1;     // Write cmd to device
914
                                if (quad_mode_enabled)
915
                                begin
916 14 dgisselq
                                        spi_in <= { 8'heb, w_spif_addr };
917 7 dgisselq
                                        state <= `WBQSPI_QRD_ADDRESS;
918
                                        // spi_len    <= 2'b00; // single byte, cmd only
919
                                end else begin
920 14 dgisselq
                                        spi_in <= { 8'h0b, w_spif_addr };
921 7 dgisselq
                                        state <= `WBQSPI_RD_DUMMY;
922
                                        spi_len    <= 2'b11; // Send cmd and addr
923
                                end end
924
                        4'b10??: begin // Write data to ... anywhere
925
                                spi_wr <= 1'b1;
926
                                spi_len <= 2'b00; // 8 bits
927
                                // Send a write enable command
928
                                spi_in <= { 8'h06, 24'h00 };
929
                                state <= `WBQSPI_WEN;
930
                                end
931
                        4'b0110: begin // Read status register
932
                                state <= `WBQSPI_READ_STATUS;
933
                                spi_wr <= 1'b1;
934
                                spi_len <= 2'b01; // 8 bits out, 8 bits in
935
                                spi_in <= { 8'h05, 24'h00};
936
                                end
937
                        4'b0111: begin
938
                                state <= `WBQSPI_READ_ID_CMD;
939
                                spi_wr <= 1'b1;
940
                                spi_len <= 2'b00;
941
                                spi_in <= { 8'h9f, 24'h00};
942
                                end
943
                        default: begin //
944
                                o_wb_stall <= 1'b1;
945
                                o_wb_ack <= spif_req;
946
                                state <= `WBQSPI_WAIT_TIL_IDLE;
947
                                end
948
                        endcase
949
                // spif_cmd   <= i_wb_we;
950
                // spif_addr  <= i_wb_addr;
951
                // spif_data  <= i_wb_data;
952
                // spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
953
                // spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
954
                end
955
        end else if (state == `WBQSPI_WEN)
956
        begin // We came here after issuing a write enable command
957
                spi_wr <= 1'b0;
958
                o_wb_ack <= 1'b0;
959
                o_wb_stall <= 1'b1;
960
                spif_req<= (spif_req) && (i_wb_cyc);
961
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Let's come to a full stop
962
                        state <= (quad_mode_enabled)?`WBQSPI_QPP:`WBQSPI_PP;
963
                        // state <= `WBQSPI_PP;
964
        end else if (state == `WBQSPI_PP)
965
        begin // We come here under a full stop / full port idle mode
966
                // Issue our command immediately
967
                spi_wr <= 1'b1;
968 14 dgisselq
                spi_in <= { 8'h02, w_spif_addr };
969 7 dgisselq
                spi_len <= 2'b11;
970
                spi_hold <= 1'b1;
971
                spi_spd  <= 1'b0;
972
                spi_dir  <= 1'b0; // Writing
973
                spif_req<= (spif_req) && (i_wb_cyc);
974
 
975
                // Once we get busy, move on
976
                if (spi_busy)
977
                        state <= `WBQSPI_WR_DATA;
978
                if (spif_sector == erased_sector)
979
                        dirty_sector <= 1'b1;
980
        end else if (state == `WBQSPI_QPP)
981
        begin // We come here under a full stop / full port idle mode
982
                // Issue our command immediately
983
                spi_wr <= 1'b1;
984 14 dgisselq
                spi_in <= { 8'h32, w_spif_addr };
985 7 dgisselq
                spi_len <= 2'b11;
986
                spi_hold <= 1'b1;
987
                spi_spd  <= 1'b0;
988
                spi_dir  <= 1'b0; // Writing
989
                spif_req<= (spif_req) && (i_wb_cyc);
990
 
991
                // Once we get busy, move on
992
                if (spi_busy)
993
                begin
994
                        // spi_wr is irrelevant here ...
995
                        // Set the speed value once, but wait til we get busy
996
                        // to do so.
997
                        spi_spd <= 1'b1;
998
                        state <= `WBQSPI_WR_DATA;
999
                end
1000
                if (spif_sector == erased_sector)
1001
                        dirty_sector <= 1'b1;
1002
        end else if (state == `WBQSPI_WR_DATA)
1003
        begin
1004
                o_wb_stall <= 1'b1;
1005
                o_wb_ack   <= 1'b0;
1006
                spi_wr   <= 1'b1; // write without waiting
1007 14 dgisselq
                spi_in   <= spif_data;
1008 7 dgisselq
                spi_len  <= 2'b11; // Write 4 bytes
1009
                spi_hold <= 1'b1;
1010
                if (~spi_busy)
1011
                begin
1012
                        o_wb_ack <= spif_req; // Ack when command given
1013
                        state <= `WBQSPI_WR_BUS_CYCLE;
1014
                end
1015
                spif_req<= (spif_req) && (i_wb_cyc);
1016
        end else if (state == `WBQSPI_WR_BUS_CYCLE)
1017
        begin
1018
                o_wb_ack <= 1'b0; // Turn off our ack and stall flags
1019
                o_wb_stall <= 1'b1;
1020
                spi_wr <= 1'b0;
1021
                spi_hold <= 1'b1;
1022
                write_in_progress <= 1'b1;
1023
                spif_req<= (spif_req) && (i_wb_cyc);
1024
                if (~i_wb_cyc)
1025
                begin
1026
                        state <= `WBQSPI_WAIT_TIL_IDLE;
1027
                        spi_hold <= 1'b0;
1028
                end else if (spi_wr)
1029
                begin // Give the SPI a chance to get busy on the last write
1030
                        // Do nothing here.
1031
                end else if ((i_wb_data_stb)&&(i_wb_we)
1032
                                &&(i_wb_addr == (spif_addr+1))
1033
                                &&(i_wb_addr[(ADDRESS_WIDTH-3):6]==spif_addr[(ADDRESS_WIDTH-3):6]))
1034
                begin
1035
                        spif_cmd  <= 1'b1;
1036
                        spif_data <= i_wb_data;
1037
                        spif_addr <= i_wb_addr;
1038
                        spif_ctrl  <= 1'b0;
1039
                        spif_req<= 1'b1;
1040
                        // We'll keep the bus stalled on this request
1041
                        // for a while
1042
                        state <= `WBQSPI_WR_DATA;
1043
                        o_wb_ack   <= 1'b0;
1044
                        o_wb_stall <= 1'b0;
1045
                end else if ((i_wb_data_stb|i_wb_ctrl_stb)&&(~o_wb_ack)) // Writing out of bounds
1046
                begin
1047
                        spi_hold <= 1'b0;
1048
                        spi_wr   <= 1'b0;
1049
                        state <= `WBQSPI_WAIT_TIL_IDLE;
1050
                end // Otherwise we stay here
1051 2 dgisselq
        end else if (state == `WBQSPI_WRITE_CONFIG)
1052
        begin // We enter immediately after commanding a WEN
1053
                o_wb_ack   <= 1'b0;
1054
                o_wb_stall <= 1'b1;
1055
 
1056
                spi_len <= 2'b10;
1057
                spi_in <= { 8'h01, last_status, spif_data[7:0], 8'h00 };
1058
                spi_wr <= 1'b0;
1059
                spi_hold <= 1'b0;
1060
                spif_req <= (spif_req) && (i_wb_cyc);
1061
                if ((~spi_busy)&&(~spi_wr))
1062
                begin
1063
                        spi_wr <= 1'b1;
1064
                        state <= `WBQSPI_WAIT_TIL_IDLE;
1065
                        write_in_progress <= 1'b1;
1066
                        quad_mode_enabled <= spif_data[1];
1067
                end
1068
        end else if (state == `WBQSPI_WRITE_STATUS)
1069
        begin // We enter immediately after commanding a WEN
1070
                o_wb_ack   <= 1'b0;
1071
                o_wb_stall <= 1'b1;
1072
 
1073
                spi_len <= 2'b01;
1074
                spi_in <= { 8'h01, spif_data[7:0], 16'h00 };
1075
                // last_status <= i_wb_data[7:0]; // We'll read this in a moment
1076
                spi_wr <= 1'b0;
1077
                spi_hold <= 1'b0;
1078
                spif_req <= (spif_req) && (i_wb_cyc);
1079
                if ((~spi_busy)&&(~spi_wr))
1080
                begin
1081
                        spi_wr <= 1'b1;
1082
                        last_status <= spif_data[7:0];
1083
                        write_in_progress <= 1'b1;
1084
                        if(((last_status[6])||(last_status[5]))
1085
                                &&((~spif_data[6])&&(~spif_data[5])))
1086
                                state <= `WBQSPI_CLEAR_STATUS;
1087
                        else
1088
                                state <= `WBQSPI_WAIT_TIL_IDLE;
1089
                end
1090
        end else if (state == `WBQSPI_ERASE_CMD)
1091
        begin // Know that WIP is clear on entry, WEN has just been commanded
1092
                spi_wr     <= 1'b0;
1093
                o_wb_ack   <= 1'b0;
1094
                o_wb_stall <= 1'b1;
1095
                spi_hold   <= 1'b0;
1096
                spi_spd <= 1'b0;
1097
                spi_dir <= 1'b0;
1098
                spif_req <= (spif_req) && (i_wb_cyc);
1099
 
1100
                // Here's the erase command
1101
                spi_in <= { 8'hd8, 2'h0, spif_data[19:14], 14'h000, 2'b00 };
1102
                spi_len <= 2'b11; // 32 bit write
1103
                // together with setting our copy of the WIP bit
1104
                write_in_progress <= 1'b1;
1105
                // keeping track of which sector we just erased
1106 7 dgisselq
                erased_sector <= spif_data[(ADDRESS_WIDTH-3):14];
1107 2 dgisselq
                // and marking this erase sector as no longer dirty
1108
                dirty_sector <= 1'b0;
1109
 
1110
                // Wait for a full stop before issuing this command
1111
                if ((~spi_busy)&&(~spi_wr)&&(o_qspi_cs_n))
1112
                begin // When our command is accepted, move to the next state
1113
                        spi_wr <= 1'b1;
1114
                        state <= `WBQSPI_ERASE_BLOCK;
1115
                end
1116
        end else if (state == `WBQSPI_ERASE_BLOCK)
1117
        begin
1118
                spi_wr     <= 1'b0;
1119
                spi_hold   <= 1'b0;
1120
                o_wb_stall <= 1'b1;
1121
                o_wb_ack   <= 1'b0;
1122
                spif_req <= (spif_req) && (i_wb_cyc);
1123
                // When the port clears, we can head back to idle
1124
                if ((~spi_busy)&&(~spi_wr))
1125
                begin
1126
                        o_wb_ack <= spif_req;
1127
                        state <= `WBQSPI_IDLE;
1128
                end
1129
        end else if (state == `WBQSPI_CLEAR_STATUS)
1130
        begin // Issue a clear status command
1131
                spi_wr <= 1'b1;
1132
                spi_hold <= 1'b0;
1133
                spi_len <= 2'b00; // 8 bit command
1134
                spi_in <= { 8'h30, 24'h00 };
1135
                spi_spd <= 1'b0;
1136
                spi_dir <= 1'b0;
1137
                last_status[6:5] <= 2'b00;
1138
                spif_req <= (spif_req) && (i_wb_cyc);
1139
                if ((spi_wr)&&(~spi_busy))
1140
                        state <= `WBQSPI_WAIT_TIL_IDLE;
1141
        end else if (state == `WBQSPI_IDLE_CHECK_WIP)
1142
        begin // We are now in read status register mode
1143
 
1144
                // No bus commands have (yet) been given
1145
                o_wb_stall <= 1'b1;
1146
                o_wb_ack   <= 1'b0;
1147
                spif_req <= (spif_req) && (i_wb_cyc);
1148
 
1149
                // Stay in this mode unless/until we get a command, or
1150
                //      the write is over
1151
                spi_wr <= (((~i_wb_cyc)||((~i_wb_data_stb)&&(~i_wb_ctrl_stb)))
1152
                                &&(write_in_progress));
1153
                spi_len <= 2'b00; // 8 bit reads
1154
                spi_spd <= 1'b0;  // SPI, not quad
1155
                spi_dir <= 1'b1;  // Read
1156
                if (spi_valid)
1157
                begin
1158
                        write_in_progress <= spi_out[0];
1159
                        if ((~spi_out[0])&&(write_in_progress))
1160
                                o_interrupt <= 1'b1;
1161
                end else
1162
                        o_interrupt <= 1'b0;
1163
 
1164
                if ((~spi_wr)&&(~spi_busy)&&(o_qspi_cs_n))
1165
                begin // We can now go to idle and process a command
1166
                        o_wb_stall <= 1'b0;
1167
                        o_wb_ack   <= 1'b0;
1168
                        state <= `WBQSPI_IDLE;
1169
                end
1170 7 dgisselq
`endif //       !READ_ONLY
1171 2 dgisselq
        end else // if (state == `WBQSPI_WAIT_TIL_IDLE) or anything else
1172
        begin
1173
                spi_wr     <= 1'b0;
1174
                spi_hold   <= 1'b0;
1175
                o_wb_stall <= 1'b1;
1176
                o_wb_ack   <= 1'b0;
1177
                spif_req   <= 1'b0;
1178
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
1179
                begin // clearing of the SPI port before moving on
1180
                        state <= `WBQSPI_IDLE;
1181
                        o_wb_stall <= 1'b0;
1182
                        o_wb_ack   <= 1'b0; // Shouldn't be acking anything here
1183
                end
1184
        end
1185 4 dgisselq
        end
1186 2 dgisselq
 
1187 4 dgisselq
        // Command and control during the reset sequence
1188
        assign  o_qspi_cs_n = (spif_override)?spif_cmd :w_qspi_cs_n;
1189
        assign  o_qspi_sck  = (spif_override)?spif_ctrl:w_qspi_sck;
1190
        assign  o_qspi_mod  = (spif_override)?   2'b01 :w_qspi_mod;
1191
        assign  o_qspi_dat  = (spif_override)?   4'b00 :w_qspi_dat;
1192 2 dgisselq
endmodule

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