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[/] [qspiflash/] [trunk/] [rtl/] [wbqspiflash.v] - Blame information for rev 2

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1 2 dgisselq
//
2
//
3
// Filename:    wbspiflash.v
4
//
5
// Project:     FPGA library development (Basys3 development board)
6
//
7
// Purpose:     Access a Quad SPI flash via a WISHBONE interface.  This
8
//              includes both read and write (and erase) commands to the SPI
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//              flash.  All read/write commands are accomplished using the
10
//              high speed (4-bit) interface.  Further, the device will be
11
//              left/kept in the 4-bit read interface mode between accesses,
12
//              for a minimum read latency.
13
//
14
//      Wishbone Registers (See Basys3 Wishbone HTML page):
15
//      0: local config(r) / erase commands(w) / deep power down cmds / etc.
16
//      R: (Write in Progress), (dirty-block), (spi_port_busy), 1'b0, 9'h00,
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//              { last_erased_sector, 14'h00 } if (WIP)
18
//              else { current_sector_being_erased, 14'h00 }
19
//              current if write in progress, last if written
20
//      W: (1'b1 to erase), (12'h ignored), next_erased_block, 14'h ignored)
21
//      1: Read ID (read only)
22
//      2: Status register (R(/w?)), reads update the WIP bit ...
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//      (19 bits): Data (R/w, but expect writes to take a while)
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//              
25
//
26
// Creator:     Dan Gisselquist
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//              Gisselquist Tecnology, LLC
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//
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// Copyright:   2015
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//
31
//
32
`define WBQSPI_RESET            0
33
`define WBQSPI_RESET_WEN        1
34
`define WBQSPI_IDLE             2
35
`define WBQSPI_RDIDLE           3       // Idle, but in fast read mode
36
`define WBQSPI_WBDECODE         4
37
`define WBQSPI_WAIT_WIP_CLEAR   5
38
`define WBQSPI_CHECK_WIP_CLEAR  6
39
`define WBQSPI_CHECK_WIP_DONE   7
40
`define WBQSPI_WEN              8
41
`define WBQSPI_PP               9       // Program page
42
`define WBQSPI_QPP              10      // Program page, 4 bit mode
43
`define WBQSPI_WR_DATA          11
44
`define WBQSPI_WR_BUS_CYCLE     12
45
`define WBQSPI_RD_DUMMY         13
46
`define WBQSPI_QRD_ADDRESS      14
47
`define WBQSPI_QRD_DUMMY        15
48
`define WBQSPI_READ_CMD         16
49
`define WBQSPI_READ_DATA        17
50
`define WBQSPI_WAIT_TIL_RDIDLE  18
51
`define WBQSPI_READ_ID_CMD      19
52
`define WBQSPI_READ_ID          20
53
`define WBQSPI_READ_STATUS      21
54
`define WBQSPI_READ_CONFIG      22
55
`define WBQSPI_WRITE_STATUS     23
56
`define WBQSPI_WRITE_CONFIG     24
57
`define WBQSPI_ERASE_WEN        25
58
`define WBQSPI_ERASE_CMD        26
59
`define WBQSPI_ERASE_BLOCK      27
60
`define WBQSPI_CLEAR_STATUS     28
61
`define WBQSPI_IDLE_CHECK_WIP   29
62
`define WBQSPI_WAIT_TIL_IDLE    30
63
 
64
module  wbqspiflash(i_clk_100mhz,
65
                // Internal wishbone connections
66
                i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,
67
                i_wb_addr, i_wb_data,
68
                // Wishbone return values
69
                o_wb_ack, o_wb_stall, o_wb_data,
70
                // Quad Spi connections to the external device
71
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
72
                o_interrupt,
73
                // Info for a wbscope
74
                o_debug);
75
        input                   i_clk_100mhz;
76
        // Wishbone, inputs first
77
        input                   i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
78
        input           [19:0]   i_wb_addr;
79
        input           [31:0]   i_wb_data;
80
        // then outputs
81
        output  reg             o_wb_ack;
82
        output  reg             o_wb_stall;
83
        output  reg     [31:0]   o_wb_data;
84
        // Quad SPI control wires
85
        output  wire            o_qspi_sck, o_qspi_cs_n;
86
        output  wire    [1:0]    o_qspi_mod;
87
        output  wire    [3:0]    o_qspi_dat;
88
        input           [3:0]    i_qspi_dat;
89
        // Interrupt line
90
        output  reg             o_interrupt;
91
        // Debug/scope
92
        output  wire    [31:0]   o_debug;
93
 
94
        reg             spi_wr, spi_hold, spi_spd, spi_dir;
95
        reg     [31:0]   spi_in;
96
        reg     [1:0]    spi_len;
97
        wire    [31:0]   spi_out;
98
        wire            spi_valid, spi_busy;
99
        wire    [22:0]   spi_dbg;
100
        llqspi  lldriver(i_clk_100mhz,
101
                        spi_wr, spi_hold, spi_in, spi_len, spi_spd, spi_dir,
102
                                spi_out, spi_valid, spi_busy,
103
                        o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat,
104
                                i_qspi_dat,
105
                        spi_dbg);
106
 
107
        // Erase status tracking
108
        reg             write_in_progress, write_protect;
109
        reg     [5:0]    erased_sector;
110
        reg             dirty_sector;
111
        initial begin
112
                write_in_progress = 1'b0;
113
                erased_sector = 6'h00;
114
                dirty_sector  = 1'b1;
115
                write_protect = 1'b1;
116
        end
117
 
118
        reg     [7:0]    last_status;
119
        reg             quad_mode_enabled;
120
        reg             spif_cmd;
121
        reg     [19:0]   spif_addr;
122
        reg     [31:0]   spif_data;
123
        reg     [5:0]    state;
124
        reg     [5:0]    spif_return;
125
        reg             spif_ctrl, spif_req;
126
        wire    [5:0]    spif_sector;
127
        assign  spif_sector = spif_addr[19:14];
128
 
129
        assign  o_debug = { spi_wr, spi_spd, spi_hold, state, spi_dbg };
130
 
131
        initial state = `WBQSPI_RESET;
132
        initial o_wb_ack   = 1'b0;
133
        initial o_wb_stall = 1'b1;
134
        initial spi_wr     = 1'b0;
135
        initial spi_len    = 2'b00;
136
        initial quad_mode_enabled = 1'b0;
137
        initial o_interrupt = 1'b0;
138
        always @(posedge i_clk_100mhz)
139
        if (state == `WBQSPI_RESET)
140
        begin
141
                // From a reset, we should
142
                //      Enable the Quad I/O mode
143
                //      Disable the Write protection bits in the status register
144
                //      Chip should already be up and running, so we can start
145
                //      immediately ....
146
                o_wb_ack <= 1'b0;
147
                o_wb_stall <= 1'b1;
148
                spi_hold <= 1'b0;
149
                spi_spd  <= 1'b0;
150
                spi_dir  <= 1'b0;
151
                last_status <= 8'h00;
152
                if (spi_len < 2'b11)
153
                        spi_len <= spi_len + 1;
154
                state <= `WBQSPI_IDLE;
155
                spif_req <= 1'b0;
156
        /*
157
        // This next bit of logic is confusing ...
158
        // I wish to enable quad SPI mode automatically.  However, this is
159
        // a configuration register thing, so once written it never needs to
160
        // be adjusted again.  Further, some bits within the configuration
161
        // register cannot be undone, and my inkling might be to set those.
162
        // Finally, the configuration register affects the control of the
163
        // block protect registers in the status register.  So ...
164
        // let's just leave these registers alone, or command them from the
165
        // UART-wishbone interface.
166
                else if (~spi_busy)
167
                begin
168
                        spi_wr  <= 1'b1;
169
                        spi_len <= 2'b00; // 1 byte
170
                        spi_in  <= { 8'h06, 24'h000 };
171
                end
172
        end else if (state == `WBQSPI_RESET_WEN)
173
        begin
174
                spi_wr <= 1'b0;
175
                if ((~spi_busy)&&(~spi_wr)&&(o_qspi_cs_n))
176
                begin
177
                        spi_wr  <= 1'b1;
178
                        spi_spd <= 1'b0;
179
                        spi_len <= 2'b10; // 3 bytes
180
                        // Command, status, config, then don't care
181
                        spi_in <= { 8'h01, 8'h00, 8'h0b, 8'h00 };
182
                        spi_dir <= 1'b0;
183
                        quad_mode_enabled <= 1'b1;
184
                        state <= `WBQSPI_WAIT_TIL_IDLE;
185
                        write_in_progress <= 1'b1;
186
                end
187
        */
188
        end else if (state == `WBQSPI_IDLE)
189
        begin
190
                o_interrupt <= 1'b0;
191
                o_wb_stall <= 1'b0;
192
                o_wb_ack <= 1'b0;
193
                spif_cmd   <= i_wb_we;
194
                spif_addr  <= i_wb_addr;
195
                spif_data  <= i_wb_data;
196
                spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
197
                spif_req   <= (i_wb_ctrl_stb)||(i_wb_data_stb);
198
                spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
199
                spi_hold <= 1'b0;
200
                spi_spd  <= 1'b0;
201
                spi_dir <= 1'b0; // Write (for now, 'cause of cmd)
202
                // Data register access
203
                if ((i_wb_data_stb)&&(i_wb_cyc))
204
                begin
205
 
206
                        if (i_wb_we) // Request to write a page
207
                        begin
208
                                if((~write_protect)&&(~write_in_progress))
209
                                begin // 00
210
                                        spi_wr <= 1'b1;
211
                                        spi_len <= 2'b00; // 8 bits
212
                                        // Send a write enable command
213
                                        spi_in <= { 8'h06, 24'h00 };
214
                                        state <= `WBQSPI_WEN;
215
 
216
                                        o_wb_ack <= 1'b0;
217
                                        o_wb_stall <= 1'b1;
218
                                end else if (write_protect)
219
                                begin // whether or not write-in_progress ...
220
                                        // Do nothing on a write protect
221
                                        // violation
222
                                        //
223
                                        o_wb_ack <= 1'b1;
224
                                        o_wb_stall <= 1'b0;
225
                                end else begin // write is in progress, wait
226
                                        // for it to complete
227
                                        state <= `WBQSPI_WAIT_WIP_CLEAR;
228
                                        o_wb_ack <= 1'b0;
229
                                        o_wb_stall <= 1'b1;
230
                                end
231
                        end else if (~write_in_progress)
232
                        begin // Read access, normal mode(s)
233
                                o_wb_ack   <= 1'b0;
234
                                o_wb_stall <= 1'b1;
235
                                spi_wr     <= 1'b1;     // Write cmd to device
236
                                if (quad_mode_enabled)
237
                                begin
238
                                        spi_in <= { 8'heb, 2'b00, i_wb_addr[19:0], 2'b00 };
239
                                        state <= `WBQSPI_QRD_ADDRESS;
240
                                        spi_len    <= 2'b00; // single byte, cmd only
241
                                end else begin
242
                                        spi_in <= { 8'h0b, 2'b00, i_wb_addr[19:0], 2'b00 };
243
                                        state <= `WBQSPI_RD_DUMMY;
244
                                        spi_len    <= 2'b11; // cmd+addr,32bits
245
                                end
246
                        end else begin
247
                                // A write is in progress ... need to stall
248
                                // the bus until the write is complete.
249
                                state <= `WBQSPI_WAIT_WIP_CLEAR;
250
                                o_wb_ack   <= 1'b0;
251
                                o_wb_stall <= 1'b1;
252
                        end
253
                end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)&&(i_wb_we))
254
                begin
255
                        o_wb_stall <= 1'b1;
256
                        case(i_wb_addr[1:0])
257
                        2'b00: begin // Erase command register
258
                                write_protect <= ~i_wb_data[28];
259
                                o_wb_stall <= 1'b0;
260
 
261
                                if((i_wb_data[31])&&(~write_in_progress))
262
                                begin
263
                                        // Command an erase--ack it immediately
264
 
265
                                        o_wb_ack <= 1'b1;
266
                                        o_wb_stall <= 1'b0;
267
 
268
                                        if ((i_wb_data[31])&&(~write_protect))
269
                                        begin
270
                                                spi_wr <= 1'b1;
271
                                                spi_len <= 2'b00;
272
                                                // Send a write enable command
273
                                                spi_in <= { 8'h06, 24'h00 };
274
                                                state <= `WBQSPI_ERASE_CMD;
275
                                                o_wb_stall <= 1'b1;
276
                                        end
277
                                end else if (i_wb_data[31])
278
                                begin
279
                                        state <= `WBQSPI_WAIT_WIP_CLEAR;
280
                                        o_wb_ack   <= 1'b1;
281
                                        o_wb_stall <= 1'b1;
282
                                end else
283
                                        o_wb_ack   <= 1'b1;
284
                                        o_wb_stall <= 1'b0;
285
                                end
286
                        2'b01: begin
287
                                // Write the configuration register
288
                                o_wb_ack <= 1'b1;
289
                                o_wb_stall <= 1'b1;
290
 
291
                                // Need to send a write enable command first
292
                                spi_wr <= 1'b1;
293
                                spi_len <= 2'b00; // 8 bits
294
                                // Send a write enable command
295
                                spi_in <= { 8'h06, 24'h00 };
296
                                state <= `WBQSPI_WRITE_CONFIG;
297
                                end
298
                        2'b10: begin
299
                                // Write the status register
300
                                o_wb_ack <= 1'b1; // Ack immediately
301
                                o_wb_stall <= 1'b1; // Stall other cmds
302
                                // Need to send a write enable command first
303
                                spi_wr <= 1'b1;
304
                                spi_len <= 2'b00; // 8 bits
305
                                // Send a write enable command
306
                                spi_in <= { 8'h06, 24'h00 };
307
                                state <= `WBQSPI_WRITE_STATUS;
308
                                end
309
                        2'b11: begin // Write the ID register??? makes no sense
310
                                o_wb_ack <= 1'b1;
311
                                o_wb_stall <= 1'b0;
312
                                end
313
                        endcase
314
                end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)) // &&(~i_wb_we))
315
                begin
316
                        case(i_wb_addr[1:0])
317
                        2'b00: begin // Read local register
318
                                if (write_in_progress) // Read status
319
                                begin// register, is write still in progress?
320
                                        state <= `WBQSPI_READ_STATUS;
321
                                        spi_wr <= 1'b1;
322
                                        spi_len <= 2'b01;// 8 bits out, 8 bits in
323
                                        spi_in <= { 8'h05, 24'h00};
324
 
325
                                        o_wb_ack <= 1'b0;
326
                                        o_wb_stall <= 1'b1;
327
                                end else begin // Return w/o talking to device
328
                                        o_wb_ack <= 1'b1;
329
                                        o_wb_stall <= 1'b0;
330
                                        o_wb_data <= { write_in_progress,
331
                                                dirty_sector, spi_busy,
332
                                                ~write_protect,
333
                                                quad_mode_enabled,
334
                                                7'h00,
335
                                                erased_sector, 14'h000 };
336
                                end end
337
                        2'b01: begin // Read configuration register
338
                                state <= `WBQSPI_READ_CONFIG;
339
                                spi_wr <= 1'b1;
340
                                spi_len <= 2'b01;
341
                                spi_in <= { 8'h35, 24'h00};
342
 
343
                                o_wb_ack <= 1'b0;
344
                                o_wb_stall <= 1'b1;
345
                                end
346
                        2'b10: begin // Read status register
347
                                state <= `WBQSPI_READ_STATUS;
348
                                spi_wr <= 1'b1;
349
                                spi_len <= 2'b01; // 8 bits out, 8 bits in
350
                                spi_in <= { 8'h05, 24'h00};
351
 
352
                                o_wb_ack <= 1'b0;
353
                                o_wb_stall <= 1'b1;
354
                                end
355
                        2'b11: begin // Read ID register
356
                                state <= `WBQSPI_READ_ID_CMD;
357
                                spi_wr <= 1'b1;
358
                                spi_len <= 2'b00;
359
                                spi_in <= { 8'h9f, 24'h00};
360
 
361
                                o_wb_ack <= 1'b0;
362
                                o_wb_stall <= 1'b1;
363
                                end
364
                        endcase
365
                end else if ((~i_wb_cyc)&&(write_in_progress))
366
                begin
367
                        state <= `WBQSPI_IDLE_CHECK_WIP;
368
                        spi_wr <= 1'b1;
369
                        spi_len <= 2'b01; // 8 bits out, 8 bits in
370
                        spi_in <= { 8'h05, 24'h00};
371
 
372
                        o_wb_ack <= 1'b0;
373
                        o_wb_stall <= 1'b1;
374
                end
375
        end else if (state == `WBQSPI_RDIDLE)
376
        begin
377
                spi_wr <= 1'b0;
378
                o_wb_stall <= 1'b0;
379
                o_wb_ack <= 1'b0;
380
                spif_cmd   <= i_wb_we;
381
                spif_addr  <= i_wb_addr;
382
                spif_data  <= i_wb_data;
383
                spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
384
                spif_req   <= (i_wb_ctrl_stb)||(i_wb_data_stb);
385
                spi_hold <= 1'b0;
386
                spi_spd<= 1'b1;
387
                spi_dir <= 1'b0; // Write (for now)
388
                if ((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we))
389
                begin // Continue our read ... send the new address / mode
390
                        o_wb_stall <= 1'b1;
391
                        spi_wr <= 1'b1;
392
                        spi_len <= 2'b10;
393
                        spi_in <= { 2'h0, i_wb_addr[19:0], 2'h0, 8'ha0 };
394
                        state <= `WBQSPI_QRD_DUMMY;
395
                end else if((i_wb_cyc)&&(i_wb_ctrl_stb)&&(~i_wb_we)&&(i_wb_addr[1:0] == 2'b00))
396
                begin
397
                        // A local read that doesn't touch the device, so leave
398
                        // the device in its current state
399
                        o_wb_stall <= 1'b0;
400
                        o_wb_ack <= 1'b1;
401
                        o_wb_data <= { write_in_progress,
402
                                        dirty_sector, spi_busy,
403
                                        ~write_protect,
404
                                        quad_mode_enabled,
405
                                        7'h00,
406
                                        erased_sector, 14'h000 };
407
                end else if((i_wb_cyc)&&((i_wb_ctrl_stb)||(i_wb_data_stb)))
408
                begin // Need to release the device from quad mode for all else
409
                        o_wb_ack   <= 1'b0;
410
                        o_wb_stall <= 1'b1;
411
                        spi_wr <= 1'b1;
412
                        spi_len <= 2'b11;
413
                        spi_in <= 32'h00;
414
                        state <= `WBQSPI_WBDECODE;
415
                end
416
        end else if (state == `WBQSPI_WBDECODE)
417
        begin
418
                // We were in quad SPI read mode, and had to get out.
419
                // Now we've got a command (not data read) to read and
420
                // execute.  Accomplish what we would've done while in the
421
                // IDLE state here, save only that we don't have to worry
422
                // about data reads, and we need to operate on a stored
423
                // version of the bus command
424
                o_wb_stall <= 1'b1;
425
                o_wb_ack <= 1'b0;
426
                spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
427
                spi_hold <= 1'b0;
428
                spi_spd <= 1'b0;
429
                spi_dir <= 1'b0;
430
                spif_req<= (spif_req) && (i_wb_cyc);
431
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // only in full idle ...
432
                begin
433
                        // Data register access
434
                        if (~spif_ctrl)
435
                        begin
436
                                if (spif_cmd) // Request to write a page
437
                                begin
438
                                        if((~write_protect)&&(~write_in_progress))
439
                                        begin // 00
440
                                                spi_wr <= 1'b1;
441
                                                spi_len <= 2'b00; // 8 bits
442
                                                // Send a write enable command
443
                                                spi_in <= { 8'h06, 24'h00 };
444
                                                state <= `WBQSPI_WEN;
445
 
446
                                                o_wb_ack <= 1'b0;
447
                                                o_wb_stall <= 1'b1;
448
                                        end else if (write_protect)
449
                                        begin // whether or not write-in_progress ...
450
                                                // Do nothing on a write protect
451
                                                // violation
452
                                                //
453
                                                o_wb_ack <= spif_req;
454
                                                o_wb_stall <= 1'b0;
455
                                                state <= `WBQSPI_IDLE;
456
                                        end else begin // write is in progress, wait
457
                                                // for it to complete
458
                                                state <= `WBQSPI_WAIT_WIP_CLEAR;
459
                                                o_wb_ack <= 1'b0;
460
                                                o_wb_stall <= 1'b1;
461
                                        end
462
                                // end else if (~write_in_progress) // always true
463
                                // but ... we wouldn't get here on a normal read access
464
                                end else begin
465
                                        // Something's wrong, we should never get here
466
                                        // Attempt to go to idle to recover
467
                                        state <= `WBQSPI_IDLE;
468
                                end
469
                        end else if ((spif_ctrl)&&(spif_cmd))
470
                        begin
471
                                o_wb_stall <= 1'b1;
472
                                case(spif_addr[1:0])
473
                                2'b00: begin // Erase command register
474
                                        o_wb_ack   <= spif_req;
475
                                        o_wb_stall <= 1'b0;
476
                                        state <= `WBQSPI_IDLE;
477
                                        write_protect <= ~spif_data[28];
478
                                        // Are we commanding an erase?
479
                                        // We're in read mode, writes cannot
480
                                        // be in progress, so ...
481
                                        if (spif_data[31]) // Command an erase
482
                                        begin
483
                                                // Since we're not going back
484
                                                // to IDLE, we must stall the
485
                                                // bus here
486
                                                o_wb_stall <= 1'b1;
487
                                                spi_wr <= 1'b1;
488
                                                spi_len <= 2'b00;
489
                                                // Send a write enable command
490
                                                spi_in <= { 8'h06, 24'h00 };
491
                                                state <= `WBQSPI_ERASE_CMD;
492
                                        end end
493
                                2'b01: begin
494
                                        // Write the configuration register
495
                                        o_wb_ack <= spif_req;
496
                                        o_wb_stall <= 1'b1;
497
 
498
                                        // Need to send a write enable command first
499
                                        spi_wr <= 1'b1;
500
                                        spi_len <= 2'b00; // 8 bits
501
                                        // Send a write enable command
502
                                        spi_in <= { 8'h06, 24'h00 };
503
                                        state <= `WBQSPI_WRITE_CONFIG;
504
                                        end
505
                                2'b10: begin
506
                                        // Write the status register
507
                                        o_wb_ack <= spif_req; // Ack immediately
508
                                        o_wb_stall <= 1'b1; // Stall other cmds
509
                                        // Need to send a write enable command first
510
                                        spi_wr <= 1'b1;
511
                                        spi_len <= 2'b00; // 8 bits
512
                                        // Send a write enable command
513
                                        spi_in <= { 8'h06, 24'h00 };
514
                                        state <= `WBQSPI_WRITE_STATUS;
515
                                        end
516
                                2'b11: begin // Write the ID register??? makes no sense
517
                                        o_wb_ack <= spif_req;
518
                                        o_wb_stall <= 1'b0;
519
                                        state <= `WBQSPI_IDLE;
520
                                        end
521
                                endcase
522
                        end else begin // on (~spif_we)
523
                                case(spif_addr[1:0])
524
                                2'b00: begin // Read local register
525
                                        // Nonsense case--would've done this
526
                                        // already
527
                                        state <= `WBQSPI_IDLE;
528
                                        o_wb_ack <= spif_req;
529
                                        o_wb_stall <= 1'b0;
530
                                        end
531
                                2'b01: begin // Read configuration register
532
                                        state <= `WBQSPI_READ_CONFIG;
533
                                        spi_wr <= 1'b1;
534
                                        spi_len <= 2'b01;
535
                                        spi_in <= { 8'h35, 24'h00};
536
 
537
                                        o_wb_ack <= 1'b0;
538
                                        o_wb_stall <= 1'b1;
539
                                        end
540
                                2'b10: begin // Read status register
541
                                        state <= `WBQSPI_READ_STATUS;
542
                                        spi_wr <= 1'b1;
543
                                        spi_len <= 2'b01; // 8 bits out, 8 bits in
544
                                        spi_in <= { 8'h05, 24'h00};
545
 
546
                                        o_wb_ack <= 1'b0;
547
                                        o_wb_stall <= 1'b1;
548
                                        end
549
                                2'b11: begin // Read ID register
550
                                        state <= `WBQSPI_READ_ID_CMD;
551
                                        spi_wr <= 1'b1;
552
                                        spi_len <= 2'b00;
553
                                        spi_in <= { 8'h9f, 24'h00};
554
 
555
                                        o_wb_ack <= 1'b0;
556
                                        o_wb_stall <= 1'b1;
557
                                        end
558
                                endcase
559
                        end
560
                end
561
        end else if (state == `WBQSPI_WAIT_WIP_CLEAR)
562
        begin
563
                o_wb_stall <= 1'b1;
564
                o_wb_ack   <= 1'b0;
565
                spi_wr <= 1'b0;
566
                spif_req<= (spif_req) && (i_wb_cyc);
567
                if (~spi_busy)
568
                begin
569
                        spi_wr   <= 1'b1;
570
                        spi_in   <= { 8'h05, 24'h0000 };
571
                        spi_hold <= 1'b1;
572
                        spi_len  <= 2'b01; // 16 bits write, so we can read 8
573
                        state <= `WBQSPI_CHECK_WIP_CLEAR;
574
                        spi_spd  <= 1'b0; // Slow speed
575
                        spi_dir  <= 1'b0;
576
                end
577
        end else if (state == `WBQSPI_CHECK_WIP_CLEAR)
578
        begin
579
                o_wb_stall <= 1'b1;
580
                o_wb_ack   <= 1'b0;
581
                // Repeat as often as necessary until we are clear
582
                spi_wr <= 1'b1;
583
                spi_in <= 32'h0000; // Values here are actually irrelevant
584
                spi_hold <= 1'b1;
585
                spi_len <= 2'b00; // One byte at a time
586
                spi_spd  <= 1'b0; // Slow speed
587
                spi_dir  <= 1'b0;
588
                spif_req<= (spif_req) && (i_wb_cyc);
589
                if ((spi_valid)&&(~spi_out[0]))
590
                begin
591
                        state <= `WBQSPI_CHECK_WIP_DONE;
592
                        spi_wr   <= 1'b0;
593
                        spi_hold <= 1'b0;
594
                        write_in_progress <= 1'b0;
595
                        last_status <= spi_out[7:0];
596
                end
597
        end else if (state == `WBQSPI_CHECK_WIP_DONE)
598
        begin
599
                o_wb_stall <= 1'b1;
600
                o_wb_ack   <= 1'b0;
601
                // Let's let the SPI port come back to a full idle,
602
                // and the chip select line go low before continuing
603
                spi_wr   <= 1'b0;
604
                spi_len  <= 2'b00;
605
                spi_hold <= 1'b0;
606
                spi_spd  <= 1'b0; // Slow speed
607
                spi_dir  <= 1'b0;
608
                spif_req<= (spif_req) && (i_wb_cyc);
609
                if ((o_qspi_cs_n)&&(~spi_busy)) // Chip select line is high, we can continue
610
                begin
611
                        spi_wr   <= 1'b0;
612
                        spi_hold <= 1'b0;
613
 
614
                        casez({ spif_cmd, spif_ctrl, spif_addr[1:0] })
615
                        4'b00??: begin // Read data from ... somewhere
616
                                spi_wr     <= 1'b1;     // Write cmd to device
617
                                if (quad_mode_enabled)
618
                                begin
619
                                        spi_in <= { 8'heb, 2'b00, spif_addr[19:0], 2'b00 };
620
                                        state <= `WBQSPI_QRD_DUMMY;
621
                                end else begin
622
                                        spi_in <= { 8'h0b, 2'b00, spif_addr[19:0], 2'b00 };
623
                                        state <= `WBQSPI_RD_DUMMY;
624
                                end end
625
                        4'b10??: begin // Write data to ... anywhere
626
                                spi_wr <= 1'b1;
627
                                spi_len <= 2'b00; // 8 bits
628
                                // Send a write enable command
629
                                spi_in <= { 8'h06, 24'h00 };
630
                                state <= `WBQSPI_WEN;
631
                                end
632
                        4'b0110: begin // Read status register
633
                                state <= `WBQSPI_READ_STATUS;
634
                                spi_wr <= 1'b1;
635
                                spi_len <= 2'b01; // 8 bits out, 8 bits in
636
                                spi_in <= { 8'h05, 24'h00};
637
                                end
638
                        4'b0111: begin
639
                                state <= `WBQSPI_READ_ID_CMD;
640
                                spi_wr <= 1'b1;
641
                                spi_len <= 2'b00;
642
                                spi_in <= { 8'h9f, 24'h00};
643
                                end
644
                        default: begin //
645
                                o_wb_stall <= 1'b1;
646
                                o_wb_ack <= spif_req;
647
                                state <= `WBQSPI_WAIT_TIL_IDLE;
648
                                end
649
                        endcase
650
                // spif_cmd   <= i_wb_we;
651
                // spif_addr  <= i_wb_addr;
652
                // spif_data  <= i_wb_data;
653
                // spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
654
                // spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
655
                end
656
        end else if (state == `WBQSPI_WEN)
657
        begin // We came here after issuing a write enable command
658
                spi_wr <= 1'b0;
659
                o_wb_ack <= 1'b0;
660
                o_wb_stall <= 1'b1;
661
                spif_req<= (spif_req) && (i_wb_cyc);
662
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Let's come to a full stop
663
                        // state <= (quad_mode_enabled)?`WBQSPI_QPP:`WBQSPI_PP;
664
                        state <= `WBQSPI_PP;
665
        end else if (state == `WBQSPI_PP)
666
        begin // We come here under a full stop / full port idle mode
667
                // Issue our command immediately
668
                spi_wr <= 1'b1;
669
                spi_in <= { 8'h02, 2'h0, spif_addr, 2'b00 };
670
                spi_len <= 2'b11;
671
                spi_hold <= 1'b1;
672
                spi_spd  <= 1'b0;
673
                spi_dir  <= 1'b0; // Writing
674
                spif_req<= (spif_req) && (i_wb_cyc);
675
 
676
                // Once we get busy, move on
677
                if (spi_busy)
678
                        state <= `WBQSPI_WR_DATA;
679
                if (spif_sector == erased_sector)
680
                        dirty_sector <= 1'b1;
681
        end else if (state == `WBQSPI_QPP)
682
        begin // We come here under a full stop / full port idle mode
683
                // Issue our command immediately
684
                spi_wr <= 1'b1;
685
                spi_in <= { 8'h32, 2'h0, spif_addr, 2'b00 };
686
                spi_len <= 2'b11;
687
                spi_hold <= 1'b1;
688
                spi_spd  <= 1'b0;
689
                spi_dir  <= 1'b0; // Writing
690
                spif_req<= (spif_req) && (i_wb_cyc);
691
 
692
                // Once we get busy, move on
693
                if (spi_busy)
694
                begin
695
                        // spi_wr is irrelevant here ...
696
                        // Set the speed value once, but wait til we get busy
697
                        // to do so.
698
                        spi_spd <= 1'b1;
699
                        state <= `WBQSPI_WR_DATA;
700
                end
701
                if (spif_sector == erased_sector)
702
                        dirty_sector <= 1'b1;
703
        end else if (state == `WBQSPI_WR_DATA)
704
        begin
705
                o_wb_stall <= 1'b1;
706
                o_wb_ack   <= 1'b0;
707
                spi_wr   <= 1'b1; // write without waiting
708
                spi_in   <= {
709
                        spif_data[ 7: 0],
710
                        spif_data[15: 8],
711
                        spif_data[23:16],
712
                        spif_data[31:24] };
713
                spi_len  <= 2'b11; // Write 4 bytes
714
                spi_hold <= 1'b1;
715
                if (~spi_busy)
716
                begin
717
                        o_wb_ack <= spif_req; // Ack when command given
718
                        state <= `WBQSPI_WR_BUS_CYCLE;
719
                end
720
                spif_req<= (spif_req) && (i_wb_cyc);
721
        end else if (state == `WBQSPI_WR_BUS_CYCLE)
722
        begin
723
                o_wb_ack <= 1'b0; // Turn off our ack and stall flags
724
                o_wb_stall <= 1'b1;
725
                spi_wr <= 1'b0;
726
                spi_hold <= 1'b1;
727
                write_in_progress <= 1'b1;
728
                spif_req<= (spif_req) && (i_wb_cyc);
729
                if (~i_wb_cyc)
730
                begin
731
                        state <= `WBQSPI_WAIT_TIL_IDLE;
732
                        spi_hold <= 1'b0;
733
                end else if (spi_wr)
734
                begin // Give the SPI a chance to get busy on the last write
735
                        // Do nothing here.
736
                end else if ((i_wb_data_stb)&&(i_wb_we)
737
                                &&(i_wb_addr == (spif_addr+1))
738
                                &&(i_wb_addr[19:6]==spif_addr[19:6]))
739
                begin
740
                        spif_cmd  <= 1'b1;
741
                        spif_data <= i_wb_data;
742
                        spif_addr <= i_wb_addr;
743
                        spif_ctrl  <= 1'b0;
744
                        spif_req<= 1'b1;
745
                        // We'll keep the bus stalled on this request
746
                        // for a while
747
                        state <= `WBQSPI_WR_DATA;
748
                        o_wb_ack   <= 1'b0;
749
                        o_wb_stall <= 1'b0;
750
                end else if ((i_wb_data_stb|i_wb_ctrl_stb)&&(~o_wb_ack)) // Writing out of bounds
751
                begin
752
                        spi_hold <= 1'b0;
753
                        spi_wr   <= 1'b0;
754
                        state <= `WBQSPI_WAIT_TIL_IDLE;
755
                end // Otherwise we stay here
756
        end else if (state == `WBQSPI_RD_DUMMY)
757
        begin
758
                o_wb_ack   <= 1'b0;
759
                o_wb_stall <= 1'b1;
760
 
761
                spi_wr <= 1'b1; // Non-stop
762
                // Need to read one byte of dummy data,
763
                // just to consume 8 clocks
764
                spi_in <= { 8'h00, 24'h00 };
765
                spi_len <= 2'b00; // Read 8 bits
766
                spi_spd <= 1'b0;
767
                spi_hold <= 1'b0;
768
                spif_req<= (spif_req) && (i_wb_cyc);
769
 
770
                if ((~spi_busy)&&(~o_qspi_cs_n))
771
                        // Our command was accepted
772
                        state <= `WBQSPI_READ_CMD;
773
        end else if (state == `WBQSPI_QRD_ADDRESS)
774
        begin
775
                // We come in here immediately upon issuing a QRD read
776
                // command (8-bits), but we have to pause to give the
777
                // address (24-bits) and mode (8-bits) in quad speed.
778
                o_wb_ack   <= 1'b0;
779
                o_wb_stall <= 1'b1;
780
 
781
                spi_wr <= 1'b1; // Non-stop
782
                spi_in <= { 2'b0, spif_addr, 2'b0, 8'ha0 };
783
                spi_len <= 2'b11; // Write all 32 bits bits
784
                spi_spd <= 1'b1;
785
                spi_dir <= 1'b0; // Still writing
786
                spi_hold <= 1'b0;
787
                spif_req<= (spif_req) && (i_wb_cyc);
788
 
789
                if ((~spi_busy)&&(spi_spd))
790
                        // Our command was accepted
791
                        state <= `WBQSPI_QRD_DUMMY;
792
        end else if (state == `WBQSPI_QRD_DUMMY)
793
        begin
794
                o_wb_ack   <= 1'b0;
795
                o_wb_stall <= 1'b1;
796
 
797
                spi_wr <= 1'b1; // Non-stop
798
                spi_in <= { 8'ha0, 24'h00 }; // Mode byte, then 2 bytes dummy
799
                spi_len <= 2'b10; // Write 8 bits
800
                spi_spd <= 1'b1;
801
                spi_dir <= 1'b0; // Still writing
802
                spi_hold <= 1'b0;
803
                spif_req<= (spif_req) && (i_wb_cyc);
804
 
805
                if ((~spi_busy)&&(spi_in[31:28] == 4'ha))
806
                        // Our command was accepted
807
                        state <= `WBQSPI_READ_CMD;
808
        end else if (state == `WBQSPI_READ_CMD)
809
        begin // Issue our first command to read 32 bits.
810
                o_wb_ack   <= 1'b0;
811
                o_wb_stall <= 1'b1;
812
 
813
                spi_wr <= 1'b1;
814
                spi_in <= { 8'hff, 24'h00 }; // Empty
815
                spi_len <= 2'b11; // Read 32 bits
816
                spi_dir <= 1'b1; // Now reading
817
                spi_hold <= 1'b0;
818
                spif_req<= (spif_req) && (i_wb_cyc);
819
                if ((spi_valid)&&(spi_len == 2'b11))
820
                        state <= `WBQSPI_READ_DATA;
821
        end else if (state == `WBQSPI_READ_DATA)
822
        begin
823
                // Pipelined read support
824
                spi_wr <=((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we)&&(i_wb_addr== (spif_addr+1)));
825
                // spi_wr <= 1'b0; // No pipelined read support
826
                spi_in <= 32'h00;
827
                spi_len <= 2'b11;
828
                // Don't adjust the speed here, it was set in the setup
829
                spi_dir <= 1'b1; // Now we get to read
830
                spi_hold <= 1'b0;
831
                spif_req<= (spif_req) && (i_wb_cyc);
832
                if ((spi_valid)&&(~spi_in[31]))
833
                begin // Single pulse acknowledge and write data out
834
                        o_wb_ack <= spif_req;
835
                        o_wb_stall <= (~spi_wr);
836
                        // adjust endian-ness to match the PC
837
                        o_wb_data <= { spi_out[7:0], spi_out[15:8],
838
                                spi_out[23:16], spi_out[31:24] };
839
                        state <= (spi_wr)?`WBQSPI_READ_DATA
840
                                : ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
841
                        spif_req <= spi_wr;
842
                        if (spi_wr)
843
                                spif_addr <= i_wb_addr;
844
                end else begin
845
                        o_wb_ack <= 1'b0;
846
                        o_wb_stall <= 1'b1;
847
                end
848
        end else if (state == `WBQSPI_WAIT_TIL_RDIDLE)
849
        begin // Wait 'til idle, but then go to fast read idle instead of full
850
                spi_wr     <= 1'b0;     // idle
851
                spi_hold   <= 1'b0;
852
                o_wb_stall <= 1'b1;
853
                o_wb_ack   <= 1'b0;
854
                spif_req   <= 1'b0;
855
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
856
                begin // clearing of the SPI port before moving on
857
                        state <= `WBQSPI_RDIDLE;
858
                        o_wb_stall <= 1'b0;
859
                        o_wb_ack   <= 1'b0;// Shouldn't be acking anything here
860
                end
861
        end else if (state == `WBQSPI_READ_ID_CMD)
862
        begin // We came into here immediately after issuing a 0x9f command
863
                // Now we need to read 32 bits of data.  Result should be
864
                // 0x0102154d (8'h manufacture ID, 16'h device ID, followed
865
                // by the number of extended bytes available 8'h4d).
866
                o_wb_ack <= 1'b0;
867
                o_wb_stall<= 1'b1;
868
 
869
                spi_wr <= 1'b1; // No data to send, but need four bytes, since
870
                spi_len <= 2'b11; // 32 bits of data are ... useful
871
                spi_in <= 32'h00; // Irrelevant
872
                spi_spd <= 1'b0; // Slow speed
873
                spi_dir <= 1'b1; // Reading
874
                spi_hold <= 1'b0;
875
                spif_req <= (spif_req) && (i_wb_cyc);
876
                if ((~spi_busy)&&(~o_qspi_cs_n)&&(spi_len == 2'b11))
877
                        // Our command was accepted, now go read the result
878
                        state <= `WBQSPI_READ_ID;
879
        end else if (state == `WBQSPI_READ_ID)
880
        begin
881
                o_wb_ack <= 1'b0; // Assuming we're still waiting
882
                o_wb_stall <= 1'b1;
883
 
884
                spi_wr <= 1'b0; // No more writes, we'ev already written the cmd
885
                spi_hold <= 1'b0;
886
                spif_req <= (spif_req) && (i_wb_cyc);
887
 
888
                // Here, we just wait until the result comes back
889
                // The problem is, the result may be the previous result.
890
                // So we use spi_len as an indicator
891
                spi_len <= 2'b00;
892
                if((spi_valid)&&(spi_len==2'b00))
893
                begin // Put the results out as soon as possible
894
                        o_wb_data <= spi_out[31:0];
895
                        o_wb_ack <= spif_req;
896
                        spif_req <= 1'b0;
897
                end else if ((~spi_busy)&&(~o_qspi_cs_n))
898
                begin
899
                        state <= `WBQSPI_IDLE;
900
                        o_wb_stall <= 1'b0;
901
                end
902
        end else if (state == `WBQSPI_READ_STATUS)
903
        begin // We enter after the command has been given, for now just
904
                // read and return
905
                spi_wr <= 1'b0;
906
                o_wb_ack <= 1'b0;
907
                spi_hold <= 1'b0;
908
                spif_req <= (spif_req) && (i_wb_cyc);
909
                if (spi_valid)
910
                begin
911
                        o_wb_ack <= spif_req;
912
                        o_wb_stall <= 1'b1;
913
                        spif_req <= 1'b0;
914
                        last_status <= spi_out[7:0];
915
                        write_in_progress <= spi_out[0];
916
                        if (spif_addr[1:0] == 2'b00) // Local read, checking
917
                        begin // status, 'cause we're writing
918
                                o_wb_data <= { spi_out[0],
919
                                        dirty_sector, spi_busy,
920
                                        ~write_protect,
921
                                        quad_mode_enabled,
922
                                        7'h00,
923
                                        erased_sector, 14'h000 };
924
                        end else begin
925
                                o_wb_data <= { 24'h00, spi_out[7:0] };
926
                        end
927
                end
928
 
929
                if ((~spi_busy)&&(~spi_wr))
930
                        state <= `WBQSPI_IDLE;
931
        end else if (state == `WBQSPI_READ_CONFIG)
932
        begin // We enter after the command has been given, for now just
933
                // read and return
934
                spi_wr <= 1'b0;
935
                o_wb_ack <= 1'b0;
936
                o_wb_stall <= 1'b1;
937
                spi_hold <= 1'b0;
938
                spif_req <= (spif_req) && (i_wb_cyc);
939
 
940
                if (spi_valid)
941
                begin
942
                        o_wb_data <= { 24'h00, spi_out[7:0] };
943
                        quad_mode_enabled <= spi_out[1];
944
                end
945
 
946
                if ((~spi_busy)&&(~spi_wr))
947
                begin
948
                        state <= `WBQSPI_IDLE;
949
                        o_wb_ack   <= spif_req;
950
                        o_wb_stall <= 1'b0;
951
                        spif_req <= 1'b0;
952
                end
953
        end else if (state == `WBQSPI_WRITE_CONFIG)
954
        begin // We enter immediately after commanding a WEN
955
                o_wb_ack   <= 1'b0;
956
                o_wb_stall <= 1'b1;
957
 
958
                spi_len <= 2'b10;
959
                spi_in <= { 8'h01, last_status, spif_data[7:0], 8'h00 };
960
                spi_wr <= 1'b0;
961
                spi_hold <= 1'b0;
962
                spif_req <= (spif_req) && (i_wb_cyc);
963
                if ((~spi_busy)&&(~spi_wr))
964
                begin
965
                        spi_wr <= 1'b1;
966
                        state <= `WBQSPI_WAIT_TIL_IDLE;
967
                        write_in_progress <= 1'b1;
968
                        quad_mode_enabled <= spif_data[1];
969
                end
970
        end else if (state == `WBQSPI_WRITE_STATUS)
971
        begin // We enter immediately after commanding a WEN
972
                o_wb_ack   <= 1'b0;
973
                o_wb_stall <= 1'b1;
974
 
975
                spi_len <= 2'b01;
976
                spi_in <= { 8'h01, spif_data[7:0], 16'h00 };
977
                // last_status <= i_wb_data[7:0]; // We'll read this in a moment
978
                spi_wr <= 1'b0;
979
                spi_hold <= 1'b0;
980
                spif_req <= (spif_req) && (i_wb_cyc);
981
                if ((~spi_busy)&&(~spi_wr))
982
                begin
983
                        spi_wr <= 1'b1;
984
                        last_status <= spif_data[7:0];
985
                        write_in_progress <= 1'b1;
986
                        if(((last_status[6])||(last_status[5]))
987
                                &&((~spif_data[6])&&(~spif_data[5])))
988
                                state <= `WBQSPI_CLEAR_STATUS;
989
                        else
990
                                state <= `WBQSPI_WAIT_TIL_IDLE;
991
                end
992
        end else if (state == `WBQSPI_ERASE_CMD)
993
        begin // Know that WIP is clear on entry, WEN has just been commanded
994
                spi_wr     <= 1'b0;
995
                o_wb_ack   <= 1'b0;
996
                o_wb_stall <= 1'b1;
997
                spi_hold   <= 1'b0;
998
                spi_spd <= 1'b0;
999
                spi_dir <= 1'b0;
1000
                spif_req <= (spif_req) && (i_wb_cyc);
1001
 
1002
                // Here's the erase command
1003
                spi_in <= { 8'hd8, 2'h0, spif_data[19:14], 14'h000, 2'b00 };
1004
                spi_len <= 2'b11; // 32 bit write
1005
                // together with setting our copy of the WIP bit
1006
                write_in_progress <= 1'b1;
1007
                // keeping track of which sector we just erased
1008
                erased_sector <= spif_data[19:14];
1009
                // and marking this erase sector as no longer dirty
1010
                dirty_sector <= 1'b0;
1011
 
1012
                // Wait for a full stop before issuing this command
1013
                if ((~spi_busy)&&(~spi_wr)&&(o_qspi_cs_n))
1014
                begin // When our command is accepted, move to the next state
1015
                        spi_wr <= 1'b1;
1016
                        state <= `WBQSPI_ERASE_BLOCK;
1017
                end
1018
        end else if (state == `WBQSPI_ERASE_BLOCK)
1019
        begin
1020
                spi_wr     <= 1'b0;
1021
                spi_hold   <= 1'b0;
1022
                o_wb_stall <= 1'b1;
1023
                o_wb_ack   <= 1'b0;
1024
                spif_req <= (spif_req) && (i_wb_cyc);
1025
                // When the port clears, we can head back to idle
1026
                if ((~spi_busy)&&(~spi_wr))
1027
                begin
1028
                        o_wb_ack <= spif_req;
1029
                        state <= `WBQSPI_IDLE;
1030
                end
1031
        end else if (state == `WBQSPI_CLEAR_STATUS)
1032
        begin // Issue a clear status command
1033
                spi_wr <= 1'b1;
1034
                spi_hold <= 1'b0;
1035
                spi_len <= 2'b00; // 8 bit command
1036
                spi_in <= { 8'h30, 24'h00 };
1037
                spi_spd <= 1'b0;
1038
                spi_dir <= 1'b0;
1039
                last_status[6:5] <= 2'b00;
1040
                spif_req <= (spif_req) && (i_wb_cyc);
1041
                if ((spi_wr)&&(~spi_busy))
1042
                        state <= `WBQSPI_WAIT_TIL_IDLE;
1043
        end else if (state == `WBQSPI_IDLE_CHECK_WIP)
1044
        begin // We are now in read status register mode
1045
 
1046
                // No bus commands have (yet) been given
1047
                o_wb_stall <= 1'b1;
1048
                o_wb_ack   <= 1'b0;
1049
                spif_req <= (spif_req) && (i_wb_cyc);
1050
 
1051
                // Stay in this mode unless/until we get a command, or
1052
                //      the write is over
1053
                spi_wr <= (((~i_wb_cyc)||((~i_wb_data_stb)&&(~i_wb_ctrl_stb)))
1054
                                &&(write_in_progress));
1055
                spi_len <= 2'b00; // 8 bit reads
1056
                spi_spd <= 1'b0;  // SPI, not quad
1057
                spi_dir <= 1'b1;  // Read
1058
                if (spi_valid)
1059
                begin
1060
                        write_in_progress <= spi_out[0];
1061
                        if ((~spi_out[0])&&(write_in_progress))
1062
                                o_interrupt <= 1'b1;
1063
                end else
1064
                        o_interrupt <= 1'b0;
1065
 
1066
                if ((~spi_wr)&&(~spi_busy)&&(o_qspi_cs_n))
1067
                begin // We can now go to idle and process a command
1068
                        o_wb_stall <= 1'b0;
1069
                        o_wb_ack   <= 1'b0;
1070
                        state <= `WBQSPI_IDLE;
1071
                end
1072
        end else // if (state == `WBQSPI_WAIT_TIL_IDLE) or anything else
1073
        begin
1074
                spi_wr     <= 1'b0;
1075
                spi_hold   <= 1'b0;
1076
                o_wb_stall <= 1'b1;
1077
                o_wb_ack   <= 1'b0;
1078
                spif_req   <= 1'b0;
1079
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
1080
                begin // clearing of the SPI port before moving on
1081
                        state <= `WBQSPI_IDLE;
1082
                        o_wb_stall <= 1'b0;
1083
                        o_wb_ack   <= 1'b0; // Shouldn't be acking anything here
1084
                end
1085
        end
1086
 
1087
endmodule

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