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[/] [qspiflash/] [trunk/] [rtl/] [wbqspiflash.v] - Blame information for rev 4

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1 3 dgisselq
///////////////////////////////////////////////////////////////////////////
2 2 dgisselq
//
3
// Filename:    wbspiflash.v
4
//
5 3 dgisselq
// Project:     Wishbone Controlled Quad SPI Flash Controller
6 2 dgisselq
//
7
// Purpose:     Access a Quad SPI flash via a WISHBONE interface.  This
8
//              includes both read and write (and erase) commands to the SPI
9
//              flash.  All read/write commands are accomplished using the
10
//              high speed (4-bit) interface.  Further, the device will be
11
//              left/kept in the 4-bit read interface mode between accesses,
12
//              for a minimum read latency.
13
//
14 3 dgisselq
//      Wishbone Registers (See spec sheet for more detail):
15 2 dgisselq
//      0: local config(r) / erase commands(w) / deep power down cmds / etc.
16
//      R: (Write in Progress), (dirty-block), (spi_port_busy), 1'b0, 9'h00,
17
//              { last_erased_sector, 14'h00 } if (WIP)
18
//              else { current_sector_being_erased, 14'h00 }
19
//              current if write in progress, last if written
20
//      W: (1'b1 to erase), (12'h ignored), next_erased_block, 14'h ignored)
21 3 dgisselq
//      1: Configuration register
22
//      2: Status register (R/w)
23
//      3: Read ID (read only)
24 2 dgisselq
//      (19 bits): Data (R/w, but expect writes to take a while)
25
//              
26
//
27
// Creator:     Dan Gisselquist
28
//              Gisselquist Tecnology, LLC
29
//
30 3 dgisselq
///////////////////////////////////////////////////////////////////////////
31 2 dgisselq
//
32 3 dgisselq
// Copyright (C) 2015, Gisselquist Technology, LLC
33 2 dgisselq
//
34 3 dgisselq
// This program is free software (firmware): you can redistribute it and/or
35
// modify it under the terms of  the GNU General Public License as published
36
// by the Free Software Foundation, either version 3 of the License, or (at
37
// your option) any later version.
38
//
39
// This program is distributed in the hope that it will be useful, but WITHOUT
40
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
41
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
42
// for more details.
43
//
44
// You should have received a copy of the GNU General Public License along
45
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
46
// target there if the PDF file isn't present.)  If not, see
47
// <http://www.gnu.org/licenses/> for a copy.
48
//
49
// License:     GPL, v3, as defined and found on www.gnu.org,
50
//              http://www.gnu.org/licenses/gpl.html
51
//
52
//
53
///////////////////////////////////////////////////////////////////////////
54 2 dgisselq
`define WBQSPI_RESET            0
55 4 dgisselq
`define WBQSPI_RESET_QUADMODE   1
56 2 dgisselq
`define WBQSPI_IDLE             2
57
`define WBQSPI_RDIDLE           3       // Idle, but in fast read mode
58
`define WBQSPI_WBDECODE         4
59
`define WBQSPI_WAIT_WIP_CLEAR   5
60
`define WBQSPI_CHECK_WIP_CLEAR  6
61
`define WBQSPI_CHECK_WIP_DONE   7
62
`define WBQSPI_WEN              8
63
`define WBQSPI_PP               9       // Program page
64
`define WBQSPI_QPP              10      // Program page, 4 bit mode
65
`define WBQSPI_WR_DATA          11
66
`define WBQSPI_WR_BUS_CYCLE     12
67
`define WBQSPI_RD_DUMMY         13
68
`define WBQSPI_QRD_ADDRESS      14
69
`define WBQSPI_QRD_DUMMY        15
70
`define WBQSPI_READ_CMD         16
71
`define WBQSPI_READ_DATA        17
72
`define WBQSPI_WAIT_TIL_RDIDLE  18
73
`define WBQSPI_READ_ID_CMD      19
74
`define WBQSPI_READ_ID          20
75
`define WBQSPI_READ_STATUS      21
76
`define WBQSPI_READ_CONFIG      22
77
`define WBQSPI_WRITE_STATUS     23
78
`define WBQSPI_WRITE_CONFIG     24
79
`define WBQSPI_ERASE_WEN        25
80
`define WBQSPI_ERASE_CMD        26
81
`define WBQSPI_ERASE_BLOCK      27
82
`define WBQSPI_CLEAR_STATUS     28
83
`define WBQSPI_IDLE_CHECK_WIP   29
84
`define WBQSPI_WAIT_TIL_IDLE    30
85
 
86
module  wbqspiflash(i_clk_100mhz,
87
                // Internal wishbone connections
88
                i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,
89
                i_wb_addr, i_wb_data,
90
                // Wishbone return values
91
                o_wb_ack, o_wb_stall, o_wb_data,
92
                // Quad Spi connections to the external device
93
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
94 3 dgisselq
                o_interrupt);
95 2 dgisselq
        input                   i_clk_100mhz;
96
        // Wishbone, inputs first
97
        input                   i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
98
        input           [19:0]   i_wb_addr;
99
        input           [31:0]   i_wb_data;
100
        // then outputs
101
        output  reg             o_wb_ack;
102
        output  reg             o_wb_stall;
103
        output  reg     [31:0]   o_wb_data;
104
        // Quad SPI control wires
105
        output  wire            o_qspi_sck, o_qspi_cs_n;
106
        output  wire    [1:0]    o_qspi_mod;
107
        output  wire    [3:0]    o_qspi_dat;
108
        input           [3:0]    i_qspi_dat;
109
        // Interrupt line
110
        output  reg             o_interrupt;
111
 
112
        reg             spi_wr, spi_hold, spi_spd, spi_dir;
113
        reg     [31:0]   spi_in;
114
        reg     [1:0]    spi_len;
115
        wire    [31:0]   spi_out;
116
        wire            spi_valid, spi_busy;
117 4 dgisselq
        wire            w_qspi_sck, w_qspi_cs_n;
118
        wire    [3:0]    w_qspi_dat;
119
        wire    [1:0]    w_qspi_mod;
120 2 dgisselq
        llqspi  lldriver(i_clk_100mhz,
121
                        spi_wr, spi_hold, spi_in, spi_len, spi_spd, spi_dir,
122
                                spi_out, spi_valid, spi_busy,
123 4 dgisselq
                        w_qspi_sck, w_qspi_cs_n, w_qspi_mod, w_qspi_dat,
124 3 dgisselq
                                i_qspi_dat);
125 2 dgisselq
 
126
        // Erase status tracking
127
        reg             write_in_progress, write_protect;
128
        reg     [5:0]    erased_sector;
129
        reg             dirty_sector;
130
        initial begin
131
                write_in_progress = 1'b0;
132
                erased_sector = 6'h00;
133
                dirty_sector  = 1'b1;
134
                write_protect = 1'b1;
135
        end
136
 
137
        reg     [7:0]    last_status;
138
        reg             quad_mode_enabled;
139 4 dgisselq
        reg             spif_cmd, spif_override;
140 2 dgisselq
        reg     [19:0]   spif_addr;
141
        reg     [31:0]   spif_data;
142
        reg     [5:0]    state;
143
        reg             spif_ctrl, spif_req;
144
        wire    [5:0]    spif_sector;
145
        assign  spif_sector = spif_addr[19:14];
146
 
147
        initial state = `WBQSPI_RESET;
148
        initial o_wb_ack   = 1'b0;
149
        initial o_wb_stall = 1'b1;
150
        initial spi_wr     = 1'b0;
151
        initial spi_len    = 2'b00;
152
        initial quad_mode_enabled = 1'b0;
153
        initial o_interrupt = 1'b0;
154
        always @(posedge i_clk_100mhz)
155 4 dgisselq
        begin
156
        spif_override <= 1'b0;
157 2 dgisselq
        if (state == `WBQSPI_RESET)
158
        begin
159
                // From a reset, we should
160
                //      Enable the Quad I/O mode
161
                //      Disable the Write protection bits in the status register
162
                //      Chip should already be up and running, so we can start
163
                //      immediately ....
164
                o_wb_ack <= 1'b0;
165
                o_wb_stall <= 1'b1;
166 4 dgisselq
                spi_wr   <= 1'b0;
167 2 dgisselq
                spi_hold <= 1'b0;
168
                spi_spd  <= 1'b0;
169
                spi_dir  <= 1'b0;
170
                last_status <= 8'h00;
171 4 dgisselq
                state <= `WBQSPI_RESET_QUADMODE;
172 2 dgisselq
                spif_req <= 1'b0;
173 4 dgisselq
                spif_override <= 1'b1;
174
                last_status <= 8'hfc; //
175
                        // This guarantees that we aren't starting in quad
176
                        // I/O mode, where the FPGA configuration scripts may
177
                        // have left us.
178
        end else if (state == `WBQSPI_RESET_QUADMODE)
179 2 dgisselq
        begin
180 4 dgisselq
                // Okay, so here's the problem: we don't know whether or not
181
                // the Xilinx loader started us up in Quad Read I/O idle mode.
182
                // So, thus we need to 
183
                // Not ready to handle the bus yet, so stall any requests
184
                o_wb_ack   <= 1'b0;
185
                o_wb_stall <= 1'b1;
186
 
187
                // Do something ...
188
                if (last_status == 8'h00)
189 2 dgisselq
                begin
190 4 dgisselq
                        spif_override <= 1'b0;
191
                        state <= `WBQSPI_IDLE;
192
                end else begin
193
                        last_status <= last_status - 8'h1;
194
                        spif_override <= 1'b1;
195
                        spif_cmd  <= last_status[3]; // Toggle CS_n
196
                        spif_ctrl <= last_status[0]; // Toggle clock too
197 2 dgisselq
                end
198
        end else if (state == `WBQSPI_IDLE)
199
        begin
200
                o_interrupt <= 1'b0;
201
                o_wb_stall <= 1'b0;
202
                o_wb_ack <= 1'b0;
203
                spif_cmd   <= i_wb_we;
204
                spif_addr  <= i_wb_addr;
205
                spif_data  <= i_wb_data;
206
                spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
207
                spif_req   <= (i_wb_ctrl_stb)||(i_wb_data_stb);
208
                spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
209
                spi_hold <= 1'b0;
210
                spi_spd  <= 1'b0;
211
                spi_dir <= 1'b0; // Write (for now, 'cause of cmd)
212
                // Data register access
213
                if ((i_wb_data_stb)&&(i_wb_cyc))
214
                begin
215
 
216
                        if (i_wb_we) // Request to write a page
217
                        begin
218
                                if((~write_protect)&&(~write_in_progress))
219
                                begin // 00
220
                                        spi_wr <= 1'b1;
221
                                        spi_len <= 2'b00; // 8 bits
222
                                        // Send a write enable command
223
                                        spi_in <= { 8'h06, 24'h00 };
224
                                        state <= `WBQSPI_WEN;
225
 
226
                                        o_wb_ack <= 1'b0;
227
                                        o_wb_stall <= 1'b1;
228
                                end else if (write_protect)
229
                                begin // whether or not write-in_progress ...
230
                                        // Do nothing on a write protect
231
                                        // violation
232
                                        //
233
                                        o_wb_ack <= 1'b1;
234
                                        o_wb_stall <= 1'b0;
235
                                end else begin // write is in progress, wait
236
                                        // for it to complete
237
                                        state <= `WBQSPI_WAIT_WIP_CLEAR;
238
                                        o_wb_ack <= 1'b0;
239
                                        o_wb_stall <= 1'b1;
240
                                end
241
                        end else if (~write_in_progress)
242
                        begin // Read access, normal mode(s)
243
                                o_wb_ack   <= 1'b0;
244
                                o_wb_stall <= 1'b1;
245
                                spi_wr     <= 1'b1;     // Write cmd to device
246
                                if (quad_mode_enabled)
247
                                begin
248
                                        spi_in <= { 8'heb, 2'b00, i_wb_addr[19:0], 2'b00 };
249
                                        state <= `WBQSPI_QRD_ADDRESS;
250
                                        spi_len    <= 2'b00; // single byte, cmd only
251
                                end else begin
252
                                        spi_in <= { 8'h0b, 2'b00, i_wb_addr[19:0], 2'b00 };
253
                                        state <= `WBQSPI_RD_DUMMY;
254
                                        spi_len    <= 2'b11; // cmd+addr,32bits
255
                                end
256
                        end else begin
257
                                // A write is in progress ... need to stall
258
                                // the bus until the write is complete.
259
                                state <= `WBQSPI_WAIT_WIP_CLEAR;
260
                                o_wb_ack   <= 1'b0;
261
                                o_wb_stall <= 1'b1;
262
                        end
263
                end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)&&(i_wb_we))
264
                begin
265
                        o_wb_stall <= 1'b1;
266
                        case(i_wb_addr[1:0])
267
                        2'b00: begin // Erase command register
268
                                write_protect <= ~i_wb_data[28];
269
                                o_wb_stall <= 1'b0;
270
 
271
                                if((i_wb_data[31])&&(~write_in_progress))
272
                                begin
273
                                        // Command an erase--ack it immediately
274
 
275
                                        o_wb_ack <= 1'b1;
276
                                        o_wb_stall <= 1'b0;
277
 
278
                                        if ((i_wb_data[31])&&(~write_protect))
279
                                        begin
280
                                                spi_wr <= 1'b1;
281
                                                spi_len <= 2'b00;
282
                                                // Send a write enable command
283
                                                spi_in <= { 8'h06, 24'h00 };
284
                                                state <= `WBQSPI_ERASE_CMD;
285
                                                o_wb_stall <= 1'b1;
286
                                        end
287
                                end else if (i_wb_data[31])
288
                                begin
289
                                        state <= `WBQSPI_WAIT_WIP_CLEAR;
290
                                        o_wb_ack   <= 1'b1;
291
                                        o_wb_stall <= 1'b1;
292
                                end else
293
                                        o_wb_ack   <= 1'b1;
294
                                        o_wb_stall <= 1'b0;
295
                                end
296
                        2'b01: begin
297
                                // Write the configuration register
298
                                o_wb_ack <= 1'b1;
299
                                o_wb_stall <= 1'b1;
300
 
301
                                // Need to send a write enable command first
302
                                spi_wr <= 1'b1;
303
                                spi_len <= 2'b00; // 8 bits
304
                                // Send a write enable command
305
                                spi_in <= { 8'h06, 24'h00 };
306
                                state <= `WBQSPI_WRITE_CONFIG;
307
                                end
308
                        2'b10: begin
309
                                // Write the status register
310
                                o_wb_ack <= 1'b1; // Ack immediately
311
                                o_wb_stall <= 1'b1; // Stall other cmds
312
                                // Need to send a write enable command first
313
                                spi_wr <= 1'b1;
314
                                spi_len <= 2'b00; // 8 bits
315
                                // Send a write enable command
316
                                spi_in <= { 8'h06, 24'h00 };
317
                                state <= `WBQSPI_WRITE_STATUS;
318
                                end
319
                        2'b11: begin // Write the ID register??? makes no sense
320
                                o_wb_ack <= 1'b1;
321
                                o_wb_stall <= 1'b0;
322
                                end
323
                        endcase
324
                end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)) // &&(~i_wb_we))
325
                begin
326
                        case(i_wb_addr[1:0])
327
                        2'b00: begin // Read local register
328
                                if (write_in_progress) // Read status
329
                                begin// register, is write still in progress?
330
                                        state <= `WBQSPI_READ_STATUS;
331
                                        spi_wr <= 1'b1;
332
                                        spi_len <= 2'b01;// 8 bits out, 8 bits in
333
                                        spi_in <= { 8'h05, 24'h00};
334
 
335
                                        o_wb_ack <= 1'b0;
336
                                        o_wb_stall <= 1'b1;
337
                                end else begin // Return w/o talking to device
338
                                        o_wb_ack <= 1'b1;
339
                                        o_wb_stall <= 1'b0;
340
                                        o_wb_data <= { write_in_progress,
341
                                                dirty_sector, spi_busy,
342
                                                ~write_protect,
343
                                                quad_mode_enabled,
344
                                                7'h00,
345
                                                erased_sector, 14'h000 };
346
                                end end
347
                        2'b01: begin // Read configuration register
348
                                state <= `WBQSPI_READ_CONFIG;
349
                                spi_wr <= 1'b1;
350
                                spi_len <= 2'b01;
351
                                spi_in <= { 8'h35, 24'h00};
352
 
353
                                o_wb_ack <= 1'b0;
354
                                o_wb_stall <= 1'b1;
355
                                end
356
                        2'b10: begin // Read status register
357
                                state <= `WBQSPI_READ_STATUS;
358
                                spi_wr <= 1'b1;
359
                                spi_len <= 2'b01; // 8 bits out, 8 bits in
360
                                spi_in <= { 8'h05, 24'h00};
361
 
362
                                o_wb_ack <= 1'b0;
363
                                o_wb_stall <= 1'b1;
364
                                end
365
                        2'b11: begin // Read ID register
366
                                state <= `WBQSPI_READ_ID_CMD;
367
                                spi_wr <= 1'b1;
368
                                spi_len <= 2'b00;
369
                                spi_in <= { 8'h9f, 24'h00};
370
 
371
                                o_wb_ack <= 1'b0;
372
                                o_wb_stall <= 1'b1;
373
                                end
374
                        endcase
375
                end else if ((~i_wb_cyc)&&(write_in_progress))
376
                begin
377
                        state <= `WBQSPI_IDLE_CHECK_WIP;
378
                        spi_wr <= 1'b1;
379
                        spi_len <= 2'b01; // 8 bits out, 8 bits in
380
                        spi_in <= { 8'h05, 24'h00};
381
 
382
                        o_wb_ack <= 1'b0;
383
                        o_wb_stall <= 1'b1;
384
                end
385
        end else if (state == `WBQSPI_RDIDLE)
386
        begin
387
                spi_wr <= 1'b0;
388
                o_wb_stall <= 1'b0;
389
                o_wb_ack <= 1'b0;
390
                spif_cmd   <= i_wb_we;
391
                spif_addr  <= i_wb_addr;
392
                spif_data  <= i_wb_data;
393
                spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
394
                spif_req   <= (i_wb_ctrl_stb)||(i_wb_data_stb);
395
                spi_hold <= 1'b0;
396
                spi_spd<= 1'b1;
397
                spi_dir <= 1'b0; // Write (for now)
398
                if ((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we))
399
                begin // Continue our read ... send the new address / mode
400
                        o_wb_stall <= 1'b1;
401
                        spi_wr <= 1'b1;
402 4 dgisselq
                        spi_len <= 2'b10; // Write address, but not mode byte
403 2 dgisselq
                        spi_in <= { 2'h0, i_wb_addr[19:0], 2'h0, 8'ha0 };
404
                        state <= `WBQSPI_QRD_DUMMY;
405
                end else if((i_wb_cyc)&&(i_wb_ctrl_stb)&&(~i_wb_we)&&(i_wb_addr[1:0] == 2'b00))
406
                begin
407
                        // A local read that doesn't touch the device, so leave
408
                        // the device in its current state
409
                        o_wb_stall <= 1'b0;
410
                        o_wb_ack <= 1'b1;
411
                        o_wb_data <= { write_in_progress,
412
                                        dirty_sector, spi_busy,
413
                                        ~write_protect,
414
                                        quad_mode_enabled,
415
                                        7'h00,
416
                                        erased_sector, 14'h000 };
417
                end else if((i_wb_cyc)&&((i_wb_ctrl_stb)||(i_wb_data_stb)))
418
                begin // Need to release the device from quad mode for all else
419
                        o_wb_ack   <= 1'b0;
420
                        o_wb_stall <= 1'b1;
421
                        spi_wr <= 1'b1;
422
                        spi_len <= 2'b11;
423
                        spi_in <= 32'h00;
424
                        state <= `WBQSPI_WBDECODE;
425
                end
426
        end else if (state == `WBQSPI_WBDECODE)
427
        begin
428
                // We were in quad SPI read mode, and had to get out.
429
                // Now we've got a command (not data read) to read and
430
                // execute.  Accomplish what we would've done while in the
431
                // IDLE state here, save only that we don't have to worry
432
                // about data reads, and we need to operate on a stored
433
                // version of the bus command
434
                o_wb_stall <= 1'b1;
435
                o_wb_ack <= 1'b0;
436
                spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
437
                spi_hold <= 1'b0;
438
                spi_spd <= 1'b0;
439
                spi_dir <= 1'b0;
440
                spif_req<= (spif_req) && (i_wb_cyc);
441
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // only in full idle ...
442
                begin
443
                        // Data register access
444
                        if (~spif_ctrl)
445
                        begin
446
                                if (spif_cmd) // Request to write a page
447
                                begin
448
                                        if((~write_protect)&&(~write_in_progress))
449
                                        begin // 00
450
                                                spi_wr <= 1'b1;
451
                                                spi_len <= 2'b00; // 8 bits
452
                                                // Send a write enable command
453
                                                spi_in <= { 8'h06, 24'h00 };
454
                                                state <= `WBQSPI_WEN;
455
 
456
                                                o_wb_ack <= 1'b0;
457
                                                o_wb_stall <= 1'b1;
458
                                        end else if (write_protect)
459
                                        begin // whether or not write-in_progress ...
460
                                                // Do nothing on a write protect
461
                                                // violation
462
                                                //
463
                                                o_wb_ack <= spif_req;
464
                                                o_wb_stall <= 1'b0;
465
                                                state <= `WBQSPI_IDLE;
466
                                        end else begin // write is in progress, wait
467
                                                // for it to complete
468
                                                state <= `WBQSPI_WAIT_WIP_CLEAR;
469
                                                o_wb_ack <= 1'b0;
470
                                                o_wb_stall <= 1'b1;
471
                                        end
472
                                // end else if (~write_in_progress) // always true
473
                                // but ... we wouldn't get here on a normal read access
474
                                end else begin
475
                                        // Something's wrong, we should never get here
476
                                        // Attempt to go to idle to recover
477
                                        state <= `WBQSPI_IDLE;
478
                                end
479
                        end else if ((spif_ctrl)&&(spif_cmd))
480
                        begin
481
                                o_wb_stall <= 1'b1;
482
                                case(spif_addr[1:0])
483
                                2'b00: begin // Erase command register
484
                                        o_wb_ack   <= spif_req;
485
                                        o_wb_stall <= 1'b0;
486
                                        state <= `WBQSPI_IDLE;
487
                                        write_protect <= ~spif_data[28];
488
                                        // Are we commanding an erase?
489
                                        // We're in read mode, writes cannot
490
                                        // be in progress, so ...
491
                                        if (spif_data[31]) // Command an erase
492
                                        begin
493
                                                // Since we're not going back
494
                                                // to IDLE, we must stall the
495
                                                // bus here
496
                                                o_wb_stall <= 1'b1;
497
                                                spi_wr <= 1'b1;
498
                                                spi_len <= 2'b00;
499
                                                // Send a write enable command
500
                                                spi_in <= { 8'h06, 24'h00 };
501
                                                state <= `WBQSPI_ERASE_CMD;
502
                                        end end
503
                                2'b01: begin
504
                                        // Write the configuration register
505
                                        o_wb_ack <= spif_req;
506
                                        o_wb_stall <= 1'b1;
507
 
508
                                        // Need to send a write enable command first
509
                                        spi_wr <= 1'b1;
510
                                        spi_len <= 2'b00; // 8 bits
511
                                        // Send a write enable command
512
                                        spi_in <= { 8'h06, 24'h00 };
513
                                        state <= `WBQSPI_WRITE_CONFIG;
514
                                        end
515
                                2'b10: begin
516
                                        // Write the status register
517
                                        o_wb_ack <= spif_req; // Ack immediately
518
                                        o_wb_stall <= 1'b1; // Stall other cmds
519
                                        // Need to send a write enable command first
520
                                        spi_wr <= 1'b1;
521
                                        spi_len <= 2'b00; // 8 bits
522
                                        // Send a write enable command
523
                                        spi_in <= { 8'h06, 24'h00 };
524
                                        state <= `WBQSPI_WRITE_STATUS;
525
                                        end
526
                                2'b11: begin // Write the ID register??? makes no sense
527
                                        o_wb_ack <= spif_req;
528
                                        o_wb_stall <= 1'b0;
529
                                        state <= `WBQSPI_IDLE;
530
                                        end
531
                                endcase
532
                        end else begin // on (~spif_we)
533
                                case(spif_addr[1:0])
534
                                2'b00: begin // Read local register
535
                                        // Nonsense case--would've done this
536
                                        // already
537
                                        state <= `WBQSPI_IDLE;
538
                                        o_wb_ack <= spif_req;
539
                                        o_wb_stall <= 1'b0;
540
                                        end
541
                                2'b01: begin // Read configuration register
542
                                        state <= `WBQSPI_READ_CONFIG;
543
                                        spi_wr <= 1'b1;
544
                                        spi_len <= 2'b01;
545
                                        spi_in <= { 8'h35, 24'h00};
546
 
547
                                        o_wb_ack <= 1'b0;
548
                                        o_wb_stall <= 1'b1;
549
                                        end
550
                                2'b10: begin // Read status register
551
                                        state <= `WBQSPI_READ_STATUS;
552
                                        spi_wr <= 1'b1;
553
                                        spi_len <= 2'b01; // 8 bits out, 8 bits in
554
                                        spi_in <= { 8'h05, 24'h00};
555
 
556
                                        o_wb_ack <= 1'b0;
557
                                        o_wb_stall <= 1'b1;
558
                                        end
559
                                2'b11: begin // Read ID register
560
                                        state <= `WBQSPI_READ_ID_CMD;
561
                                        spi_wr <= 1'b1;
562
                                        spi_len <= 2'b00;
563
                                        spi_in <= { 8'h9f, 24'h00};
564
 
565
                                        o_wb_ack <= 1'b0;
566
                                        o_wb_stall <= 1'b1;
567
                                        end
568
                                endcase
569
                        end
570
                end
571
        end else if (state == `WBQSPI_WAIT_WIP_CLEAR)
572
        begin
573
                o_wb_stall <= 1'b1;
574
                o_wb_ack   <= 1'b0;
575
                spi_wr <= 1'b0;
576
                spif_req<= (spif_req) && (i_wb_cyc);
577
                if (~spi_busy)
578
                begin
579
                        spi_wr   <= 1'b1;
580
                        spi_in   <= { 8'h05, 24'h0000 };
581
                        spi_hold <= 1'b1;
582
                        spi_len  <= 2'b01; // 16 bits write, so we can read 8
583
                        state <= `WBQSPI_CHECK_WIP_CLEAR;
584
                        spi_spd  <= 1'b0; // Slow speed
585
                        spi_dir  <= 1'b0;
586
                end
587
        end else if (state == `WBQSPI_CHECK_WIP_CLEAR)
588
        begin
589
                o_wb_stall <= 1'b1;
590
                o_wb_ack   <= 1'b0;
591
                // Repeat as often as necessary until we are clear
592
                spi_wr <= 1'b1;
593
                spi_in <= 32'h0000; // Values here are actually irrelevant
594
                spi_hold <= 1'b1;
595
                spi_len <= 2'b00; // One byte at a time
596
                spi_spd  <= 1'b0; // Slow speed
597
                spi_dir  <= 1'b0;
598
                spif_req<= (spif_req) && (i_wb_cyc);
599
                if ((spi_valid)&&(~spi_out[0]))
600
                begin
601
                        state <= `WBQSPI_CHECK_WIP_DONE;
602
                        spi_wr   <= 1'b0;
603
                        spi_hold <= 1'b0;
604
                        write_in_progress <= 1'b0;
605
                        last_status <= spi_out[7:0];
606
                end
607
        end else if (state == `WBQSPI_CHECK_WIP_DONE)
608
        begin
609
                o_wb_stall <= 1'b1;
610
                o_wb_ack   <= 1'b0;
611
                // Let's let the SPI port come back to a full idle,
612
                // and the chip select line go low before continuing
613
                spi_wr   <= 1'b0;
614
                spi_len  <= 2'b00;
615
                spi_hold <= 1'b0;
616
                spi_spd  <= 1'b0; // Slow speed
617
                spi_dir  <= 1'b0;
618
                spif_req<= (spif_req) && (i_wb_cyc);
619
                if ((o_qspi_cs_n)&&(~spi_busy)) // Chip select line is high, we can continue
620
                begin
621
                        spi_wr   <= 1'b0;
622
                        spi_hold <= 1'b0;
623
 
624
                        casez({ spif_cmd, spif_ctrl, spif_addr[1:0] })
625
                        4'b00??: begin // Read data from ... somewhere
626
                                spi_wr     <= 1'b1;     // Write cmd to device
627
                                if (quad_mode_enabled)
628
                                begin
629
                                        spi_in <= { 8'heb, 2'b00, spif_addr[19:0], 2'b00 };
630 4 dgisselq
                                        state <= `WBQSPI_QRD_ADDRESS;
631
                                        // spi_len    <= 2'b00; // single byte, cmd only
632 2 dgisselq
                                end else begin
633
                                        spi_in <= { 8'h0b, 2'b00, spif_addr[19:0], 2'b00 };
634
                                        state <= `WBQSPI_RD_DUMMY;
635 4 dgisselq
                                        spi_len    <= 2'b11; // Send cmd and addr
636 2 dgisselq
                                end end
637
                        4'b10??: begin // Write data to ... anywhere
638
                                spi_wr <= 1'b1;
639
                                spi_len <= 2'b00; // 8 bits
640
                                // Send a write enable command
641
                                spi_in <= { 8'h06, 24'h00 };
642
                                state <= `WBQSPI_WEN;
643
                                end
644
                        4'b0110: begin // Read status register
645
                                state <= `WBQSPI_READ_STATUS;
646
                                spi_wr <= 1'b1;
647
                                spi_len <= 2'b01; // 8 bits out, 8 bits in
648
                                spi_in <= { 8'h05, 24'h00};
649
                                end
650
                        4'b0111: begin
651
                                state <= `WBQSPI_READ_ID_CMD;
652
                                spi_wr <= 1'b1;
653
                                spi_len <= 2'b00;
654
                                spi_in <= { 8'h9f, 24'h00};
655
                                end
656
                        default: begin //
657
                                o_wb_stall <= 1'b1;
658
                                o_wb_ack <= spif_req;
659
                                state <= `WBQSPI_WAIT_TIL_IDLE;
660
                                end
661
                        endcase
662
                // spif_cmd   <= i_wb_we;
663
                // spif_addr  <= i_wb_addr;
664
                // spif_data  <= i_wb_data;
665
                // spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
666
                // spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
667
                end
668
        end else if (state == `WBQSPI_WEN)
669
        begin // We came here after issuing a write enable command
670
                spi_wr <= 1'b0;
671
                o_wb_ack <= 1'b0;
672
                o_wb_stall <= 1'b1;
673
                spif_req<= (spif_req) && (i_wb_cyc);
674
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Let's come to a full stop
675 4 dgisselq
                        state <= (quad_mode_enabled)?`WBQSPI_QPP:`WBQSPI_PP;
676
                        // state <= `WBQSPI_PP;
677 2 dgisselq
        end else if (state == `WBQSPI_PP)
678
        begin // We come here under a full stop / full port idle mode
679
                // Issue our command immediately
680
                spi_wr <= 1'b1;
681
                spi_in <= { 8'h02, 2'h0, spif_addr, 2'b00 };
682
                spi_len <= 2'b11;
683
                spi_hold <= 1'b1;
684
                spi_spd  <= 1'b0;
685
                spi_dir  <= 1'b0; // Writing
686
                spif_req<= (spif_req) && (i_wb_cyc);
687
 
688
                // Once we get busy, move on
689
                if (spi_busy)
690
                        state <= `WBQSPI_WR_DATA;
691
                if (spif_sector == erased_sector)
692
                        dirty_sector <= 1'b1;
693
        end else if (state == `WBQSPI_QPP)
694
        begin // We come here under a full stop / full port idle mode
695
                // Issue our command immediately
696
                spi_wr <= 1'b1;
697
                spi_in <= { 8'h32, 2'h0, spif_addr, 2'b00 };
698
                spi_len <= 2'b11;
699
                spi_hold <= 1'b1;
700
                spi_spd  <= 1'b0;
701
                spi_dir  <= 1'b0; // Writing
702
                spif_req<= (spif_req) && (i_wb_cyc);
703
 
704
                // Once we get busy, move on
705
                if (spi_busy)
706
                begin
707
                        // spi_wr is irrelevant here ...
708
                        // Set the speed value once, but wait til we get busy
709
                        // to do so.
710
                        spi_spd <= 1'b1;
711
                        state <= `WBQSPI_WR_DATA;
712
                end
713
                if (spif_sector == erased_sector)
714
                        dirty_sector <= 1'b1;
715
        end else if (state == `WBQSPI_WR_DATA)
716
        begin
717
                o_wb_stall <= 1'b1;
718
                o_wb_ack   <= 1'b0;
719
                spi_wr   <= 1'b1; // write without waiting
720
                spi_in   <= {
721
                        spif_data[ 7: 0],
722
                        spif_data[15: 8],
723
                        spif_data[23:16],
724
                        spif_data[31:24] };
725
                spi_len  <= 2'b11; // Write 4 bytes
726
                spi_hold <= 1'b1;
727
                if (~spi_busy)
728
                begin
729
                        o_wb_ack <= spif_req; // Ack when command given
730
                        state <= `WBQSPI_WR_BUS_CYCLE;
731
                end
732
                spif_req<= (spif_req) && (i_wb_cyc);
733
        end else if (state == `WBQSPI_WR_BUS_CYCLE)
734
        begin
735
                o_wb_ack <= 1'b0; // Turn off our ack and stall flags
736
                o_wb_stall <= 1'b1;
737
                spi_wr <= 1'b0;
738
                spi_hold <= 1'b1;
739
                write_in_progress <= 1'b1;
740
                spif_req<= (spif_req) && (i_wb_cyc);
741
                if (~i_wb_cyc)
742
                begin
743
                        state <= `WBQSPI_WAIT_TIL_IDLE;
744
                        spi_hold <= 1'b0;
745
                end else if (spi_wr)
746
                begin // Give the SPI a chance to get busy on the last write
747
                        // Do nothing here.
748
                end else if ((i_wb_data_stb)&&(i_wb_we)
749
                                &&(i_wb_addr == (spif_addr+1))
750
                                &&(i_wb_addr[19:6]==spif_addr[19:6]))
751
                begin
752
                        spif_cmd  <= 1'b1;
753
                        spif_data <= i_wb_data;
754
                        spif_addr <= i_wb_addr;
755
                        spif_ctrl  <= 1'b0;
756
                        spif_req<= 1'b1;
757
                        // We'll keep the bus stalled on this request
758
                        // for a while
759
                        state <= `WBQSPI_WR_DATA;
760
                        o_wb_ack   <= 1'b0;
761
                        o_wb_stall <= 1'b0;
762
                end else if ((i_wb_data_stb|i_wb_ctrl_stb)&&(~o_wb_ack)) // Writing out of bounds
763
                begin
764
                        spi_hold <= 1'b0;
765
                        spi_wr   <= 1'b0;
766
                        state <= `WBQSPI_WAIT_TIL_IDLE;
767
                end // Otherwise we stay here
768
        end else if (state == `WBQSPI_RD_DUMMY)
769
        begin
770
                o_wb_ack   <= 1'b0;
771
                o_wb_stall <= 1'b1;
772
 
773
                spi_wr <= 1'b1; // Non-stop
774
                // Need to read one byte of dummy data,
775
                // just to consume 8 clocks
776
                spi_in <= { 8'h00, 24'h00 };
777
                spi_len <= 2'b00; // Read 8 bits
778
                spi_spd <= 1'b0;
779
                spi_hold <= 1'b0;
780
                spif_req<= (spif_req) && (i_wb_cyc);
781
 
782
                if ((~spi_busy)&&(~o_qspi_cs_n))
783
                        // Our command was accepted
784
                        state <= `WBQSPI_READ_CMD;
785
        end else if (state == `WBQSPI_QRD_ADDRESS)
786
        begin
787
                // We come in here immediately upon issuing a QRD read
788
                // command (8-bits), but we have to pause to give the
789
                // address (24-bits) and mode (8-bits) in quad speed.
790
                o_wb_ack   <= 1'b0;
791
                o_wb_stall <= 1'b1;
792
 
793
                spi_wr <= 1'b1; // Non-stop
794
                spi_in <= { 2'b0, spif_addr, 2'b0, 8'ha0 };
795 4 dgisselq
                spi_len <= 2'b10; // Write address, not mode byte
796 2 dgisselq
                spi_spd <= 1'b1;
797
                spi_dir <= 1'b0; // Still writing
798
                spi_hold <= 1'b0;
799
                spif_req<= (spif_req) && (i_wb_cyc);
800
 
801
                if ((~spi_busy)&&(spi_spd))
802
                        // Our command was accepted
803
                        state <= `WBQSPI_QRD_DUMMY;
804
        end else if (state == `WBQSPI_QRD_DUMMY)
805
        begin
806
                o_wb_ack   <= 1'b0;
807
                o_wb_stall <= 1'b1;
808
 
809
                spi_wr <= 1'b1; // Non-stop
810
                spi_in <= { 8'ha0, 24'h00 }; // Mode byte, then 2 bytes dummy
811
                spi_len <= 2'b10; // Write 8 bits
812
                spi_spd <= 1'b1;
813
                spi_dir <= 1'b0; // Still writing
814
                spi_hold <= 1'b0;
815
                spif_req<= (spif_req) && (i_wb_cyc);
816
 
817
                if ((~spi_busy)&&(spi_in[31:28] == 4'ha))
818
                        // Our command was accepted
819
                        state <= `WBQSPI_READ_CMD;
820
        end else if (state == `WBQSPI_READ_CMD)
821
        begin // Issue our first command to read 32 bits.
822
                o_wb_ack   <= 1'b0;
823
                o_wb_stall <= 1'b1;
824
 
825
                spi_wr <= 1'b1;
826
                spi_in <= { 8'hff, 24'h00 }; // Empty
827
                spi_len <= 2'b11; // Read 32 bits
828
                spi_dir <= 1'b1; // Now reading
829
                spi_hold <= 1'b0;
830
                spif_req<= (spif_req) && (i_wb_cyc);
831
                if ((spi_valid)&&(spi_len == 2'b11))
832
                        state <= `WBQSPI_READ_DATA;
833
        end else if (state == `WBQSPI_READ_DATA)
834
        begin
835
                // Pipelined read support
836
                spi_wr <=((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we)&&(i_wb_addr== (spif_addr+1)));
837
                spi_in <= 32'h00;
838
                spi_len <= 2'b11;
839
                // Don't adjust the speed here, it was set in the setup
840 4 dgisselq
                spi_dir <= 1'b1;        // Now we get to read
841
                // Don't let the device go to idle until the bus cycle ends.
842
                //      This actually prevents a *really* nasty race condition,
843
                //      where the strobe comes in after the lower level device
844
                //      has decided to stop waiting.  The write is then issued,
845
                //      but no one is listening.  By leaving the device open,
846
                //      the device is kept in a state where a valid strobe
847
                //      here will be useful.  Of course, we don't accept
848
                //      all commands, just reads.  Further, the strobe needs
849
                //      to be high for two clocks cycles without changing
850
                //      anything on the bus--one for us to notice it and pull
851
                //      our head out of the sand, and a second for whoever
852
                //      owns the bus to realize their command went through.
853
                spi_hold <= 1'b1;
854 2 dgisselq
                spif_req<= (spif_req) && (i_wb_cyc);
855
                if ((spi_valid)&&(~spi_in[31]))
856
                begin // Single pulse acknowledge and write data out
857
                        o_wb_ack <= spif_req;
858
                        o_wb_stall <= (~spi_wr);
859
                        // adjust endian-ness to match the PC
860
                        o_wb_data <= { spi_out[7:0], spi_out[15:8],
861
                                spi_out[23:16], spi_out[31:24] };
862
                        state <= (spi_wr)?`WBQSPI_READ_DATA
863
                                : ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
864
                        spif_req <= spi_wr;
865 4 dgisselq
                        spi_hold <= (~spi_wr);
866 2 dgisselq
                        if (spi_wr)
867
                                spif_addr <= i_wb_addr;
868 4 dgisselq
                end else if (~i_wb_cyc)
869
                begin // FAIL SAFE: If the bus cycle ends, forget why we're
870
                        // here, just go back to idle
871
                        state <= ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
872
                        spi_hold <= 1'b0;
873
                        o_wb_ack <= 1'b0;
874
                        o_wb_stall <= 1'b1;
875 2 dgisselq
                end else begin
876
                        o_wb_ack <= 1'b0;
877
                        o_wb_stall <= 1'b1;
878
                end
879
        end else if (state == `WBQSPI_WAIT_TIL_RDIDLE)
880
        begin // Wait 'til idle, but then go to fast read idle instead of full
881
                spi_wr     <= 1'b0;     // idle
882
                spi_hold   <= 1'b0;
883
                o_wb_stall <= 1'b1;
884
                o_wb_ack   <= 1'b0;
885
                spif_req   <= 1'b0;
886
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
887
                begin // clearing of the SPI port before moving on
888
                        state <= `WBQSPI_RDIDLE;
889
                        o_wb_stall <= 1'b0;
890
                        o_wb_ack   <= 1'b0;// Shouldn't be acking anything here
891
                end
892
        end else if (state == `WBQSPI_READ_ID_CMD)
893
        begin // We came into here immediately after issuing a 0x9f command
894
                // Now we need to read 32 bits of data.  Result should be
895
                // 0x0102154d (8'h manufacture ID, 16'h device ID, followed
896
                // by the number of extended bytes available 8'h4d).
897
                o_wb_ack <= 1'b0;
898
                o_wb_stall<= 1'b1;
899
 
900
                spi_wr <= 1'b1; // No data to send, but need four bytes, since
901
                spi_len <= 2'b11; // 32 bits of data are ... useful
902
                spi_in <= 32'h00; // Irrelevant
903
                spi_spd <= 1'b0; // Slow speed
904
                spi_dir <= 1'b1; // Reading
905
                spi_hold <= 1'b0;
906
                spif_req <= (spif_req) && (i_wb_cyc);
907
                if ((~spi_busy)&&(~o_qspi_cs_n)&&(spi_len == 2'b11))
908
                        // Our command was accepted, now go read the result
909
                        state <= `WBQSPI_READ_ID;
910
        end else if (state == `WBQSPI_READ_ID)
911
        begin
912
                o_wb_ack <= 1'b0; // Assuming we're still waiting
913
                o_wb_stall <= 1'b1;
914
 
915 4 dgisselq
                spi_wr <= 1'b0; // No more writes, we've already written the cmd
916 2 dgisselq
                spi_hold <= 1'b0;
917
                spif_req <= (spif_req) && (i_wb_cyc);
918
 
919
                // Here, we just wait until the result comes back
920
                // The problem is, the result may be the previous result.
921
                // So we use spi_len as an indicator
922
                spi_len <= 2'b00;
923
                if((spi_valid)&&(spi_len==2'b00))
924
                begin // Put the results out as soon as possible
925
                        o_wb_data <= spi_out[31:0];
926
                        o_wb_ack <= spif_req;
927
                        spif_req <= 1'b0;
928 4 dgisselq
                end else if ((~spi_busy)&&(o_qspi_cs_n))
929 2 dgisselq
                begin
930
                        state <= `WBQSPI_IDLE;
931
                        o_wb_stall <= 1'b0;
932
                end
933
        end else if (state == `WBQSPI_READ_STATUS)
934
        begin // We enter after the command has been given, for now just
935
                // read and return
936
                spi_wr <= 1'b0;
937
                o_wb_ack <= 1'b0;
938
                spi_hold <= 1'b0;
939
                spif_req <= (spif_req) && (i_wb_cyc);
940
                if (spi_valid)
941
                begin
942
                        o_wb_ack <= spif_req;
943
                        o_wb_stall <= 1'b1;
944
                        spif_req <= 1'b0;
945
                        last_status <= spi_out[7:0];
946
                        write_in_progress <= spi_out[0];
947
                        if (spif_addr[1:0] == 2'b00) // Local read, checking
948
                        begin // status, 'cause we're writing
949
                                o_wb_data <= { spi_out[0],
950
                                        dirty_sector, spi_busy,
951
                                        ~write_protect,
952
                                        quad_mode_enabled,
953
                                        7'h00,
954
                                        erased_sector, 14'h000 };
955
                        end else begin
956
                                o_wb_data <= { 24'h00, spi_out[7:0] };
957
                        end
958
                end
959
 
960
                if ((~spi_busy)&&(~spi_wr))
961
                        state <= `WBQSPI_IDLE;
962
        end else if (state == `WBQSPI_READ_CONFIG)
963
        begin // We enter after the command has been given, for now just
964
                // read and return
965
                spi_wr <= 1'b0;
966
                o_wb_ack <= 1'b0;
967
                o_wb_stall <= 1'b1;
968
                spi_hold <= 1'b0;
969
                spif_req <= (spif_req) && (i_wb_cyc);
970
 
971
                if (spi_valid)
972
                begin
973
                        o_wb_data <= { 24'h00, spi_out[7:0] };
974
                        quad_mode_enabled <= spi_out[1];
975
                end
976
 
977
                if ((~spi_busy)&&(~spi_wr))
978
                begin
979
                        state <= `WBQSPI_IDLE;
980
                        o_wb_ack   <= spif_req;
981
                        o_wb_stall <= 1'b0;
982
                        spif_req <= 1'b0;
983
                end
984
        end else if (state == `WBQSPI_WRITE_CONFIG)
985
        begin // We enter immediately after commanding a WEN
986
                o_wb_ack   <= 1'b0;
987
                o_wb_stall <= 1'b1;
988
 
989
                spi_len <= 2'b10;
990
                spi_in <= { 8'h01, last_status, spif_data[7:0], 8'h00 };
991
                spi_wr <= 1'b0;
992
                spi_hold <= 1'b0;
993
                spif_req <= (spif_req) && (i_wb_cyc);
994
                if ((~spi_busy)&&(~spi_wr))
995
                begin
996
                        spi_wr <= 1'b1;
997
                        state <= `WBQSPI_WAIT_TIL_IDLE;
998
                        write_in_progress <= 1'b1;
999
                        quad_mode_enabled <= spif_data[1];
1000
                end
1001
        end else if (state == `WBQSPI_WRITE_STATUS)
1002
        begin // We enter immediately after commanding a WEN
1003
                o_wb_ack   <= 1'b0;
1004
                o_wb_stall <= 1'b1;
1005
 
1006
                spi_len <= 2'b01;
1007
                spi_in <= { 8'h01, spif_data[7:0], 16'h00 };
1008
                // last_status <= i_wb_data[7:0]; // We'll read this in a moment
1009
                spi_wr <= 1'b0;
1010
                spi_hold <= 1'b0;
1011
                spif_req <= (spif_req) && (i_wb_cyc);
1012
                if ((~spi_busy)&&(~spi_wr))
1013
                begin
1014
                        spi_wr <= 1'b1;
1015
                        last_status <= spif_data[7:0];
1016
                        write_in_progress <= 1'b1;
1017
                        if(((last_status[6])||(last_status[5]))
1018
                                &&((~spif_data[6])&&(~spif_data[5])))
1019
                                state <= `WBQSPI_CLEAR_STATUS;
1020
                        else
1021
                                state <= `WBQSPI_WAIT_TIL_IDLE;
1022
                end
1023
        end else if (state == `WBQSPI_ERASE_CMD)
1024
        begin // Know that WIP is clear on entry, WEN has just been commanded
1025
                spi_wr     <= 1'b0;
1026
                o_wb_ack   <= 1'b0;
1027
                o_wb_stall <= 1'b1;
1028
                spi_hold   <= 1'b0;
1029
                spi_spd <= 1'b0;
1030
                spi_dir <= 1'b0;
1031
                spif_req <= (spif_req) && (i_wb_cyc);
1032
 
1033
                // Here's the erase command
1034
                spi_in <= { 8'hd8, 2'h0, spif_data[19:14], 14'h000, 2'b00 };
1035
                spi_len <= 2'b11; // 32 bit write
1036
                // together with setting our copy of the WIP bit
1037
                write_in_progress <= 1'b1;
1038
                // keeping track of which sector we just erased
1039
                erased_sector <= spif_data[19:14];
1040
                // and marking this erase sector as no longer dirty
1041
                dirty_sector <= 1'b0;
1042
 
1043
                // Wait for a full stop before issuing this command
1044
                if ((~spi_busy)&&(~spi_wr)&&(o_qspi_cs_n))
1045
                begin // When our command is accepted, move to the next state
1046
                        spi_wr <= 1'b1;
1047
                        state <= `WBQSPI_ERASE_BLOCK;
1048
                end
1049
        end else if (state == `WBQSPI_ERASE_BLOCK)
1050
        begin
1051
                spi_wr     <= 1'b0;
1052
                spi_hold   <= 1'b0;
1053
                o_wb_stall <= 1'b1;
1054
                o_wb_ack   <= 1'b0;
1055
                spif_req <= (spif_req) && (i_wb_cyc);
1056
                // When the port clears, we can head back to idle
1057
                if ((~spi_busy)&&(~spi_wr))
1058
                begin
1059
                        o_wb_ack <= spif_req;
1060
                        state <= `WBQSPI_IDLE;
1061
                end
1062
        end else if (state == `WBQSPI_CLEAR_STATUS)
1063
        begin // Issue a clear status command
1064
                spi_wr <= 1'b1;
1065
                spi_hold <= 1'b0;
1066
                spi_len <= 2'b00; // 8 bit command
1067
                spi_in <= { 8'h30, 24'h00 };
1068
                spi_spd <= 1'b0;
1069
                spi_dir <= 1'b0;
1070
                last_status[6:5] <= 2'b00;
1071
                spif_req <= (spif_req) && (i_wb_cyc);
1072
                if ((spi_wr)&&(~spi_busy))
1073
                        state <= `WBQSPI_WAIT_TIL_IDLE;
1074
        end else if (state == `WBQSPI_IDLE_CHECK_WIP)
1075
        begin // We are now in read status register mode
1076
 
1077
                // No bus commands have (yet) been given
1078
                o_wb_stall <= 1'b1;
1079
                o_wb_ack   <= 1'b0;
1080
                spif_req <= (spif_req) && (i_wb_cyc);
1081
 
1082
                // Stay in this mode unless/until we get a command, or
1083
                //      the write is over
1084
                spi_wr <= (((~i_wb_cyc)||((~i_wb_data_stb)&&(~i_wb_ctrl_stb)))
1085
                                &&(write_in_progress));
1086
                spi_len <= 2'b00; // 8 bit reads
1087
                spi_spd <= 1'b0;  // SPI, not quad
1088
                spi_dir <= 1'b1;  // Read
1089
                if (spi_valid)
1090
                begin
1091
                        write_in_progress <= spi_out[0];
1092
                        if ((~spi_out[0])&&(write_in_progress))
1093
                                o_interrupt <= 1'b1;
1094
                end else
1095
                        o_interrupt <= 1'b0;
1096
 
1097
                if ((~spi_wr)&&(~spi_busy)&&(o_qspi_cs_n))
1098
                begin // We can now go to idle and process a command
1099
                        o_wb_stall <= 1'b0;
1100
                        o_wb_ack   <= 1'b0;
1101
                        state <= `WBQSPI_IDLE;
1102
                end
1103
        end else // if (state == `WBQSPI_WAIT_TIL_IDLE) or anything else
1104
        begin
1105
                spi_wr     <= 1'b0;
1106
                spi_hold   <= 1'b0;
1107
                o_wb_stall <= 1'b1;
1108
                o_wb_ack   <= 1'b0;
1109
                spif_req   <= 1'b0;
1110
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
1111
                begin // clearing of the SPI port before moving on
1112
                        state <= `WBQSPI_IDLE;
1113
                        o_wb_stall <= 1'b0;
1114
                        o_wb_ack   <= 1'b0; // Shouldn't be acking anything here
1115
                end
1116
        end
1117 4 dgisselq
        end
1118 2 dgisselq
 
1119 4 dgisselq
        // Command and control during the reset sequence
1120
        assign  o_qspi_cs_n = (spif_override)?spif_cmd :w_qspi_cs_n;
1121
        assign  o_qspi_sck  = (spif_override)?spif_ctrl:w_qspi_sck;
1122
        assign  o_qspi_mod  = (spif_override)?   2'b01 :w_qspi_mod;
1123
        assign  o_qspi_dat  = (spif_override)?   4'b00 :w_qspi_dat;
1124 2 dgisselq
endmodule

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