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https://opencores.org/ocsvn/radiohdl/radiohdl/trunk
[/] [radiohdl/] [trunk/] [config/] [hdl_buildset_unb2b.cfg] - Blame information for rev 4
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danv |
# Uniboard 2b configuration
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buildset_name = unb2b
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technology_names = ip_arria10_e1sg
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family_names = arria10
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block_design_names = qsys
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synth_tool_name = quartus
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synth_tool_version = 18.0
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sim_tool_name = modelsim
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sim_tool_version = 10.4
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lib_root_dirs = ${RADIOHDL_WORK}/libraries ${RADIOHDL_WORK}/applications ${RADIOHDL_WORK}/boards
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[quartus]
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quartus_dir = ${ALTERA_DIR}/
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[modelsim]
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modelsim_dir = ${MENTOR_DIR}//questasim
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modelsim_platform = linux_x86_64
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modelsim_search_libraries =
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# arria10 only
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altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
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altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
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# both stratixiv and arria10
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#altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
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#altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip twentynm twentynm_hssi twentynm_hip
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