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Author E. Kooistra, ASTRON:
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This hdltool_readme.txt is a stripped down with left over content. All removed
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content is now moved and restructured in the RadioHDL markdown (*.md)
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documentation.
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Contents:
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1) Introduction
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2) Tool environment setup
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l) UniBoard2 device family
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m) Upgrading the IP for new version of Quartus or for another device family
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3) HDL environment configuration files
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b) Target configuration scripts
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c) hdl_buildset_.cfg key sections
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9) RadioHDL directory structure
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a) applications
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b) boards
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c) libraries
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d) software
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e) tools
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f) sub directories
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100) To do
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b) Generate Quartus IP key
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f) Improve support IP for multiple FPGA device types and Quartus tool versions
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g) Improve buildset_name scheme
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h) Declare IP libraries to ensure default binding in simulation.
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101) More ideas
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a) zip scripts
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b) support dynamic generation of IP
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c) Link RadioHDL developments with the OneClick MyHDL developments.
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102) Know errors
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2) Tool environment setup
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l) UniBoard2 device family
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The device family of the Arria10 on UniBoard2 v0 is 10AX115U4F45I3SGES as can be seen at the photo of the FPGA:
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$RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board_v0_device_family.JPG
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The device family is used in:
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- $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
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- QSYS IP component files
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- QSYS system design file
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m) Upgrading the IP for new version of Quartus or for another device family
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On 20 May 2015 Eric manually upgraded all current Arria10 IP to Quartus 15.0 and used the Qsys GUI menu view->device family to set the FPGA that is on UniBoard2 v0.
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These are the current Qsys IP components for ip_arria10:
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kooistra@dop233 ip_arria10 $ svn status -q
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M ddio/ip_arria10_ddio_in_1.qsys
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M ddio/ip_arria10_ddio_out_1.qsys
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M ddr4_4g_1600/ip_arria10_ddr4_4g_1600.qsys
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M ddr4_8g_2400/ip_arria10_ddr4_8g_2400.qsys
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M fifo/ip_arria10_fifo_dc.qsys
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M fifo/ip_arria10_fifo_dc_mixed_widths.qsys
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M fifo/ip_arria10_fifo_sc.qsys
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M flash/asmi_parallel/ip_arria10_asmi_parallel.qsys
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M flash/remote_update/ip_arria10_remote_update.qsys
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M mac_10g/ip_arria10_mac_10g.qsys
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M phy_10gbase_r/ip_arria10_phy_10gbase_r.qsys
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M phy_10gbase_r_24/ip_arria10_phy_10gbase_r_24.qsys
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M pll_clk125/ip_arria10_pll_clk125.qsys
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M pll_clk200/ip_arria10_pll_clk200.qsys
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M pll_clk25/ip_arria10_pll_clk25.qsys
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M pll_xgmii_mac_clocks/ip_arria10_pll_xgmii_mac_clocks.qsys
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M pll_xgmii_mac_clocks/pll_xgmii_mac_clocks.qsys
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M ram/ip_arria10_ram_cr_cw.qsys
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M ram/ip_arria10_ram_crw_crw.qsys
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M ram/ip_arria10_ram_crwk_crw.qsys
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M ram/ip_arria10_ram_r_w.qsys
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M transceiver_phy_1/transceiver_phy_1.qsys
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M transceiver_phy_48/transceiver_phy_48.qsys
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M transceiver_pll/transceiver_pll.qsys
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M transceiver_pll_10g/ip_arria10_transceiver_pll_10g.qsys
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M transceiver_reset_controller_1/ip_arria10_transceiver_reset_controller_1.qsys
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M transceiver_reset_controller_1/transceiver_reset_controller_1.qsys
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M transceiver_reset_controller_24/ip_arria10_transceiver_reset_controller_24.qsys
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M transceiver_reset_controller_48/ip_arria10_transceiver_reset_controller_48.qsys
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M transceiver_reset_controller_48/transceiver_reset_controller_48.qsys
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M tse_sgmii_gx/ip_arria10_tse_sgmii_gx.qsys
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M tse_sgmii_lvds/ip_arria10_tse_sgmii_lvds.qsys
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In addition several other files need to be modified to be able to simulate the IP:
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- the tech_*.vhd files that instantiate the IP component need to have the LIBRARY clause for binding
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- the compile_ip.tcl files need to be updated according to the generated/sim/mentor/msim_setup.tcl
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because the IP library name and file names may have changed
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. the copy_hex_files.tcl files need to be updated
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. the IP library name in the hdllib.cfg of the IP needs to be changed
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This concerned these files:
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kooistra@dop233 trunk $ svn status -q
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M libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd
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M libraries/technology/ddr/tech_ddr_arria10.vhd
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M libraries/technology/flash/tech_flash_asmi_parallel.vhd
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M libraries/technology/flash/tech_flash_remote_update.vhd
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M libraries/technology/ip_arria10/ddio/compile_ip.tcl
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M libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
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M libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
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M libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
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M libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
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M libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
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M libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
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M libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
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M libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
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M libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
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M libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
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M libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
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M libraries/technology/ip_arria10/mac_10g/hdllib.cfg
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M libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
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M libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
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M libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
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M libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
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M libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
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M libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
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M libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
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M libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
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M libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
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M libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
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M libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
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M libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
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M libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
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M libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
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M libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
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M libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
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M libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
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M libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
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M libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
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M libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
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M libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
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M libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
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M libraries/technology/mac_10g/tech_mac_10g_arria10.vhd
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M libraries/technology/pll/tech_pll_clk125.vhd
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M libraries/technology/pll/tech_pll_clk200.vhd
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M libraries/technology/pll/tech_pll_clk25.vhd
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M libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
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M libraries/technology/technology_select_pkg.vhd
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M libraries/technology/tse/tech_tse_arria10.vhd
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Then run generate-all-ip.sh and try to simulate the test benches that verify the IP:
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- tb_eth
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- tb_tr_10GbE
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- tb_io_ddr
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and the try to simulate a design, eg.:
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- unb2_minimal
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3) HDL environment configuration files
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b) Target configuration scripts
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t3. verify VHDL test benches in simulation - modelsim_regression_test_vhdl.py
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c) Replace SOPC avs2_eth_coe instance
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Replace in SOPC instance avs_eth_0 with avs_eth_coe by avs2_eth_coe. The eth now uses eth_pkg.vhd from
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$RADIOHDL. The avs_eth_coe still uses the eth_pkg.vhd from $UNB and this causes duplicate source file
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error in synthesis. Therefore open the SOPC GUI and replace the instance avs_eth_0 with avs_eth_coe by
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the avs2_eth_coe component.
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Make sure that the user_component.ipx is set up oke (see point 2e), because that is needed for SOPC to
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find the new avs2_eth_coe in $RADIOHDL.
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9) RadioHDL directory structure
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Currently, the RadioHDL SVN repository is contained within the UniBoard_FP7 SVN repository, at the following URL:
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https://svn.astron.nl/UniBoard_FP7/RadioHDL/trunk
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The above location might change in the future.
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The following sections describe the subdirectories that exist.
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a) applications//designs//revisions/
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/quartus
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/src
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/tb
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libraries/
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. Contains firmware applications designs, categorized by project.
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b) boards/
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/uniboard2a/designs/unb2a_led/quartus
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src
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tb
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/libraries/unb2a_board/quartus
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src
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tb
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. Contains board-specific support files and reference/testing designs
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. /designs/
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. Contains application designs that can be run on that board to test board-specific features.
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. /libraries/
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. Contains board-specific support files, such as firmware modules to communicate with board-specific ICs,
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constraint files, pinning files, board settings template files
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c) libraries//
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base
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dsp
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external
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io
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technology/...
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ip_arria10_e3sge3
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. See libraries_hierarchy_and_structure.jpg and readme_libraries.txt
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. Library of reusable firmware blocks, categorized by function and in which generic functionality is separated
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from technology. Within technology another seperation exists between generic technology and hardware-specific IP.
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. The library_category external/ contains HDL code that was obtained from external parties (e.g. open source).
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. //designs/
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. Contains reference designs to synthesize the library block for specific boards.
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d) software/
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. Intended for software that runs on a PC, such as control/monitoring of boards and programs to capture and process
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board output, e.g. sent via Ethernet to the processing machine.
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e) tools/
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. Contains the RadioHDL tools that are described in this readme file.
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f) sub directories
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The subdirectories that reoccur contain:
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- src/vhdl : contains vhdl source code that can be synthesised
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- tb/vhdl : contains vhdl source code that can is only for simulation (e.g. test benches, models, stubs)
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- quartus : synthesis specific settings for design that uses Quartus and an Altera FPGA
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- vivado : synthesis specific settings for design that uses Vivado and an Xilinx FPGA
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- revisions : contains revisions of a design that only differ in generic settign
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The separation of src/vhdl and tb/vhdl VHDL files is not mandatory, but can be convenient. An alternative
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would be to keep all VHDL in one vhdl/ sub directory. The hdl_lib_uses_synth key in hdllib.cfg typically
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contains the files from src/vhdl and the hdl_lib_uses_sim key typically contains the files from tb/vhdl.
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The synthesis will only see the VHDL files that are listed at the hdl_lib_uses_synth key, because the files
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at the hdl_lib_uses_sim key are not needed for synthesis and could even confuse synthesis (e.g. warnings that
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file IO ignored because it is not possible to synthesize).
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100) To do
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b) Generate Quartus IP key
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The generate_ip.sh scripts for generating the MegaWizard or QSYS IP components in fact are merely a wrapper script
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around the 'qmegawiz' and 'qsys-generate' commands. The generate_ip.sh may seem an unnecessary intermediate step if
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the IP is generated automatically. The IP could be generated automatically based on a megawizard key or a qsys key
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that has the description file as value.
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A disadvantage of the generate_ip.sh is that currently they use a fixed selection of the buildset_name, so they do not use
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the -t argument. An advantage of a generate_ip.sh script is that it can hide whether the MegaWizard or QSYS needs
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to be used to generate the IP, so in that way a 'quartus_generate_ip' key can fit both. Another advantage is that
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the generate_ip.sh can call 'qmegawiz' or 'qsys-generate' multiple time and with lots of arguments. Without
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generate_ip.sh this would become:
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quartus_generate_ip =
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qmegawiz filename and arguments
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qmegawiz filename and arguments
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Which is difficult to parse, because arguments can contain spaces and all arguments then have to be on one line.
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Within the cfg files only lists of values and lists of value pairs without spaces are supported.
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Therefore it is better to define a *_generate_ip key per generate IP tool. This is also more clear, because it shows
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in the cfg file which IP generation tool is used.
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The key values are the IP config files that need to be generated. First these IP config files need to be copied
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to the build dir using quartus_copy_files. The IP generate command options are then defined by the method that
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processes the qmegawiz_generate_ip or qsys_generate_ip key. The options can be complicated, but it appears that they
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are the same for all IP, so it is fine to define the options hard coded in the method or by some options txt file:
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qmegawiz_generate_ip =
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filename
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filename
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qsys_generate_ip = filename
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The 'quartus_copy_files' key is used to copy the IP generation source file and the generation script to the
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build directory.
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danv |
The '*_generate_ip' key identifies the tool script that needs to be ran when the IP has to be generated. The toolscript
|
289 |
|
|
can be a dedicated tool script per key, e.g.:
|
290 |
4 |
danv |
|
291 |
7 |
danv |
qmegawiz_generate_ip --> qmegawiz_generate_ip.py
|
292 |
|
|
qsys_generate_ip --> qsys_generate_ip.py
|
293 |
|
|
|
294 |
|
|
Eg. a
|
295 |
|
|
--generate_ip command line argument for quartus_config.py (rather than a separate quartus_generate_ip.py script)
|
296 |
|
|
can then generate the IP for all libraries that have such a key. The IP can then be generated outside the SVN tree.
|
297 |
|
|
The $IP_DIR path compile_ip.tcl needs to be adjusted to generated/ and the IP then gets generated in:
|
298 |
|
|
|
299 |
|
|
$RADIOHDL_BUILD_DIR//quartus//generated
|
300 |
|
|
|
301 |
4 |
danv |
For generated IP that is kept in SVN that IP could still remain there.
|
302 |
|
|
|
303 |
7 |
danv |
The hdllib.cfg should then also define a IP tool name subdirectory in build dir, eg.:
|
304 |
4 |
danv |
|
305 |
7 |
danv |
$RADIOHDL_BUILD_DIR// = $HDL_BUILD_DIR/qsys or
|
306 |
|
|
$HDL_BUILD_DIR/megawizard
|
307 |
4 |
danv |
|
308 |
|
|
or more general $RADIOHDL_BUILD_DIR/ip?
|
309 |
|
|
The $RADIOHDL_BUILD_DIR now has a modelsim and quartus subdir:
|
310 |
|
|
|
311 |
7 |
danv |
$RADIOHDL_BUILD_DIR//modelsim -- made by modelsim_config.py using sim_tool_name from hdl_buildset_.cfg
|
312 |
|
|
$RADIOHDL_BUILD_DIR//quartus -- made by quartus_config.py using synth_tool_name from hdl_buildset_.cfg
|
313 |
4 |
danv |
|
314 |
7 |
danv |
The IP can be put in a subdir using eg 'tool_name_ip' = quartus_ip:
|
315 |
4 |
danv |
|
316 |
7 |
danv |
$RADIOHDL_BUILD_DIR//quartus_ip -- made by quartus_config.py using a new tool_name_ip from hdl_buildset_.cfg
|
317 |
4 |
danv |
|
318 |
|
|
or can it be put in the synth_tool_name directory:
|
319 |
|
|
|
320 |
7 |
danv |
$RADIOHDL_BUILD_DIR//quartus
|
321 |
4 |
danv |
|
322 |
|
|
or do we need tool_name_megawizard and tool_name_qsys to be able to create:
|
323 |
|
|
|
324 |
7 |
danv |
$RADIOHDL_BUILD_DIR//
|
325 |
4 |
danv |
$RADIOHDL_BUILD_DIR/unb1/megawizard -- Altera MegaWizard
|
326 |
|
|
$RADIOHDL_BUILD_DIR/unb1/qsys -- Altera QSYS
|
327 |
|
|
$RADIOHDL_BUILD_DIR/unb1/coregen -- Xilinx
|
328 |
|
|
|
329 |
|
|
Probably it is not so important whether the IP is generated by MegaWizard or Qsys, because that selection is
|
330 |
7 |
danv |
already covered by the generate_ip.sh scripts. In the hdl_buildset_.cfg both MegaWizard and Qsys can be regarded as
|
331 |
|
|
being part of the Quartus tool. Therefore using tool_name_ip provides sufficient distinction in IP build
|
332 |
|
|
sub directory. However the IP could also be generated into the tool_name_synth build directory and then even
|
333 |
|
|
the tool_name_ip key is not needed, because the tool_name_synth sub directory also suits the Quartus IP
|
334 |
4 |
danv |
generation.
|
335 |
7 |
danv |
|
336 |
|
|
Assume that per IP HDL library there can only be one IP tool that generates the IP. This then implies that
|
337 |
|
|
it is not necessary to distinghuis between megawizard and qsys per HDL library.
|
338 |
4 |
danv |
|
339 |
|
|
Conclusion:
|
340 |
|
|
- Using synth_tool_name = quartus is also sufficient/suitable to define the build subdirectory for IP generation.
|
341 |
7 |
danv |
- Use dedicated key per IP generation tool:
|
342 |
|
|
. qmegawiz_generate_ip --> generate in //
|
343 |
|
|
. qsys_generate_ip --> generate in //
|
344 |
|
|
so assume that multiple generated IP they can share the generated directory, this
|
345 |
|
|
option in the method that treats the *_generate_ip key, so it could be different per IP generation tool.
|
346 |
|
|
- Use --generate_ip option with quartus_config.py to generate the IP. This option looks for the *_generate_ip keys
|
347 |
|
|
and then executes them. Default this option is not used, because it the IP only needs t obe generated once.
|
348 |
|
|
- Generated IP that is kept in SVN could be copied to the build dir, and then treated as if it was generated.
|
349 |
|
|
- The sim files of the generated IP are used by Modelsim as well, via compile_ip.tcl, it is oke that these
|
350 |
|
|
generated IP sim files are in the synth_tool_name dir.
|
351 |
|
|
- Having a dedicate tool_name_ip could be nice, to more clearly see in the build tree which libraries have IP and
|
352 |
|
|
to bring them at a the same level as sim_tool_name and synth_tool_name.
|
353 |
|
|
|
354 |
4 |
danv |
|
355 |
|
|
f) Improve support IP for multiple FPGA device types and Quartus tool versions
|
356 |
|
|
|
357 |
|
|
The IP is FPGA type specific (because it needs to be defined in the Qsys source file) and tool version specific
|
358 |
|
|
(because some parameters and even port IO may change). Currently there is only one IP directory per FPGA
|
359 |
|
|
technology (eg. ip_arria10) so there is no further separation into device family type and tool version. The
|
360 |
|
|
disadvantage of this scheme is that only one version of Quartus can be supported. For a minor version
|
361 |
|
|
change it may not be necessary to upgrade, but for a major version change or for a device family type (eg. from
|
362 |
|
|
engineering sample to production sample) change it probably is. To preserve the old version IP it is best to
|
363 |
|
|
treat the both the FPGA device version id and the Quartus tool version as a new technology. For example for
|
364 |
|
|
Arria10 we now use Quartus 15.0 and device family of UniBoard2 v0 and the IP for that is kept in:
|
365 |
|
|
|
366 |
7 |
danv |
$RADIOHDL/libraries/technology/ip_arria10/
|
367 |
4 |
danv |
|
368 |
|
|
This can be renamed in:
|
369 |
|
|
|
370 |
7 |
danv |
$RADIOHDL/libraries/technology/ip_arria10_device_10AX115U4F45I3SGES_quartus_15.0/
|
371 |
4 |
danv |
|
372 |
|
|
For a directory name it is allowed to use a '.' instead of a '_'. The directory name is not mandatory, but the name convention is
|
373 |
|
|
to define the FPGA technology as a triplet:
|
374 |
|
|
|
375 |
|
|
ip__device__quartus_
|
376 |
|
|
|
377 |
|
|
A future version of the IP can be kept in:
|
378 |
|
|
|
379 |
7 |
danv |
$RADIOHDL/libraries/technology/ip_arria10_device_10AX115U4F45I3SGES_quartus_16.0/
|
380 |
4 |
danv |
|
381 |
|
|
The technology_pkg.vhd then gets;
|
382 |
|
|
|
383 |
|
|
c_tech_arria10_device_10AX115U4F45I3SGES_quartus_14_1 = ...;
|
384 |
|
|
c_tech_arria10_device_10AX115U4F45I3SGES_quartus_15_0 = ...;
|
385 |
|
|
c_tech_arria10 = c_tech_arria10_device_10AX115U4F45I3SGES_quartus_15_0; -- optional default
|
386 |
|
|
|
387 |
|
|
The hdllib.cfg of the specific technology IP library then has key (only one value):
|
388 |
|
|
|
389 |
|
|
hdl_lib_technology = ip_arria10_device_10AX115U4F45I3SGES_quartus_15_0
|
390 |
|
|
|
391 |
7 |
danv |
The hdl_buildset_.cfg can support multiple technologies eg. to be able to simulate a system with more than one FPGA that are
|
392 |
4 |
danv |
of different technology (eg. an application with Uniboard1 and Uniboard2):
|
393 |
|
|
|
394 |
|
|
technology_names = ip_stratixiv
|
395 |
|
|
ip_arria10_device_10AX115U4F45I3SGES_quartus_15_0
|
396 |
|
|
|
397 |
|
|
All libraries that have hdl_lib_technology value that is not in the list of technology_names are removed from the dictionary list
|
398 |
|
|
by hdl_config.py, so these IP libraries will not be build.
|
399 |
|
|
|
400 |
|
|
The build directory currently contains:
|
401 |
|
|
|
402 |
7 |
danv |
$RADIOHDL_BUILD_DIR///
|
403 |
4 |
danv |
|
404 |
|
|
This scheme is probably still sufficent to also support the FPGA technology as a triplet. However it may be necessary to rename the
|
405 |
|
|
library key values in the IP hdllib.cfg to contain the full triplet information, so eg.
|
406 |
|
|
|
407 |
|
|
hdl_lib_name = ip_arria10_fifo
|
408 |
|
|
hdl_library_clause_name = ip_arria10_fifo_lib
|
409 |
|
|
|
410 |
|
|
then becomes:
|
411 |
|
|
|
412 |
|
|
hdl_lib_name = ip_arria10_device_10AX115U4F45I3SGES_quartus_15_0_fifo
|
413 |
|
|
hdl_library_clause_name = ip_arria10_device_10AX115U4F45I3SGES_quartus_15_0_fifo_lib
|
414 |
|
|
|
415 |
7 |
danv |
this is a bit awkward. If only one Quartus version and only one device type are supported per buildset_name, then all these versions can keep
|
416 |
4 |
danv |
the same basic hdl_lib_name and hdl_library_clause_name because the IP libraries that are not used can be removed from the build.
|
417 |
|
|
Alternatively the hdllib_config.py could support multiple technology version IP libraries that use the same logical library name and use
|
418 |
|
|
clause.
|
419 |
|
|
|
420 |
|
|
The purpose is to be able to handle in parallel different FPGA vendors, different FPGA types and different tool version. We do not have
|
421 |
|
|
to support all combinations, but only the combinations that we actually use. Eg. for the FPGA type this implies that we only support the FPGA types
|
422 |
|
|
that are actually used on our board. If we make a new board with another FPGA, then we add the technology triplet for that FPGA.
|
423 |
|
|
|
424 |
|
|
|
425 |
7 |
danv |
g) Improve buildset_name scheme
|
426 |
4 |
danv |
|
427 |
7 |
danv |
The buildset_name defines the combination of Modelsim version and Quartus version. Currently there are buildset_names 'unb1', 'unb2' and 'unb2a'. This
|
428 |
|
|
buildset_name scheme can be improved because:
|
429 |
4 |
danv |
|
430 |
7 |
danv |
- the buildset_names are tight to a board name 'unb1' (is that oke?) or should we use more general buildset_name names, or do we need a symbolic
|
431 |
|
|
buildset_name names at all?
|
432 |
|
|
- there is also a 'site' level in the bash scripts set_modelsim and set quartus (is that still needed?)
|
433 |
4 |
danv |
|
434 |
|
|
|
435 |
|
|
h) Declare IP libraries to ensure default binding in simulation.
|
436 |
|
|
|
437 |
|
|
Currently the IP library is declared in the technology VHDL file e.g. like 'LIBRARY ip_arria10_ddr4_4g_1600_altera_emif_150;' in tech_ddr_arria10.vhd.
|
438 |
|
|
This IP library clause is ignored by synthesis. The IP library must be mapped for simulation, because otherwise Modelsim gives
|
439 |
|
|
an error when it compiles the VHDL. Therefore the IP library can then not be excluded for simulation with 'hdl_lib_include_ip' key.
|
440 |
|
|
Alternatively the LIBRARY clause could be omitted if the IP library is added to the -L libraries search list of each simulation configuration the
|
441 |
|
|
Modelsim project file. This can be achieved adding the IP library to the modelsim_search_libraries key in the hdl_buildset_unb2.cfg. However the problem is
|
442 |
|
|
then that if the IP library is not mapped to a directory then Modelsim will issue an error when it tries to search it.
|
443 |
|
|
--> For now keep the 'hdl_lib_include_ip' but only use it for synthesis. For simulation the 'hdl_lib_include_ip' is ignored. Which is fine because
|
444 |
|
|
for simulation there is no need to exclude IP libraries.
|
445 |
7 |
danv |
|
446 |
4 |
danv |
101) More ideas
|
447 |
|
|
|
448 |
|
|
a) zip scripts
|
449 |
|
|
A zip script can gather all sources that are needed for a particular RadioHDL view point, eg.
|
450 |
|
|
|
451 |
|
|
- zip all required libraries for a certain level library --> useful for somebody who wants to reuse a HDL library.
|
452 |
|
|
- zip all code necessary to run Python test cases on HW target --> useful for somebody who only wants to use the HW.
|
453 |
|
|
- zip all tool environent code --> useful for somebody who wants to use our tool flow but not our HDL.
|
454 |
|
|
|
455 |
|
|
Related to this is (how) can we more clearly divide up the RadioHDL/ directory to eg. reuse only parts of it and
|
456 |
|
|
to develop these in other locations/repositories (eg. GIT). Eg. the applications/ directory may not be needed or
|
457 |
|
|
even suitable in RadioHDL/ because applications could be kept elsewhere, even in another repository at another
|
458 |
|
|
institute.
|
459 |
|
|
|
460 |
|
|
b) support dynamic generation of IP
|
461 |
|
|
Very preliminary ideas:
|
462 |
|
|
Currently the MegaWizard or QSYS component description file is fixed and created manually in advance via the
|
463 |
|
|
GUI. In future the component description file could be created based on parameters that are defined in the
|
464 |
|
|
hdllib.cfg or even parameters that depend on the requirements from the design. In a dynamic flow the hdllib.cfg
|
465 |
|
|
for IP could even not exist as a file, but only as a dictionary in the script.
|
466 |
|
|
|
467 |
|
|
c) Link RadioHDL developments with the OneClick MyHDL developments.
|
468 |
|
|
The hdllib.cfg dictionary format seems useful also in the OneClick flow. For some created libraries the hdllib.cfg
|
469 |
|
|
may not exist as a file and but only as the dictionary in the script. The various methods in modelsim_config.py
|
470 |
|
|
and quartus_config.py can also be reused in a OneClick flow.
|
471 |
|
|
|
472 |
|
|
|
473 |
|
|
102) Know errors
|
474 |
|
|
|
475 |
|
|
a) ** Fatal: Error occurred in protected context. when loading a simulation in Modelsim
|
476 |
|
|
- Example:
|
477 |
|
|
# Loading ip_stratixiv_phy_xaui_lib.ip_stratixiv_phy_xaui_0(rtl)
|
478 |
|
|
# ** Fatal: Error occurred in protected context.
|
479 |
|
|
# Time: 0 fs Iteration: 0 Instance: /tb_<...>//ip_stratixiv_phy_xaui_0_inst////// File: nofile
|
480 |
|
|
# FATAL ERROR while loading design
|
481 |
|
|
|
482 |
7 |
danv |
Make sure that the StratixIV IP search libraries are defined by modelsim_search_libraries in the hdl_buildset_.cfg.
|
483 |
|
|
|