OpenCores
URL https://opencores.org/ocsvn/radiohdl/radiohdl/trunk

Subversion Repositories radiohdl

[/] [radiohdl/] [trunk/] [doc/] [radiohdl_hdl_buildset_uniboard1.md] - Blame information for rev 7

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 7 danv
# RadioHDL buildset for UniBoard1
2
 
3
---
4
#### Document history:
5
|Revision|Date|Author|Affiliation|Modification|
6
|:---|:---|:---|:---|:---|
7
|1.0|27 jan 2020|E. Kooistra|ASTRON|Created.|
8
 
9
---
10
#### Contents:
11
1 Introduction
12
1.1 Scope
13
1.2 RadioHDL commands
14
2 Workflow
15
2.1 Preconditions
16
2.2 Setup RadioHDL
17
2.2.1 Source project settings
18
2.2.2 Source RadioHDL settings
19
2.3 Check the RadioHDL configuration
20
2.4 Create intermediate product files and project files
21
2.4.1 Compile standard Altera component libraries for Modelsim simulation
22
2.4.2 Pre-generate custom Altera IP blocks for simulation and synthesis
23
2.4.3 Create project files for simulation
24
2.4.4 Create project files for synthesis
25
2.4.5 Create an IP block design for a design library in your project
26
2.5 Simulate the HDL project
27
2.6 Synthesize the HDL project
28
3 Appendix: hdl_buildset_unb1.cfg
29
 
30
#### References:
31
[1] radiohdl_user_guide.md
32
[2] A. Gunst, A. Szomoru, G. Schoonderbeek, E. Kooistra, D. van der Schuur, H. Pepping, "The application of UniBoard as a beam former for APERTIF", Experimental Astronomy, Volume 37, Issue 1, pp 55-67, February 2014, doi:10.1007/s10686-013-9366-x.
33
[3] radiohdl_hdl_tool_modelsim.md
34
[4] radiohdl_hdl_tool_quartus.md
35
[5] radiohdl_hdl_buildset_key_descriptions.md
36
 
37
---
38
# 1 Introduction
39
 
40
## 1.1 Scope
41
The RadioHDL package offers scripts to ease and speed up HDL code development. The RadioHDL User Guide describes the general concept s of RadioHDL [1]. This RadioHDL for UniBoard1 user guide describes how to use RadioHDL for developing HDL applications on UniBoard1. The UniBoard1 [2] is an electronic board with 8 Altera Stratix IV FPGAs, that was developed by ASTRON and JIVE within the RadioNET FP7 program,
42
 
43
This user guide serves as an advanced start example for other projects. It describes how RadioHDL is used for the UniBoard1 at ASTRON (2019) to develop HDL firmware from source code to working FPGA image. There is too much HDL code involved and too much dependency on vendor tools to make this example publicly available as a working example. For a publicly working example please try the quick start example from [1].
44
 
45
## 1.2 RadioHDL commands
46
The HDL development for UniBoard1 involves vendor tools from Mentor/Modelsim for simulation and Intel/Altera for synthesis. For this RadioHDL offers the following command line commands:
47
 
48
* **check_config** to verify dependencies between hdl_buildset and hdl_tool configuration files
49
* **compile_altera_simlibs** to compile standard Altera component libraries for simulation with Modelsim
50
* **generate_ip_libs** to pre-generate customized IP components using Altera MegaWizard or Altera QSYS
51
* **modelsim_config** to create project files for Modelsim simulation
52
* **quartus_config** to create project files for Quartus synthesis
53
* **run_sopc** to generate a Altera SOPC memory mapped bus with NiosII
54
* **run_qsys** to generate a Altera QSYS memory mapped bus with NiosII
55
* **run_modelsim** to start Mentor Modelsim GUI for simulation
56
* **run_quartus** to start Altera Quartus GUI for synthesis
57
* **run_qcomp** to synthesize a top level design from the command line
58
* **run_rbf** to create an Altera FPGA rbf file from an FPGA sof file
59
 
60
The scripts that start with 'run_' typically are bash scripts that invoke tools. The other scripts are typically Python3 scripts that manage the build directory tree and e.g. tool project files. Please see [3] and [4] for more information on how to use Modelsim and Quartus with RadioHDL. Please see [5] for hdllib.cfg configuration file examples that are used by **generate_ip_libs**, **modelsim_config** and **quartus_config**.
61
 
62
---
63
## 2 Workflow
64
 
65
### 2.1 Preconditions
66
 
67
RadioHDL uses Python3 and bash. Python3 is used to interpret the configuration files and to create target files, bash is used to setup and invoke tools. Install a version of:
68
 
69
- Modelsim in $MENTOR_DIR/ (Modelsim version 6.6c or higher)
70
- Quartus in $ALTERA_DIR (version 11.1 for UniBoard1)
71
 
72
and take care of all vendor specific environment variables in your own .bashrc or local .profile file. For example Altera and Modelsim needs the key LM_LICENSE_FILE to be defined. So the .bashrc file contains the lines:
73
 
74
> export MENTOR_DIR=
75
> export ALTERA_DIR=
76
> export MODELSIM_ALTERA_LIBS_DIR=
77
> export LM_LICENSE_FILE=
78
 
79
 
80
### 2.2 Setup RadioHDL
81
 
82
#### 2.2.1 Source Project settings
83
The UniBoard1 HDL source code is available in a source directory tree at hdl/. Setup RadioHDL development environment for a project at hdl/ using a corresponding init_hdl.sh.
84
 
85
> \> cd /hdl
86
> \> . ./init_hdl.sh
87
 
88
The init_hdl.sh defines:
89
 
90
- RADIOHDL_WORK directory for where the source code resides
91
- RADIOHDL_BUILD_DIR directory for where the targets will be build
92
 
93
The init_hdl.sh copies version controlled ${RADIOHDL_WORK}/hdl_user_components.ipx into the Altera dir's at $ALTERA_DIR//ip/altera/user_components.ipx. This Altera user_components.ipx contains the search paths that Altera SOPC builder and Altera QSYS use.
94
 
95
> **NOTE:** Altera says that you can use your personal user_components.ipx file in ~/.altera.quartus/ip//ip_search_path for this kind of additional paths but tests show that this does not work for all tools of Altera. Therefore the user_components.ipx file is copied to the Altera installation directory.
96
 
97
#### 2.2.2 Source RadioHDL settings
98
 
99
The init_hdl.sh can automatically also source init_radiohdl.sh, or source these RadioHDL settings separately:
100
 
101
> \> . /init_radiohdl.sh
102
 
103
The init_radiohdl.sh from the RadioHDL package defines:
104
 
105
- RADIOHDL_GEAR directory of where the init_radiohdl.sh is located
106
- RADIOHDL_BUILD_DIR = ${RADIOHDL_BUILD_DIR}/build if not already defined
107
- RADIOHDL_CONFIG = ${RADIOHDL_GEAR}/config if not already defined
108
 
109
The init_radiohdl.sh extends:
110
 
111
- PATH with ${RADIOHDL_GEAR}/core, ${RADIOHDL_GEAR}/quartus, ${RADIOHDL_GEAR}/modelsim
112
- PYTHONPATH with ${RADIOHDL_GEAR}/core, ${RADIOHDL_GEAR}/components
113
 
114
### 2.3 Check the RadioHDL configuration
115
 
116
The hdl_buildset_unb1.cfg defines the buildset 'unb1' for build target files for UniBoard1. Since there are some dependencies between the hdl_buildset configuration file and the hdl_tool configuration files there is a utility that checks (most) values in these files. To check the content of the file hdl_buildset_unb1.cfg and the hdl_tool_modelsim.cfg and hdl_tool_quartus.cfg files it refers to do
117
 
118
> \> check_config unb1
119
 
120
Once the configuration files are correct you can start using the RadioHDL utilities.
121
 
122
 
123
### 2.4 Create intermediate product files and project files
124
 
125
#### 2.4.1 Compile standard Altera component libraries for Modelsim simulation
126
 
127
This only needs to be done once when a new version of Modelsim or new version of Quartus is used.
128
 
129
> \> compile_altera_simlibs unb1
130
- creates build/unb1/hdl_libraries_ip_stratixiv.txt
131
- creates build/quartus/ simulation models of Altera components that need to be moved manually using 'mv' or 'sudo mv' to $MODELSIM_ALTERA_LIBS_DIR/, because that is where Modelsim expects them.
132
 
133
> **NOTE:** For Modelsim versions newer than about version10 this compile_altera_simlibs script must be used and not the tools/Launch simulation library compiler in the Quartus GUI, because the libraries have to be compiled with the 'vlib -type directory' option to be able to use 'mk all' in Modelsim.
134
 
135
#### 2.4.2 Pre-generate custom Altera IP blocks for simulation and synthesis
136
 
137
The custom IP needs to be generated before it can be simulated or synthesized. To make all custom IP libraries for the 'unb1' buildset do:
138
 
139
> \> generate_ip_libs unb1
140
- creates build/unb1/qmegawiz/
141
 
142
> **NOTE:** The Altera tools make use of the /tmp directory intensively. Unfortunately these tools do not cleanup the files they created there. We ran into major problems when working with more than one user on the same machine:
143
> 1. /tmp/compute_pll_temp and /tmp must have write-access for anyone (rwxrwxrwx)
144
> 2. run 'rm -rf /tmp/alt* /tmp/public*' before running generate_ip_libs
145
 
146
 
147
#### 2.4.3 Create project files for simulation
148
 
149
> \> modelsim_config unb1
150
- creates build/unb1/modelsim/ with Modelsim project files (mpf) for simulation
151
- creates build/unb1/modelsim/modelsim_project_files.txt for Modelsim commands.do, that lists all HDL libraries in their hierarchical order for compilation.
152
- creates build/unb1/modelsim/technology_select_pkg.vhd to select stratixiv technology for UniBoard1
153
 
154
 
155
#### 2.4.4 Create project files for synthesis
156
 
157
> \> quartus_config unb1
158
- creates build/unb1/quartus/ with Quartus files for synthesis
159
- creates build/unb1/quartus/technology_select_pkg.vhd to select stratixiv technology for UniBoard1
160
 
161
The quartus_config creates the Quartus qpf, qsf for a top level design library and Quartus qip files all libraries. If a new VHDL file is added to a library or if a filename is changed, then it is necessary to rerun the quartus_config. Typically it is not necessary to do delete the entire $RADIOHDL_BUILD_DIR library of the design directory, but it can be necessary to make sure that Quartus is not 'confused' by obsolete files in that build directory. Make sure that any image files that needs to be kept are saved elsewhere, before deleting the build directory of the design library.
162
 
163
 
164
#### 2.4.5 Create an IP block design for a design library in your project
165
 
166
Dependent of which tool you like to use you can run run_sopc (older) or run_qsys (newer) to generate the control interface of your design.
167
 
168
> \> run_sopc unb1 unb1_minimal_sopc
169
- creates memory mapped bus block with NiosII master using Altera SOPC
170
 
171
> \> run_qsys unb1 unb1_minimal_qsys
172
- creates memory mapped bus block with NiosII master using Altera QSYS
173
 
174
Syntax:
175
 
176
> run_qsys   []
177
> run_sopc   []
178
 
179
Both utilities only differ in name not in functionality. The  is a HDL library directory that needs to exist under $RADIOHDL_BUILD_DIR/${buildset}/quartus. If no  respectively  is specified during the invocation, then the utility will look for a file with the name .qsys or .sopc in the project directory.
180
 
181
After generating all necessary files the utility will also build the software for the NiosII application using the RadioHDL run_app script. This run_app calls run_bsp and run_reg. The run_reg calls run_mif. For the FPGA designs on UniBoard the NiosII software application is fixed, because it implements the monitoring and control protocol interface between the 1GbE port and the memory mapped bus that is generated by SOPC or QSYS. The NiosII is the master on the memory mapped bus, and the slaves are configurable dependent on the design.
182
 
183
> **NOTE:** The sopc_builder from Altera uses Java and Java expects that it is started from an Xterm (environment DISPLAY must be set) otherwise it stops with an error.
184
 
185
 
186
### 2.5 Simulate the HDL project
187
 
188
To simulate test benches within the hdl project for UniBoard using the Modelsim GUI do:
189
 
190
> \> run_modelsim unb1 &
191
 
192
In simulation the entire unb1_minimal design can be simulated. The NiosII and memory mapped bus are not simulated. Instead the access to the memory mapped slaves is simulated using file IO.
193
 
194
### 2.6 Synthesize the HDL project
195
 
196
The way to start quartus is using the script **run_quartus**. This script sets up the environment variables that match the buildset and then start quartus itself. To synthesize a top level design within the hdl project for UniBoard using the Quartus GUI do:
197
 
198
> \> run_quartus unb1 &
199
 
200
To synthesize the unb1_minimal_sopc top level design from the command line do:
201
 
202
> \> run_qcomp unb1 unb1_minimal_sopc
203
 
204
To synthesize the unb1_minimal_qsys top level design from the command line do:
205
 
206
> \> run_qcomp unb1 unb1_minimal_qsys
207
 
208
The run_qcomp script can also rerun the synthesis for multiple seeds by using its --seed option. To translate the FPGA image sof file into an rbf file for use in a flash on UniBoard do:
209
 
210
> \> run_rbf unb1 unb1_minimal_sopc
211
> \> run_rbf unb1 unb1_minimal_qsys
212
 
213
---
214
## 3 Appendix: hdl_buildset_unb1.cfg
215
 
216
Buildset configuration file for Uniboard1 from $RADIOHDL_GEAR/config.
217
```
218
buildset_name             = unb1
219
technology_names          = ip_stratixiv
220
family_names              = stratixiv
221
block_design_names        = sopc
222
 
223
synth_tool_name           = quartus
224
synth_tool_version        = 11.1
225
sim_tool_name             = modelsim
226
sim_tool_version          = 6.6c
227
 
228
lib_root_dirs             = ${RADIOHDL_WORK}/libraries
229
                            ${RADIOHDL_WORK}/applications
230
                            ${RADIOHDL_WORK}/boards
231
 
232
[quartus]
233
quartus_dir               = ${ALTERA_DIR}/
234
 
235
[modelsim]
236
modelsim_dir              = ${MENTOR_DIR}//modeltech
237
modelsim_platform         = linux_x86_64
238
modelsim_search_libraries =
239
    # stratixiv only
240
    altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver
241
    stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
242
    altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi
243
    stratixiv_pcie_hip
244
```
245
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.