OpenCores
URL https://opencores.org/ocsvn/radiohdl/radiohdl/trunk

Subversion Repositories radiohdl

[/] [radiohdl/] [trunk/] [ise/] [hdl_libraries_ip_virtex4.txt] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 danv
# Used by modelsim_config.py to create library paths in the HDL library project files
2
# VHDL
3
unisim = $MODEL_TECH_XILINX_LIB/vhdl/unisim
4
unimacro = $MODEL_TECH_XILINX_LIB/vhdl/unimacro
5
simprim = $MODEL_TECH_XILINX_LIB/vhdl/simprim
6
xilinxcorelib = $MODEL_TECH_XILINX_LIB/vhdl/XilinxCoreLib
7
secureip = $MODEL_TECH_XILINX_LIB/vhdl/secureip
8
aim = $MODEL_TECH_XILINX_LIB/vhdl/abel/aim
9
pls = $MODEL_TECH_XILINX_LIB/vhdl/abel/pls
10
cpld = $MODEL_TECH_XILINX_LIB/vhdl/cpld
11
 
12
# Verilog
13
unisims_ver = $MODEL_TECH_XILINX_LIB/verilog/unisims_ver
14
unimacro_ver = $MODEL_TECH_XILINX_LIB/verilog/unimacro_ver
15
uni9000_ver = $MODEL_TECH_XILINX_LIB/verilog/uni9000_ver
16
simprims_ver = $MODEL_TECH_XILINX_LIB/verilog/simprims_ver
17
xilinxcorelib_ver = $MODEL_TECH_XILINX_LIB/verilog/XilinxCoreLib_ver
18
aim_ver = $MODEL_TECH_XILINX_LIB/verilog/aim_ver
19
cpld_ver = $MODEL_TECH_XILINX_LIB/verilog/cpld_ver

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.