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[/] [radiohdl/] [trunk/] [quartus/] [compile_altera_simlibs] - Blame information for rev 4

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1 4 danv
#!/bin/bash -eu
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###############################################################################
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#
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# Copyright (C) 2014-2018
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# ASTRON (Netherlands Institute for Radio Astronomy) 
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# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program.  If not, see .
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#
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# $Id$
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#
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###############################################################################
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# Purpose: Compile the Altera simulation libraries
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# Description:
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#   This script is equivalent to manually running the Quartus GUI tools/Launch simulation library compiler.
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#   However it is needed to use this script, because then the Altera libraries can be compiled with the 'vlib -type directory' option.
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#   Default 'vlib' compiles all components into a single binary but to be able to use 'mk all' it is necessary that each component
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#   is compiled into a seperate binary.
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#   Therefore this script uses 'sed' to replace 'vlib' by 'vlib -type directory' in the created Modelsim .do file and then
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#   it then runs the .do file. This needs to be done for all families (arria10) and all HDL (vhdl and verilog).
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#
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#   > run_altera_simlib_comp unb2
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#
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#   Then use 'sudo' to move the directory to the protected central project directory that is set by $MODEL_TECH_ALTERA_LIB.
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#
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# read generic functions/definitions
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. ${RADIOHDL_GEAR}/generic.sh
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# check the positional parameters
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if [ $# -ne 1 ]; then
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    hdl_error $0 "Syntax: $0 buildset"
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fi
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buildset=$1
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# read in the configuration based on the user arguments
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. ${RADIOHDL_GEAR}/quartus/set_quartus ${buildset}
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. ${RADIOHDL_GEAR}/modelsim/set_modelsim ${buildset}
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# Select output directory for the library compilation results
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buildset_config_file="${RADIOHDL_CONFIG}/hdl_buildset_${buildset}.cfg"
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. ${RADIOHDL_GEAR}/set_config_variable $buildset_config_file synth_tool_name,synth_tool_version
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OUTPUT_DIR=${RADIOHDL_BUILD_DIR}/${SYNTH_TOOL_NAME}/${SYNTH_TOOL_VERSION}
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mkdir -p ${OUTPUT_DIR}
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mkdir -p ${RADIOHDL_BUILD_DIR}/${buildset}
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# Select FPGA device family for the library compilation
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. ${RADIOHDL_GEAR}/set_config_variable $buildset_config_file family_names
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echo ""
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echo "Create Altera libraries for simulation with the following settings:"
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echo "    - Buildset target     : ${buildset}"
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echo "    - Output directory    : ${OUTPUT_DIR}"
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echo "    - FPGA device families: ${FAMILY_NAMES}"
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echo ""
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for FAMILY in $FAMILY_NAMES
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do
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    # 2) Create Modelsim .do file for compiling the Altera simulation libraries
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    # . verilog
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    quartus_sh --simlib_comp -family ${FAMILY} \
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                             -tool modelsim \
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                             -tool_path $MODELSIM_DIR/$MODELSIM_PLATFORM \
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                             -language verilog \
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                             -directory ${OUTPUT_DIR} \
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                             -log ${OUTPUT_DIR}/${FAMILY}_verilog.log \
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                             -cmd_file ${FAMILY}_verilog.do \
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                             -gen_only \
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                             -suppress_messages
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    # . vhdl
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    quartus_sh --simlib_comp -family ${FAMILY} \
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                             -tool modelsim \
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                             -tool_path $MODELSIM_DIR/$MODELSIM_PLATFORM \
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                             -language vhdl \
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                             -directory ${OUTPUT_DIR} \
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                             -log ${OUTPUT_DIR}/${FAMILY}_vhdl.log \
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                             -cmd_file ${FAMILY}_vhdl.do \
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                             -gen_only \
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                             -suppress_messages
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    # Go to the output directory
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    cd ${OUTPUT_DIR}
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    # 3) Now use sed to replace 'vlib' by 'vlib -type directory'
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    # TODO: unb1 dependancy!!!
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    if [ "${buildset}" != "unb1" ]; then
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      sed -i 's/vlib/vlib -type directory/g' ${FAMILY}_verilog.do
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      sed -i 's/vlib/vlib -type directory/g' ${FAMILY}_vhdl.do
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    fi
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    # 4) Compile the Altera libraries with Modelsim
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    $MODELSIM_DIR/$MODELSIM_PLATFORM/vsim -c -do ${FAMILY}_verilog.do
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    $MODELSIM_DIR/$MODELSIM_PLATFORM/vsim -c -do ${FAMILY}_vhdl.do
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    # 5) Leave files for modelsim_config
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    libraryfile=${RADIOHDL_BUILD_DIR}/${buildset}/hdl_libraries_ip_${FAMILY}.txt
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    rm -f ${libraryfile}
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    grep vmap ${OUTPUT_DIR}/${FAMILY}_*.do | sort | \
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         sed "s?${OUTPUT_DIR}?\$MODEL_TECH_ALTERA_LIB?g" | while read vmap label location
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    do
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        echo "$label = $location" | sed "s/\"//g" >> ${libraryfile}
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    done
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    echo "Created ${libraryfile} for modelsim_config"
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done
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# 5) Show all errors and warnings that occured during the comiplation
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echo
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echo "The following warnings and error occured during the compilation:"
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grep -i -e Warning: -e Error: -B1 ${OUTPUT_DIR}/transcript
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# 6) Give user a hint what to do next
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echo
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echo "To finish the compilation move the directory with the compiled files to /home/software/modelsim_altera_libs with:"
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tput bold
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echo "sudo mv ${OUTPUT_DIR} `dirname ${MODEL_TECH_ALTERA_LIB}`"
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tput init
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