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[/] [rf6809/] [trunk/] [rtl/] [noc/] [memory/] [demomem.sv] - Blame information for rev 19

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1 19 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2012-2022  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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//
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module demomem(rst_i, clk_i, cti_i, bok_o, cs_i, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i, dat_o, sp);
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input rst_i;
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input clk_i;
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input [2:0] cti_i;
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output bok_o;
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input cs_i;
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input cyc_i;
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input stb_i;
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output ack_o;
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input we_i;
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input [13:0] adr_i;
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input [11:0] dat_i;
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output reg [11:0] dat_o;
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input [23:0] sp;
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integer n;
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reg [11:0] rommem [16383:0];
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reg [13:0] radr;
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initial begin
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        for (n = 0; n < 16384; n = n + 1)
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                rommem[n] <= 12'h00;
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`include "d:/cores2022/rf6809/software/boot/demo.ver";
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end
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wire cs = cs_i && cyc_i && stb_i;
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assign bok_o = cs_i;
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reg csd = 1'b0;
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reg wed = 1'b0;
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reg [13:0] adrd = 16'h00;
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reg [11:0] datid = 8'h00;
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reg [11:0] datod = 8'h00;
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reg [2:0] cnt;
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/*
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reg rdy,rdy1;
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always @(posedge clk_i)
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if (rst_i) begin
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        rdy1 <= 1'b0;
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        rdy <= 1'b0;
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end
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else begin
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        rdy1 <= cs;
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        rdy <= rdy1 & cs && cnt!=3'b101;
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end
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assign ack_o = cs ? (we_i ? 1'b1 : rdy) : 1'b0;
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*/
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ack_gen #(
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        .READ_STAGES(2),
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        .WRITE_STAGES(1),
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        .REGISTER_OUTPUT(1)
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) ag1
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(
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        .clk_i(clk_i),
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        .ce_i(1'b1),
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        .i(cs && cnt != 3'b101),
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        .we_i(we_i && cs && cnt != 3'b101),
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        .o(ack_o),
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        .rid_i(0),
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        .wid_i(0),
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        .rid_o(),
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        .wid_o()
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);
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always @(posedge clk_i)
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        csd <= cs;
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always @(posedge clk_i)
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        wed <= we_i;
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always @(posedge clk_i)
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        adrd <= adr_i;
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always @(posedge clk_i)
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        datid <= dat_i;
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always @(posedge clk_i)
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        if (cs & we_i) begin
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                $display ("wrote to scratchmem: %h=%h", adr_i, dat_i);
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                /*
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                if (adr_i[14:3]==15'h3e9 && dat_i==64'h00) begin
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                  $display("3e9=00");
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                  $finish;
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                end
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                */
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        end
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genvar g;
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generate begin : gRom
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for (g = 0; g < 1; g = g + 1)
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always @(posedge clk_i)
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        if (csd & wed)
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                rommem[adrd[13:0]][g*12+11:g*12] <= datid[g*12+11:g*12];
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end
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endgenerate
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wire pe_cs;
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edge_det u1(.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(cs), .pe(pe_cs), .ne(), .ee() );
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reg [13:0] ctr;
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always @(posedge clk_i)
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if (rst_i) begin
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        cnt <= 3'd0;
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        ctr <= 14'd0;
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end
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else begin
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        if (pe_cs) begin
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                if (cti_i==3'b000)
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                        ctr <= adr_i[13:0];
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                else
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                        ctr <= adr_i[13:0] + 12'd1;
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                cnt <= 3'b000;
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        end
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        else if (cs && cnt[2:0]!=3'b100 && cti_i!=3'b000) begin
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                ctr <= ctr + 2'd1;
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                cnt <= cnt + 3'd1;
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        end
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end
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always @(posedge clk_i)
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        radr <= pe_cs ? adr_i[13:0] : ctr;
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//assign dat_o = cs ? {smemH[radr],smemG[radr],smemF[radr],smemE[radr],
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//                              smemD[radr],smemC[radr],smemB[radr],smemA[radr]} : 64'd0;
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reg [13:0] spr;
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always @(posedge clk_i)
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        spr <= sp[13:0];
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always @(posedge clk_i)
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if (rst_i)
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        datod <= 12'h00;
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else begin
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        datod <= rommem[radr];
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        if (!we_i & cs)
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                $display("read from scratchmem: %h=%h", radr, rommem[radr]);
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//      $display("-------------- Stack --------------");
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//      for (n = -6; n < 8; n = n + 1) begin
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//              $display("%c%c %h %h", n==0 ? "-": " ", n==0 ?">" : " ",spr + n, rommem[spr+n]);
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//      end
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end
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always @(posedge clk_i)
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if (rst_i)
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        dat_o <= 12'h00;
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else begin
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        if (cs_i)
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                dat_o <= datod;
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        else
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                dat_o <= 12'd0;
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end
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endmodule
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