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[/] [rf6809/] [trunk/] [rtl/] [noc/] [video/] [rfVideoFifo.v] - Blame information for rev 19

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1 19 robfinch
`timescale 1ns / 1ps
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2008-2021  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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//
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//      Verilog 1995
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//
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// ============================================================================
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//
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module rfVideoFifo(wrst, wclk, wr, di, rrst, rclk, rd, dout, cnt);
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parameter WID=128;
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input wrst;
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input wclk;
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input wr;
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input [WID-1:0] di;
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input rrst;
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input rclk;
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input rd;
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output [WID-1:0] dout;
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output [7:0] cnt;
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reg [7:0] cnt;
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reg [7:0] wr_ptr;
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reg [7:0] rd_ptr,rrd_ptr;
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reg [WID-1:0] mem [0:255];
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wire [7:0] wr_ptr_p1 = wr_ptr + 8'd1;
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wire [7:0] rd_ptr_p1 = rd_ptr + 8'd1;
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reg [7:0] rd_ptrs;
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always @(posedge wclk)
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        if (wrst)
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                wr_ptr <= 8'd0;
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        else if (wr) begin
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                mem[wr_ptr] <= di;
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                wr_ptr <= wr_ptr_p1;
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        end
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always @(posedge wclk)          // synchronize read pointer to wclk domain
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        rd_ptrs <= rd_ptr;
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always @(posedge rclk)
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        if (rrst)
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                rd_ptr <= 8'd0;
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        else if (rd)
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                rd_ptr <= rd_ptr_p1;
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always @(posedge rclk)
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        rrd_ptr <= rd_ptr;
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assign dout = mem[rrd_ptr[7:0]];
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always @(wr_ptr or rd_ptrs)
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        if (rd_ptrs > wr_ptr)
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                cnt <= wr_ptr + (9'd256 - rd_ptrs);
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        else
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                cnt <= wr_ptr - rd_ptrs;
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endmodule

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