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------------------------------ Remark ----------------------------------------
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This code is a generic code written in RobustVerilog. In order to convert it to Verilog a RobustVerilog parser is required.
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It is possible to download a free RobustVerilog parser from www.provartec.com/edatools.
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We will be very happy to receive any kind of feedback regarding our tools and cores.
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We will also be willing to support any company intending to integrate our cores into their project.
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For any questions / remarks / suggestions / bugs please contact info@provartec.com.
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RobustVerilog generic AXI interconnect fabric
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In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)).
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The RobustVerilog top source file is ic.v, it calls the top definition file named def_ic.txt.
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The default definition file def_ic.txt generates a fabric with 3 masters and 6 slaves.
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Changing the interconnect parameters should be made only in def_ic.txt in the src/base directory (changing master num, slave num etc.).
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